KR100318311B1 - Method of forming a silicide layer in semiconductor devices - Google Patents

Abstract

The present invention relates to a method of forming a silicide layer of a semiconductor device, and in particular, to form a polyside-type gate including a silicide layer, forming a first gate pattern having a double sidewall spacer made of an insulating material having a high etching selectivity. After removing a portion of the inner insulating material of the double sidewall spacer to extend the exposed portion of the first gate pattern, and then grow an epitaxial layer on the exposed first gate pattern surface to form a second gate pattern, and then to form a silicide to uniformity of the silicide The present invention relates to a method for forming a salicide layer of a semiconductor device to ensure the resistance and greatly reduce the resistance due to the high integration of the device. The silicide layer forming method according to the present invention comprises the steps of: forming a gate made of the semiconductor via a gate insulating film on a predetermined portion of the semiconductor substrate, and forming a pair of impurity diffusion regions corresponding to each other on the substrate at the lower side of the gate side; Forming a first sidewall spacer formed of a first insulating film on the side of the gate, and exposing a top surface of the first sidewall spacer with a second insulating film on the side of the first sidewall spacer. Forming a spacer, removing a portion of the exposed portion of the first sidewall spacer to form a space for increasing the exposed area of the gate, and forming a spacer on the exposed gate surface and the exposed impurity diffusion region. Respectively forming a first semiconductor layer and a second semiconductor layer made of the semiconductor; A first retardation to between the semiconductor layer and the second semiconductor layer and the metal silica comprises a step of forming a first silicide layer and a second silicide layers, respectively.

Description

Method for forming silicide layer of semiconductor device {METHOD OF FORMING A SILICIDE LAYER IN SEMICONDUCTOR DEVICES}

The present invention relates to a method of forming a silicide layer of a semiconductor device, and in particular, to form a polyside-type gate including a silicide layer, forming a first gate pattern having a double sidewall spacer made of an insulating material having a high etching selectivity. After removing a portion of the inner insulating material of the double sidewall spacer to extend the exposed portion of the first gate pattern, and then grow an epitaxial layer on the exposed first gate pattern surface to form a second gate pattern, and then to form a silicide to uniformity of the silicide The present invention relates to a method for forming a salicide layer of a semiconductor device to ensure the resistance and greatly reduce the resistance due to the high integration of the device.

As semiconductor devices are highly integrated, the widths of impurity regions and gates used as source and drain regions are reduced. As a result, the semiconductor device has a problem in that an operating speed decreases due to an increase in contact resistance of an impurity region and sheet resistance of a gate.

Therefore, when the wirings of the elements in the semiconductor device are formed of a low resistance material such as aluminum alloy and tungsten, or when the gate electrode is formed of polysilicon, a silicide layer is formed to reduce the resistance. When the silicide layer is formed on the gate formed of polycrystalline silicon, a silicide layer is also formed on the surface of the impurity region to reduce the contact resistance.

As described above, as the design rules of the semiconductor devices become more stringent, high sheet resistance at the gate becomes a major cause of lowering the operation speed of the devices. Therefore, fabrication of the low resistance gate electrode is essential for improving the device operation speed. In order to improve the resistance, a gate electrode having a silicide (refractory metal silicide) formed of a heat resistant metal having a low specific resistance is manufactured. The gate electrode having such a structure is called a polycide (silicide on doped polycrystalline silicon) gate electrode.

WSi ₂ is most widely used to form polyside structures, but as the integration of devices increases and the area occupied by unit devices decreases, formation of silicides having lower resistance values is required. At this time, the specific resistance value of WSi2 is 60-200 micrometer-cm. The most likely is that the silicide of the response to this demand, a CoSi ₂ and TiSi _2, those of specific resistance value is 15 to 20μΩ-㎝.

The method of forming a polyside structure can be broadly divided into two methods.

First, a metal layer is deposited on a conductive doped polysilicon layer and then heat-treated to form silicide by reaction of metal and silicon. However, the silicide of the metal-silicon formed at this time is difficult to form a silicide layer having a thick and uniform thickness.

In general, the reaction between pure metal and silicon is very violent, so that the interfacial morphology of silicide and silicon becomes rough, which makes it difficult to accurately pattern the gate electrode. In this regard, J.S. Byun et al. J. Electrochem. Soc., Vol. 144,3175 (1997)] dp.

In addition, since highly doped polysilicon and metal react, it is difficult to form uniform silicide due to the high concentration of dopant.

Second, there is a method of depositing a silicide material directly on a conductive doped polysilicon layer instead of a thermal process. In general, a silicide layer is directly formed on a polysilicon layer doped by a sputtering method using a silicide composite target. However, this method generates particles upon silicide formation. That is, since the sputtering rate of each element is different in the composite target composed of two components, metal and silicon, it is difficult to deposit silicide of uniform composition and generate particles.

1A to 1E are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the related art.

Referring to FIG. 1A, a field oxide film (not shown) is formed on a predetermined portion of a silicon substrate 10, which is a semiconductor substrate, by a device isolation method such as LOCOS (Local Oxidation of Silicon) method to form an active region and an isolation region of a device. To form.

The surface of the semiconductor substrate 10 is thermally oxidized to form an oxide film as the gate insulating film.

Next, an in-situ doped polycrystalline silicon is formed by chemical vapor deposition on the gate oxide layer to form a gate electrode, or an undoped polysilicon layer is undoped. polycrystalline silicon) is deposited by chemical vapor deposition and then doped by ion implantation. The polysilicon layer thus formed is patterned in a subsequent process to form a lower structure of the gate electrode. In this case, the deposited polysilicon layer is formed to a thickness obtained by subtracting the thickness of the silicide layer to be formed in consideration of the height of the entire gate electrode.

Then, the doped polysilicon layer and the oxide film are sequentially patterned by photolithography to form a gate electrode 12 and a gate insulating film 11 including the remaining polysilicon layer 12 and the oxide film 11.

Next, a lightly doped drain (LDD) layer for lightly doped drain (LDD) is formed in the active region of the substrate where the gate 12 is not formed by the appropriate conductivity type impurity ion implantation.

Referring to FIG. 1B, an oxide film 14 having a predetermined thickness is deposited on the entire surface of the substrate 10 including the gate electrode 12 by chemical vapor deposition. At this time, the oxide film 14 is used for forming sidewall spacers that insulate side surfaces of the gate electrode 12 and are used as part of an ion implantation mask for forming a highly doped impurity doped region.

Referring to FIG. 1C, an oxide film is etched back to form a sidewall spacer 140 formed of an oxide film remaining on the side surface of the gate electrode 12. At this time, the etch back is performed by anisotropic etching until both the active region of the substrate and the upper surface of the gate electrode 12 are exposed.

Therefore, the upper surface of the exposed gate electrode 12 is equal to the size of the gate width seen in the channel length direction.

Then, ion implantation using the gate electrode 12 and the sidewall spacer 140 as an ion implantation mask is performed to form a high concentration impurity ion buried layer in an active region of a substrate exposed with the same conductivity type impurity used to form a low concentration impurity ion buried layer. (15) is formed.

Referring to FIG. 1D, the low concentration impurity ion buried layer 13 and the high concentration impurity ion buried layer 15 are subjected to a process for sufficient diffusion of impurity ions by a thermal process or the like to form a low concentration impurity diffusion region 130 of the LDD structure. A high concentration impurity diffusion region 150 is formed to form source / drain 130 and 150. The impurity diffusion process for the source / drain 130 and 150 may be performed after the formation of silicide or salicide.

The silicide forming metal layer 16 is formed on the entire surface of the substrate 10 including the active region where the source / drain 130 and 150 are formed and the exposed gate electrode 12 surface. At this time, the metal layer is formed of a metal capable of forming a silicide in the form of a metal-silicon bond by reacting with silicon of the gate electrode 12, such metals include Co, Ti, W, etc., the deposition method is sputtering ( sputtering). At this time, the thickness of the metal layer 16 is combined with the thickness of the gate electrode 12 so that the overall height conforms to the design rule of the gate electrode to be formed later.

In addition, rapid thermal annealing is performed on the gate electrode 12 having the metal layer 16 and the high concentration impurity diffusion region 150 to react the metal with silicon to reduce the resistance of the first silicide layer 160 and the second. The silicide layers 161 are formed at the same time.

Referring to FIG. 1E, a silicide layer having a salicide structure is formed by wet etching a metal layer remaining at a portion where the first silicide layer 160 and the second silicide layer 161 is not formed. To prepare.

In addition, when the impurity diffusion process is not performed in FIG. 1D, a thermal process for completing the source / drain is performed to form the source / drain.

As described above, the silicide layer forming method according to the related art is difficult to form a silicide layer having a thick and uniform thickness of the silicide of the metal-silicon formed when the silicide is formed by heat treatment (RTA) and the reaction between the metal and silicon. There is this. This is because it is difficult to form a uniform silicide due to the high concentration of the dopant (dopant) because the highly doped polysilicon and the metal reacts.

In addition, as the line width of the gate is reduced to a size of less than one micron, the silicon exposed portion of the gate on which the silicide is formed decreases, thereby increasing the sheet resistance of the gate, thereby lowering the reliability of the device.

Accordingly, an object of the present invention is to form a first gate pattern having a double sidewall spacer made of an insulating material having a high etch selectivity to form a polyside gate including a silicide layer, and then partially replacing the inner insulating material of the double sidewall spacer. After removing to extend the exposed portion of the first gate pattern, an epitaxial layer is grown on the exposed first gate pattern surface to form a second gate pattern, and then the silicide is formed to ensure the uniformity of the silicide and resistance due to high integration of the device. To provide a method for forming a salicide layer of a semiconductor device to greatly reduce the number of.

According to an aspect of the present invention, there is provided a silicide layer forming method comprising: forming a gate formed of a semiconductor through a gate insulating layer on a predetermined portion of a semiconductor substrate; Forming an impurity diffusion region of the first sidewall, forming a first sidewall spacer made of a first insulating film on the side of the gate, and forming an upper surface of the first sidewall spacer with a second insulating film on the side of the first sidewall spacer. Forming a second sidewall spacer to expose, removing a portion of the exposed portion of the first sidewall spacer to form a space to increase the exposed area of the gate, and exposing the exposed gate surface and the exposed The first semiconductor layer and the second semiconductor layer made of the semiconductor on the surface of the impurity diffusion region And forming the first silicide layer and the second silicide layer by silicidating the first semiconductor layer and the second semiconductor layer with a metal, respectively. The forming of the first and second silicide layers may include forming a metal layer made of the metal on the substrate including the first semiconductor layer and the second semiconductor layer, and the metal layer and the second layer. Performing a thermal process on the first and second semiconductor layers to form a silicide by reacting the metal of the metal layer with the semiconductor; and removing the remaining metal layer not participating in the silicidation. Is done.

1A to 1E are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the related art.

2A through 2H are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the present invention.

As the line width of other gates decreases to submicrons due to high integration of semiconductor products, the sheet resistance at the gate contact portion increases. In order to reduce the sheet resistance, a gate electrode having a polyside structure for forming silicide on the upper surface of the gate is formed.

In the present invention, the sidewall spacers of the gate electrode are formed of a double layer structure with two kinds of insulating materials having a large etching selectivity, and then the insulating material formed on the inner side is removed to form a space between the gate electrode and the outer sidewall spacer to expose the gate electrode. To increase.

Then, a silicon epitaxial layer is formed on the exposed gate electrode surface to fill the space, thereby expanding the exposed portion of the gate electrode, and then depositing a silicide forming metal layer over the exposed portion, and then reacting the silicon with the metal. Forms silicides. Therefore, the contact area between the silicide and the gate electrode is increased to reduce the sheet resistance.

In addition, in the present invention, silicide is formed on the surface of the gate electrode and the impurity diffusion region as an epi layer not doped with impurities, and thus silicide having a uniform composition can be formed.

That is, the present invention, in order to reduce the resistance generated as the line width of the gate sub-micron is formed after forming the sidewall spacers after forming the gate to form a double sidewall and partially wet etching the inner sidewall to form an epi layer The general process forms silicides or salicides.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method of forming a silicide layer of a semiconductor device according to the present invention.

Referring to FIG. 2A, a field oxide film (not shown) is formed on a predetermined portion of a silicon substrate 20, which is a semiconductor substrate, by a device isolation method such as a local oxide of silicon (LOCOS) or shallow trench isolation (STI) method. Forming an active region and an element isolation region

The surface of the semiconductor substrate 20 is thermally oxidized to form an oxide film as the gate insulating film.

Next, an in-situ doped polycrystalline silicon is formed by chemical vapor deposition on the gate oxide layer to form a gate electrode, or an undoped polysilicon layer is undoped. polycrystalline silicon) is deposited by chemical vapor deposition and then doped by ion implantation. The polysilicon layer thus formed is patterned in a subsequent process to form a lower structure of the gate electrode. In this case, the deposited polysilicon layer is formed to a thickness obtained by subtracting the thickness of the silicide layer to be formed in consideration of the height of the entire gate electrode.

Then, the doped polysilicon layer and the oxide film are sequentially patterned by photolithography to form a gate electrode 22 and a gate insulating film 21 formed of the remaining polysilicon layer 22 and the oxide film 21.

Next, a lightly doped drain (LDD) buried layer 23 for LDD (lightly doped drain) is formed in the active region of the substrate where the gate 22 is not formed by the appropriate conductivity type impurity ion implantation.

Referring to FIG. 2B, an oxide film is formed by chemical vapor deposition on the entire surface of the substrate 20 including the gate electrode 22 with a first insulating film having a predetermined thickness. In this case, the oxide film is used to form a first sidewall spacer, which partially insulates the side surface of the gate electrode 22 and is used as part of an ion implantation mask for forming a highly doped impurity doped region.

The first sidewall spacer 24 made of the oxide film remaining on the side surface of the gate electrode 22 is formed by etching back to the first insulating film made of the oxide film. At this time, the etch back is performed by anisotropic etching such as dry etching until both the active region of the substrate and the upper surface of the gate electrode 22 are exposed.

Therefore, the upper surface of the exposed gate electrode 22 is equal to the size of the gate width seen in the channel length direction.

Then, ion implantation using the gate electrode 22 and the first sidewall spacer 24 as an ion implantation mask is performed to form a high concentration impurity in the active region of the substrate exposed with the same conductivity type impurity used to form a low concentration impurity ion buried layer. An ion buried layer 25 is formed.

Referring to FIG. 2C, a second insulating layer 26 is formed on the substrate 20 including the first sidewall spacer 24 and the exposed gate electrode 22 using an insulating material having a high etching selectivity and a first insulating layer. . In this case, when the first insulating film is formed of an oxide film, the second insulating film 26 forms a nitride film by chemical vapor deposition.

Referring to FIG. 2D, a second sidewall spacer 260 is formed of a second insulating film 260 remaining on the side surface of the first sidewall spacer 24 by etching back to the second insulating film by anisotropic etching such as dry etching. To form. At this time, the etchback for forming the second sidewall spacer 260 is formed so that the top surface of the gate electrode 22 and the active region surface of the substrate are simultaneously exposed. 2 allows active regions without sidewall spacers 24 and 260 to be exposed.

Referring to FIG. 2E, a portion of the exposed first sidewall spacer is removed to extend an exposed portion of the upper surface of the gate electrode 22 on which the silicide layer for the gate voltage applying contact portion is to be formed. In this case, the expansion of the exposed portion of the gate electrode surface is performed by performing a wet etching on the first sidewall spacer made of the oxide film to partially remove the gate electrode surface, and using the wet etching solution for B.O.E. Or HF.

In addition, a low concentration impurity diffusion region 230 and a high concentration impurity diffusion region 250 of the LDD structure are formed by performing a process for sufficient diffusion of impurity ions in a low concentration impurity ion buried layer and a high concentration impurity ion buried layer by a thermal process. Form source / drain 230, 250.

Referring to FIG. 2F, a first epitaxial layer 270 made of silicon on the exposed portion of the gate electrode 22 and the exposed surface of the high concentration impurity diffusion region 250 made of silicon. And the second epitaxial layer 271 are grown at the same time. In this case, the first and second epitaxial layers 270 and 271 are selectively formed only where nucleation sites in which a part of the exposed silicon acts as a growth nucleus are formed.

Accordingly, since the first epitaxial layer 270 formed on the upper surface of the gate electrode 22 becomes silicide afterwards, its formation area is widened, and the second epitaxial layer 271 formed on the upper surface of the impurity diffusion region 250 is formed. ) Is formed of an undoped silicon layer, so that a silicide having a uniform characteristic can be formed thereafter, thereby reducing the sheet resistance of the contact portion and the contact resistance of the contact portion as a whole.

Referring to FIG. 2G, a silicide-forming metal layer may be formed on an entire surface of a substrate including a second epitaxial layer formed on an active region having a high concentration impurity diffusion region 250 and a second epitaxial layer formed on a surface of the gate electrode 22. 28). In this case, the metal layer may react with the silicon of the first epitaxial layer on the gate electrode 22 and the second epitaxial layer on the high concentration impurity diffusion region 250 to form a silicide in which a metal-silicon bond is formed. Co, Ti, W, etc. are formed as the metal, and the deposition method uses sputtering. At this time, the thickness of the metal layer 28 is combined with the thickness of the gate electrode and the first epitaxial layer so that the overall height is suitable for the design height of the gate electrode to be formed later.

The first epitaxial layer and the second epitaxial layer on which the metal layer 28 is formed are subjected to rapid thermal annealing to react the metal of the metal layer with silicon of each epitaxial layer to reduce the resistance of the first silicide layer. 280 and the second silicide layer 281 are formed at the same time. At this time, the thickness of the second epitaxial layer participating in the reaction of forming the second silicide layer 281 is determined to be silicided.

Referring to FIG. 2H, a silicide layer having a salicide structure is formed by wet etching a metal layer remaining at a portion where the first silicide layer 280 and the second silicide layer 281 is not formed. To prepare.

The substrate is then subjected to a secondary thermal process to complete the present invention.

Accordingly, the present invention improves the morphology by uniformly forming an interface structure between the silicide layer and the silicon layer, and expands the silicide formation area on the gate, thereby increasing the contact area of the gate voltage application. The sheet resistance of the device is reduced, and the source / drain contact resistance is also reduced, thereby improving the reliability of the device.

Claims (6)

Forming a gate made of the semiconductor via a gate insulating film at a predetermined portion of the semiconductor substrate; Forming a pair of impurity diffusion regions corresponding to each other on the substrate at the lower side of the gate side; Forming a first sidewall spacer made of a first insulating film on the side of the gate; Forming a second sidewall spacer on a side of the first sidewall spacer to expose a top surface of the first sidewall spacer with a second insulating film; Removing a portion of the exposed portion of the first sidewall spacer to form a space for increasing the exposed area of the gate; Forming a first semiconductor layer and a second semiconductor layer made of the semiconductor on the exposed gate surface and the exposed impurity diffusion region, respectively; And silicating the first semiconductor layer and the second semiconductor layer with a metal to form a first silicide layer and a second silicide layer, respectively. The method of claim 1, wherein the semiconductor, the first and second semiconductor layers are formed of silicon, and the gate is formed of polysilicon. The method of claim 1, wherein the metal is formed of Co, Ti, or W. The method of forming a silicide layer of a semiconductor device according to claim 1, wherein the first semiconductor layer and the second semiconductor layer are formed by an epitaxial method. The method of claim 1, wherein the forming of the first and second silicide layers, Forming a metal layer made of the metal on the substrate including the first semiconductor layer and the second semiconductor layer; Performing a thermal process on the metal layer and the first and second semiconductor layers to form a silicide by reacting the metal of the metal layer with the semiconductor; And removing the remaining metal layer not participating in the silicidation. The method of claim 1, wherein the space is formed by a method of partially removing the first sidewall spacer by wet etching.