JP2003168652A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To evenly achieve the reduction of the resistance of a gate electrode and of source/drain regions and reduction of junction leakage currents in source/ drain regions in a MOS transistor having silicides on the surfaces of the gate electrode and of the source/drain regions. <P>SOLUTION: This method of manufacturing a semiconductor device comprises a step of forming a gate electrode 13 made of silicon on a silicon substrate 11, a step of forming impurity-diffused regions 15 in the substrate 11, a step of forming a metal layer containing cobalt and nickel on the surface of the gate electrode 13 and of at least one of the impurity-diffused regions 15, a step of forming a silicide layer 17 containing silicon, cobalt and nickel on each by heat treatment to make the metal layer react with the silicon substrate 11 or with the silicon contained in the gate electrode 13, and a step of forming a wiring layer for electrically contacting the silicide layer 17 on each. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a MOS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices such as MOS transistors, a delay in response speed has become apparent due to an increase in sheet resistance of impurity diffusion regions forming source / drain regions. Polysilicon is usually used for the gate electrode, but since silicon has a high resistance, wiring delay is also a problem for this gate electrode. As a means for solving such a problem, CoS is formed on the gate electrode and the source / drain regions.
It has been proposed to form an i ₂ layer to reduce the resistance. A semiconductor device provided with this CoSi ₂ layer is disclosed, for example, in JP-A-7-78788 and
`` A Robust 0.15um CMOS Technology with CoSi ₂ salic
ide and shallow trench isolation '' H. Kawaguchi et.
al 1997 Symposium on VLSI technology Digest of tec
hnical paper 9B-4 (1997) pp125-126.

A method of manufacturing the above semiconductor device will be described. First, a gate electrode made of polysilicon is formed on a silicon substrate via a gate insulating film, and then ion implantation is performed using the gate electrode as a mask to form a low-concentration impurity diffusion region. After forming a side wall made of an insulating film on the side wall of the gate electrode, ion implantation is carried out again to form an impurity diffusion region to be a source region and a drain region to form a MOS transistor. continue,
A cobalt layer is formed on the entire surface of the MOS transistor. Then, the first-stage heat treatment is performed to silicify the cobalt layer. At this time, since the silicide reaction proceeds only in the region where the cobalt layer and silicon (silicon substrate or gate electrode) are in direct contact with each other, the cobalt layer is formed on the side wall made of the insulating film and the element isolation insulating film. It remains unreacted. After removing the unreacted cobalt layer, the second stage heat treatment is performed, and the silicide reaction is further advanced to form a CoSi ₂ layer.

[0004]

With the miniaturization of semiconductor devices, in addition to lowering the resistance of the gate electrode and the source / drain regions, it is required to reduce the junction leak current in the source / drain regions. In the conventional semiconductor device as described above, it is possible to reduce the junction leak current by increasing the heat treatment temperature in the CoSi ₂ layer forming step (in particular, the heat treatment temperature of the second step).

However, when the heat treatment temperature is too high, the internal stress of the CoSi ₂ layer increases, so that CoS
Defects easily occur in the i ₂ layer, and as a result, the thin wire resistance of the gate electrode increases. Such an increase in the thin wire resistance of the gate electrode becomes a particular problem as the gate electrode becomes finer.

As described above, in the conventional semiconductor device, it is difficult to achieve both low resistance of the gate electrode and reduction of junction leak current in the source / drain regions.

It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can reduce both the thin wire resistance of the electrode and the junction leak current in the impurity diffusion region.

[0008]

In order to achieve the above object, a semiconductor device of the present invention comprises a silicon substrate, an electrode containing silicon formed on the substrate, and an impurity diffusion region formed in the substrate. And a silicide layer containing silicon, cobalt, and nickel is formed on the surface of at least one of the electrode and the impurity diffusion region.

With such a structure, it is possible to achieve both reduction of the thin wire resistance of the electrode and reduction of the junction leak current in the impurity diffusion region. The semiconductor device may be, for example, a MOS transistor. In this case, the electrode is a gate electrode and the impurity diffusion region is a source / drain region.

In the above semiconductor device, the composition of the silicide layer is Co _1-x Ni _x Si ₂ (where 0.05 ≦
x ≦ 0.5. ) Is preferable. According to this preferable example, the thin wire resistance of the electrode can be reduced without increasing the contact resistance.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an electrode containing silicon on a silicon substrate, a step of forming an impurity diffusion region in the substrate, the electrode and A step of forming a metal layer containing cobalt and nickel on at least one surface of the impurity diffusion region, and a reaction of the silicon contained in the substrate or the electrode with the metal layer by heat treatment to obtain silicon, cobalt and nickel. And a step of forming a silicide layer containing.

According to such a manufacturing method, the junction leak current in the impurity diffusion region can be sufficiently reduced even when the heating temperature in the silicide layer forming step is relatively low. Therefore, according to the manufacturing method of the present invention, even if the heating temperature in the silicide layer forming step is lowered, the thin wire resistance of the electrode is reduced, and
The junction leak current can be sufficiently reduced.

The reason why the thin wire resistance of the electrode and the reduction of the junction leak current can both be achieved by the manufacturing method of the present invention is considered as follows.

One of the causes of the junction leakage current is that the metal (cobalt) forming the metal layer diffuses into the deep portion of the silicon substrate during the heat treatment for forming the silicide layer.
As a result, it is considered that this metal remains in the deep portion of the silicon substrate. Therefore, if the heat treatment temperature for forming the silicide layer is increased, the silicide layer can be formed in a short time, so that the time for the metal to diffuse into the silicon substrate can be shortened and the junction leakage current can be reduced. It is thought to be possible.

However, in the conventional semiconductor device, since a simple substance of cobalt is used as the metal layer, silicidation requires a relatively high temperature. Therefore, in order to shorten the time required for forming the silicide layer and sufficiently suppress the diffusion of the metal into the silicon substrate, a considerably high temperature (for example, 875 ° C. or higher) is required. As described above, it is very difficult to reduce the thin wire resistance of the silicon electrode in such a high temperature range.

On the other hand, nickel-added cobalt can be silicidized by a heat treatment at a lower temperature than cobalt alone. Therefore, by using nickel-added cobalt, even when the heat treatment temperature is relatively low, the heat treatment time for forming the silicide layer, that is, the time for the metal forming the metal layer to diffuse into the silicon substrate is shortened. The diffusion of the metal into the deep part of the substrate can be sufficiently suppressed. As a result, it is considered that it is possible to achieve both reduction of the thin wire resistance of the silicon electrode and reduction of the junction leak current.

In the manufacturing method, the heat treatment temperature is 750 ° C. in the step of forming the silicide layer.
The following is also possible. According to the manufacturing method of the present invention, the junction leak current in the impurity diffusion region can be sufficiently reduced and the thin wire resistance of the silicon electrode can be sufficiently reduced even by such low temperature heat treatment.

In the above manufacturing method, the metal layer may be formed of an alloy containing cobalt and nickel. Such a metal layer can be formed by a step of performing sputtering with an alloy containing cobalt and nickel as a target.

In this case, the atomic ratio of cobalt and nickel (Co: Ni) in the metal layer is 95: 5-5.
It is preferably in the range of 0:50. According to this preferable example, the thin wire resistance of the silicon electrode can be reduced and the junction leak current can be further reduced without increasing the contact resistance.

Further, in the above-mentioned manufacturing method, it is preferable that the metal layer has a multi-layer structure including a cobalt layer and a nickel layer. This is because the ratio of cobalt and nickel can be controlled with high accuracy. Such a metal layer can be formed by a method including a step of performing sputtering with cobalt as a target and a step of performing sputtering with nickel as a target.

In this case, in the metal layer, the ratio (T _Co : T _Ni ) of the cobalt layer thickness (T _Co ) and the nickel layer thickness (T _Ni ) is 95: 5 to 50:50. It is preferably in the range. According to this preferable example, the thin wire resistance of the silicon electrode can be reduced and the junction leak current can be further reduced without increasing the contact resistance.

In the manufacturing method, it is preferable that the heat treatment is performed in two or more steps in the step of forming the silicide layer. As such a heat treatment method, for example, the metal layer is silicidized by a first-stage heat treatment to form a monosilicide layer, and then the monosilicide layer is further silicified by a second-stage heat treatment to form a disilicide. A two-step heat treatment of forming a layer may be mentioned. Here, the monosilicide layer is a layer mainly containing monosilicide (MSi; M is a metal containing Co and Ni), and the disilicide layer is mainly disilicide (MSi ₂ ; M
Is the same as above. ) Is a layer containing.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An example of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an example of the semiconductor device of the present invention. In this semiconductor device, the gate insulating film 12 is formed on the surface of the semiconductor substrate 11, and the gate electrode 13 is further formed thereon. A sidewall 14 is formed on the sidewall of the gate electrode 13.
A silicon substrate can be used as the semiconductor substrate 11, and polysilicon can be used as the gate electrode 13. The line width of the gate electrode 13 is, for example, 0.
1 to 0.05 nm, and the thickness thereof is, for example, 300 to
It is 100 nm. Further, as the gate insulating film 12,
For example, a silicon oxide film can be used, and as the sidewall 14, for example, a silicon oxide film, a silicon nitride film, or the like can be used.

Two impurity diffusion regions 15 are formed in the surface layer of the semiconductor substrate. These impurity diffusion regions 15 are regions to be a source region and a drain region, respectively, and are formed so as to be separated from each other with the gate electrode 13 interposed therebetween. Although not particularly limited, the impurity concentration of the impurity diffusion region 15 is, for example, about 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ^{−2 in} dose amount, and the diffusion depth thereof is, for example, 0.05 to 0. It is 15 μm. Further, an impurity diffusion region 18 having a lower concentration than that of the impurity diffusion region 15 is formed in a region that is in contact with the end portion of the impurity diffusion region 15 on the gate electrode 13 side and exists below the sidewall 14. There is.

Further, in this semiconductor device, an alloy layer (hereinafter referred to as “silicide layer”) 17 containing cobalt, nickel and silicon is formed on at least one surface of the gate electrode 13 and the impurity diffusion region 15. There is. The silicide layer 17 has a composition formula: Co _1-x Ni _x S
It is preferably a disilicide represented by i ₂ . Here, x is in the range of 0.05 or more and 0.5 or less, preferably 0.1 or more and 0.5 or less.

The layer thickness of the silicide layer 17 is not particularly limited. When it is formed on the impurity diffusion region 15, it is preferably about 1/3 of the diffusion depth of the impurity diffusion region 15. Further, when it is formed on the gate electrode 13, it is preferably about 1/3 of the thickness of the gate electrode 13. Specifically, the layer thickness of the silicide layer 17 can be set to, for example, 12 to 15 nm.

A wiring layer (not shown) is electrically connected to the impurity diffusion region 15. This wiring layer has a silicide layer 17 on the surface of the impurity diffusion region 15.
Is formed, it is electrically connected to the impurity diffusion region 15 through the silicide layer 17.

The above semiconductor device can be manufactured, for example, by the following method. 2 (A) to (D)
FIG. 6A is a process diagram for describing the example of the method of manufacturing the semiconductor device.

First, the gate insulating film 1 is formed on the semiconductor substrate 11.
2, a MOS transistor including the gate electrode 13, the sidewall 14 and the impurity diffusion region 15 is formed (FIG. 2A). The forming method is not particularly limited, but for example, the following method can be used. First, a silicon oxide film is formed on the silicon substrate 11 by a thermal oxidation method. After forming a polysilicon film on the silicon oxide film by a chemical vapor deposition (CVD) method, the silicon oxide film and the polysilicon film are patterned by photolithography and etching to form a gate insulating film 12 and a gate electrode 13.
To form. Then, using the gate electrode 13 as a mask,
Impurity ions are implanted into the silicon substrate 11 to form a low concentration impurity diffusion region 18. Then, after forming a silicon oxide film by the CVD method, anisotropic etching such as dry etching is performed. As a result, the sidewall 14 is formed on the sidewall of the gate electrode 13. Then, using the gate electrode 13 and the sidewall 14 as a mask, impurity ions are implanted again to form an impurity diffusion region 15 to be a source region and a drain region.

Subsequently, a metal layer containing cobalt and nickel is formed. Prior to this step, it is preferable to carry out a step of cleaning the surface on which the metal layer is formed.
This cleaning step can be performed by etching the substrate surface by, for example, sputter etching. In this case, the substrate surface is etched by about 5 nm, for example.

Next, the metal layer 16 containing cobalt and nickel is formed (FIG. 2B). As a method of forming the metal layer 16, for example, the following two methods can be adopted.

The first method is when the metal layer 16 is an alloy layer containing cobalt and nickel. The composition of the alloy layer can be appropriately set according to the desired composition of the silicide layer which is the final form. For example, when the composition of the alloy layer is expressed by Co _1-x Ni _x , x can be in the range of 0.05 or more and 0.5 or less, preferably 0.1 or more and 0.5 or less. The layer thickness of the alloy layer is not particularly limited, but is, for example, 3 to 15 nm, preferably 5 to 8 nm.

In this method, the metal layer 16 is formed by
For example, it can be carried out by a sputtering method using an alloy target containing cobalt and nickel. In this case, the composition of the alloy target can be appropriately set according to the desired composition of the metal layer.

The second method is a case where the metal layer 16 is a laminated film of a cobalt layer and a nickel layer. The layer thickness of each layer can be appropriately set according to the desired composition in the silicide layer which is the final form. For example, the ratio (T _Co ) of the film thickness of the cobalt layer (T _Co ) and the film thickness of the nickel layer (T _Ni )
_Co : T _Ni ) 95: 5 to 50:50, preferably 90:
It may be in the range of 10 to 50:50. Further, the film thickness (total film thickness) of the metal layer is not particularly limited, and can be set in the same range as the above-mentioned first method.

The cobalt layer and the nickel layer may be laminated in either order. That is, the nickel layer may be formed on the cobalt layer or the cobalt layer may be formed on the nickel layer. Also, the number of layers of the laminated film is not particularly limited, and a laminated film of three or more layers including at least one of a cobalt layer and a nickel layer can be used. In this case, it is preferable that the ratio of the total film thickness of the cobalt layer and the total film thickness of the nickel layer be in the range described above.

In the second method, the metal layer 16 is formed by, for example, a step of forming a cobalt layer by a sputtering method using a cobalt target and a step of forming a nickel layer by a sputtering method using a nickel target. This can be done by carrying out each of the above.

In each of the first and second methods, for example, direct current (DC) sputtering, radio frequency (RF) sputtering, magnetron sputtering, etc. can be adopted as the sputtering method. Further, in the case of the second method, it is possible to adopt the CVD method as the method of forming the metal layer.

Subsequently, heat treatment is carried out. Prior to this heat treatment, it is preferable to carry out a step of forming a protective film on the surface of the metal layer 16. This protective film is formed to suppress the oxidation of the metal layer 16 in the heat treatment process. As the protective film, for example, titanium nitride, tungsten nitride, or the like can be used, and the film thickness thereof can be set to, for example, 5 to 15 nm. The method for forming the protective film is not particularly limited, but for example, a sputtering method can be adopted.

Next, heat treatment is performed to react the metal layer 16 with the silicon constituting the semiconductor substrate 11 and the gate electrode 13 to form a silicide layer 17 (FIG. 2).
(C)). At this time, the silicide reaction proceeds in the region where the metal layer 16 is in direct contact with silicon, that is, on the impurity diffusion region 15 and the gate electrode 13, and the silicide layer 17 is formed. However, in other regions, that is, on the sidewall 14 and the element isolation region (not shown), the metal layer 16 remains unreacted.

The heat treatment temperature is preferably as low as possible in order to sufficiently suppress the resistance increase of the gate electrode 13. As described above, in the manufacturing method of the present invention, the metal layer 16 serving as the precursor of the silicide layer contains cobalt and nickel. Therefore, it is possible to lower the heat treatment temperature for forming the silicide layer as compared with the case where only cobalt is used.
It is possible to lower the temperature to below ℃. The lower limit of the heat treatment temperature is not particularly limited as long as it is a temperature at which the silicide reaction can proceed, but is, for example, 65.
It is 0 ° C or higher. The heat treatment time is, for example, 30 seconds to
2 minutes. The processing atmosphere is preferably an inert atmosphere such as a nitrogen atmosphere or a reducing atmosphere in order to suppress the oxidation of the metal layer.

After the heat treatment, the metal layer 16 which remains unreacted on the sidewalls 14 is removed (FIG. 2D).
This unreacted metal layer can be removed by, for example, wet etching. In this case, as the etching solution, for example, hydrochloric acid or sulfuric acid to which hydrogen peroxide is added can be used. When a protective film is formed, it is preferable to remove the protective film together with the unreacted metal layer.

By adjusting the heat treatment conditions (at least one of temperature and time), it is possible to control the layer thickness of the silicide layer 17 to be formed. For example, a method of performing heat treatment under the condition that an unreacted (non-silicided) region remains on the surface of the metal layer 16 and then removing this unreacted region together with the unreacted region remaining on the sidewall 14. Is adopted, regardless of the layer thickness of the metal layer 16, the silicide layer 1 having a desired layer thickness is obtained.
It is possible to form 7.

As described above, the silicide layer forming step is
It can be carried out by a two-step heat treatment, but
It is preferable to include heat treatment in more than one step. 2 like this
The method including heat treatment in more than one step can be carried out as follows, for example.

First, heat treatment at a relatively low temperature is performed to silicify the metal layer to form a first silicide layer (hereinafter, this step is referred to as "first step heat treatment"). The first silicide layer mainly contains monosilicide containing cobalt and nickel. The treatment temperature in the first-stage heat treatment is not particularly limited as long as the silicide reaction can occur. However, if the temperature is too high, the silicidation reaction may proceed in the lateral direction, and even the metal layer on the sidewall may be silicidized. Therefore, the treatment temperature is preferably in the range of 360 to 450 ° C. The treatment time is not particularly limited, but is, for example, 10 seconds to 2 minutes. The processing atmosphere is the same as that described above.

After the first-stage heat treatment, the unreacted and remaining metal layer is removed. As described above, the metal layer remaining unreacted includes the metal layer on the sidewall. This removal of the metal layer can be carried out, for example, by wet etching using an etching solution prepared by adding hydrogen peroxide to hydrochloric acid or sulfuric acid.

Subsequently, heat treatment at a relatively high temperature is performed to react the first silicide layer with the underlying silicon to form a second silicide layer (hereinafter, this step is referred to as "second step"). Heat treatment ".). The second silicide layer mainly contains disilicide containing cobalt and nickel.

The heat treatment temperature in the second step is not particularly limited, but it is preferably as low as possible in order to sufficiently suppress the resistance increase of the gate electrode. As described above, in the manufacturing method of the present invention, since the metal layer serving as the precursor of the silicide layer contains cobalt and nickel, it is possible to lower the heat treatment temperature in the second step. It is possible to lower the temperature to 750 ° C or lower. The lower limit of the second stage heat treatment temperature may be a temperature at which the disilicide is sufficiently formed, and is, for example, 650 ° C. or higher. The heat treatment time of the second stage is, for example, in the range of 30 seconds to 2 minutes, and the treatment atmosphere is the same as that of the heat treatment of the first stage.

After forming the silicide layer 17 as described above, a wiring layer electrically connected to the impurity diffusion region 15 and the like are appropriately formed to obtain a semiconductor device. This step can be performed, for example, as follows. First, after forming an insulating layer on the entire surface of the substrate, an opening is formed in the insulating layer above the impurity diffusion region 15. As the insulating layer, for example, a silicon oxide film or the like can be used, and as a method of forming the insulating layer, for example, a CVD method or the like can be adopted. The opening can be formed by etching. Then, a barrier layer is formed on the insulating layer (including on the inner wall surface of the opening).
As the barrier layer, for example, a multilayer film in which a Ti layer and a TiN layer are sequentially stacked from the substrate side can be used, and as a method of forming the barrier layer, for example, a sputtering method can be adopted.

Further, after forming a tungsten layer on the barrier layer so as to fill the inside of the opening, the tungsten layer and the barrier layer existing in the region other than the opening are selectively removed. As a result, tungsten is embedded in the opening and a tungsten plug is formed. The tungsten layer can be formed by, for example, the CVD method. Then, a wiring layer is formed on the tungsten plug.

In the above description, the silicide layer is used as the gate electrode and the impurity diffusion region (source / drain region).
Self-aligned so-called salicide (SA
The LICIDE (self-aligned silicide) transistor structure is taken as an example. However, the present invention is not limited to this, and as described above, the silicide layer may be formed on at least one of the gate electrode and the impurity diffusion region.

Similarly, the manufacturing method is not limited to the method of forming the silicide layer in a self-aligned manner. For example, a metal containing cobalt and nickel is formed on the entire surface of the substrate and patterned by photolithography and etching to form a metal layer only at a portion where a silicide layer is to be formed, and then heat treatment is performed. The metal layer may be silicidized.

[0053]

EXAMPLES Example 1 First, the following method was used.
A MOS transistor having a sidewall was formed. 2.5n film thickness on n-type silicon substrate by thermal oxidation method
After forming a silicon oxide film having a thickness of m, a polysilicon film was formed on the silicon oxide film by the CVD method. Subsequently, a photoresist is applied on the polysilicon film,
This was exposed / developed and patterned. The polysilicon film was patterned by plasma etching using this photoresist as a mask to form a gate electrode. The formed gate electrode had a line width of 0.13 μm and a thickness of 0.2 μm. Subsequently, arsenic was ion-implanted into the silicon substrate using the gate electrode as a mask. Subsequently, a silicon oxide film having a film thickness of 50 nm was formed by a CVD method using TEOS, and then plasma etching was performed to etch back the silicon oxide film on the entire surface. At this time, the silicon oxide film remained on the side wall of the gate electrode and a side wall was formed. Next, using the gate electrode and the sidewall as a mask, arsenic was ion-implanted into the silicon substrate again. By this ion implantation, source / drain regions having a concentration of 1 × 10 ¹⁸ cm ⁻³ were formed.

C is formed on the entire surface of the formed MOS transistor.
A metal layer having a thickness of about 10 nm was deposited by DC sputtering using an o-Ni alloy target. The composition of the alloy target was Co: Ni = 9: 1 (atomic ratio). The sputtering conditions are as follows. The following gas flow rate is the amount of gas introduced per unit time converted into the volume in the standard state (0 ° C., 1 atm).

Gas used: Ar gas flow rate: 10 ml / minute pressure: 0.1 Pa DC power: 1 kW After that, a first stage heat treatment was performed in a nitrogen atmosphere at 450 ° C. for 60 seconds. Subsequently, the unreacted metal layer existing on the sidewall was removed by wet etching using an etching solution obtained by adding hydrogen peroxide to hydrochloric acid. Next, a second stage heat treatment was performed in a nitrogen atmosphere at 800 ° C. for 60 seconds. As a result, a silicide layer containing cobalt and nickel was formed on the surfaces of the gate electrode and the source / drain regions. The layer thickness of the silicide layer was 15 nm.

In the obtained semiconductor device, the thin wire resistance of the gate electrode and the junction leak current of the source / drain regions were measured. As a result, the thin wire resistance of the gate electrode is about 5.8 Ω / □ and the junction leakage current is about 1 × 10 ^-10.
It was A / cm ² . The thin wire resistance of the gate electrode was measured by the four-point probe method and expressed as a sheet resistance value. As the junction leak current, a current flowing when a reverse bias of 4 V was applied to the contact side (silicide layer side) with respect to the junction region having an area of 3 × 10 ⁻⁶ μm ² was measured.

A plurality of semiconductor devices were manufactured in the same manner as described above except that the processing temperature in the second stage heat treatment was changed, and the thin wire resistance of the gate electrode and the source.
The junction leak current in the drain region was measured. From the measured values, the relationship between the processing temperature and the thin wire resistance and the junction leakage current was obtained. The result is shown by a solid line in FIG.

As shown by the solid line in FIG. 3, it was confirmed that according to this embodiment, a sufficiently low junction leak current can be achieved even when the heat treatment temperature is relatively low. Therefore, a wide range of heat treatment temperature that can achieve both a sufficiently low junction leakage current and suppression of increase in sheet resistance value,
It was easy to achieve both a sufficiently low junction leak current and suppression of an increase in sheet resistance value.

(Example 2) Similar to Example 1, a MOS transistor having a sidewall was formed. A nickel layer having a thickness of about 1 nm was deposited on the entire surface of the formed MOS transistor by DC sputtering using a Ni target. Note that this sputtering was performed under the same conditions as in Example 1 except that the target was different. Further, a cobalt layer having a thickness of about 9 nm was deposited by DC sputtering using a Co target. In addition,
This sputtering has different targets and D
It carried out on the conditions similar to Example 1 except having set C power to 0.3 kW. As a result, a metal layer having a two-layer structure including the nickel layer and the cobalt layer was formed.

Then, heat treatment is carried out in the same manner as in Embodiment 1, and the gate electrode and the source / drain region surfaces are
A silicide layer containing cobalt and nickel was formed. The layer thickness of the silicide layer was 15 nm.

In the obtained semiconductor device, the thin wire resistance of the gate electrode and the junction leak current were measured. As a result, the thin wire resistance was about 5.8 Ω / □, and the junction leak current was about 1.
It was × 10 ^-10 A / cm ² . The measuring method is as described above.

Further, when the relationship between the processing temperature and the thin wire resistance of the gate electrode and the junction leakage current was obtained in the same manner as in Example 1, the same results as in Example 1 can be obtained also in this example. It could be confirmed.

(Comparative Example) A MOS transistor having a sidewall was formed in the same manner as in Example 1. A cobalt layer having a thickness of about 10 nm was deposited on the entire surface of the formed MOS transistor by DC sputtering using a Co target. Note that this sputtering was performed under the same conditions as in Example 1 except that the target was different.

Thereafter, as in Example 1, the first stage heat treatment and wet etching were performed. Next, a second stage heat treatment was performed in a nitrogen atmosphere at 875 ° C. for 60 seconds. This allows the gate electrode and the source
A cobalt silicide layer was formed on the surface of the drain region. The layer thickness of the silicide layer was 15 nm.

In the obtained semiconductor device, the thin wire resistance and the junction leak current of the gate electrode were measured, and the thin wire resistance was about 6 to 20 Ω / □, and the junction leak current was about 1 × 10 ⁻⁸ to about 1 ×. It was 10 ⁻⁹ A / cm ² . In addition,
The measuring method is as described above.

Further, when the relationship between the processing temperature and the thin wire resistance of the gate electrode and the junction leak current was obtained in the same manner as in the first embodiment, the same results as in the first embodiment can be obtained for the thin wire resistance. It could be confirmed. The measurement result of the junction leakage current was as shown by the broken line in FIG.

As shown by the broken line in FIG. 3, in this comparative example, a heat treatment temperature higher than that in the example was required in order to realize a junction leak current equivalent to that in the example. Therefore, it has been extremely difficult to achieve both a sufficiently low junction leakage current and suppression of an increase in the thin wire resistance of the gate electrode.

[0068]

As described above, according to the semiconductor device of the present invention, since the silicide layer containing silicon, cobalt and nickel is provided on the surface of at least one of the electrode and the impurity diffusion region, the resistance of the electrode is low. And reduction of junction leak current in the diffusion region can be achieved at the same time.

According to the manufacturing method of the present invention, a metal layer containing cobalt and nickel is formed on at least one surface of the electrode and the impurity diffusion region, and the metal layer is silicified by heat treatment to form a silicide layer. Therefore, the junction leakage current can be sufficiently reduced even when the heating temperature in the silicide layer forming step is relatively low. Therefore, it becomes easy to sufficiently reduce the junction leakage current while suppressing the increase in the resistance of the electrode.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device of the present invention.

FIG. 2 is a process cross-sectional view for explaining an example of the manufacturing method of the present invention.

FIG. 3 is a diagram showing the heat treatment temperature dependence of the thin wire resistance of the gate electrode and the junction leakage current in the semiconductor devices manufactured in Examples and Comparative Examples.

[Explanation of symbols]

11 Silicon substrate 12 Gate insulating film 13 Gate electrode 14 Sidewall 15 Impurity diffusion region 16 metal layers 17 Silicide layer 18 Low concentration impurity diffusion region

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M104 AA01 BB01 BB14 BB19 BB38                       BB40 CC01 CC05 DD02 DD04                       DD16 DD22 DD26 DD37 DD43                       DD64 DD65 DD78 DD84 FF14                       FF22 GG09 GG10 GG14 HH12                       HH14 HH16 HH20                 5F033 HH04 HH25 JJ18 JJ19 JJ33                       KK01 KK25 LL04 LL10 NN06                       NN07 PP06 PP15 QQ08 QQ09                       QQ12 QQ19 QQ31 QQ58 QQ59                       QQ65 QQ70 QQ73 QQ84 QQ92                       RR04 SS04 SS11 TT08 WW00                       XX00 XX01 XX03 XX10 XX20                 5F140 AA01 AA10 AA24 AA39 BA01                       BE07 BF04 BF11 BF19 BG08                       BG12 BG14 BG28 BG30 BG32                       BG34 BG35 BG38 BG44 BG45                       BG52 BG53 BH15 BH49 BJ09                       BJ11 BJ17 BJ20 BJ27 BK02                       BK09 BK13 BK24 BK26 BK29                       BK30 BK34 BK35 BK38 BK39                       CC03 CC12 CF04

Claims (11)

[Claims] 1. A step of forming an electrode containing silicon on a silicon substrate, a step of forming an impurity diffusion region in the substrate, and cobalt and nickel on at least one surface of the electrode and the impurity diffusion region. Manufacturing a semiconductor device including a step of forming a metal layer containing silicon and a step of reacting silicon contained in the substrate or the electrode with the metal layer by heat treatment to form a silicide layer containing silicon, cobalt and nickel. Method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the silicide layer, the heat treatment temperature is 750 ° C. or lower. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the metal layer is formed of an alloy containing cobalt and nickel. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the atomic ratio of cobalt and nickel (Co: Ni) in the metal layer is in the range of 95: 5 to 50:50. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming the metal layer is a step of performing sputtering with an alloy containing cobalt and nickel as a target. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer has a multilayer structure including a cobalt layer and a nickel layer. 7. The ratio (T _Co : T) of the thickness (T _Co ) of the cobalt layer and the thickness (T _Ni ) of the nickel layer in the metal layer.
_The method for manufacturing a semiconductor device according to claim 6, wherein _Ni ) is in the range of 95: 5 to 50:50. 8. The step of forming the metal layer, the step of carrying out sputtering targeting cobalt,
The method of manufacturing a semiconductor device according to claim 6, further comprising: performing a sputtering targeting nickel. 9. The heat treatment is performed in two or more steps in the step of forming the silicide layer.
The method for manufacturing a semiconductor device according to any one of 1. 10. A semiconductor device comprising a silicon substrate, an electrode containing silicon formed on the substrate, and an impurity diffusion region formed in the substrate, wherein the electrode and the impurity diffusion region are formed. On at least one surface,
A semiconductor device, wherein a silicide layer containing silicon, cobalt and nickel is formed. 11. The composition of the silicide layer is Co _1-x
The semiconductor device according to claim 10, which is represented by Ni _x Si ₂ (where 0.05 ≦ x ≦ 0.5).