JP2003150132A - Display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type display in which the power consumption can be effectively reduced. SOLUTION: This is an active matrix type display provided with a display pixel group 10 arranged in a matrix form, a 1st driving circuit 30 for outputting scanning signals to the display pixel group via scanning signal lines 21, and a 2nd driving circuit 40 for outputting video signals to the display pixel group via video signal lines 22, and at least one of the 1st and 2nd driving circuits has a plurality of driving steps operating based on a clock signal to be inputted, and is provided with a selection means 33 for selecting at least two or more driving steps, and a clock halting means for halting the clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device for mobile equipment such as a mobile phone.

[0002]

2. Description of the Related Art A flat-panel display device represented by a liquid crystal display device is mounted on many mobile devices such as a mobile phone by taking advantage of features such as thinness, light weight and low power consumption. With the rapid development of mobile phones and the like, demands for higher image quality and lower power consumption are increasing for such display devices. At present, it is attempting to cope with the high image quality by shifting from a simple matrix type liquid crystal display device to an active matrix type liquid crystal display device. However, the active matrix type liquid crystal display device is better than the simple matrix type liquid crystal display device. It consumes a lot of power, and therefore the usage time is reduced, which is a problem.

Display screens of mobile phones include a call screen for making a call, an operation screen for setting functions, a standby screen for waiting for incoming radio waves, and an information service screen. Of these, on the standby screen, only the icon (pictogram) indicating the reception intensity of the incoming radio wave, the clock, etc. may be displayed.
Therefore, in the simple matrix type liquid crystal display device, the number of scans is reduced by partially displaying only the picto icon on the standby screen to lower the drive voltage to save power (for example, Japanese Patent Laid-Open No. 11- 251277
issue).

However, in the active matrix type liquid crystal display device, if the scanning signal line is simply turned off, an abnormal display may occur due to the potential generated instantaneously at the time of turning off / on, or the scanning signal line may be turned off. However, since the video signal line is always driven, it may be displayed abnormally. Therefore, it is necessary to perform the operations of scanning, writing, and holding for all display pixels, and it is not possible to display only the pictogram.

Further, Japanese Patent Laid-Open No. 7-114862 proposes to stop the clock in the blanking period in an active matrix type display device for a moving body. However, since the blanking period is about 1/40 of the display period, it is difficult to achieve a sufficiently low power consumption.

[0006]

As described above, in a display device for a mobile device such as a mobile phone, it is desired to use an active matrix type display device from the viewpoint of high image quality and the like. In an active matrix type display device, even if only a part of the display screen needs to be displayed, there is a lot of waste such as writing a display signal to the entire display screen, thus sufficiently reducing power consumption. Was difficult.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide an active matrix type display device capable of effectively reducing power consumption.

[0008]

A display device according to the present invention comprises a display pixel group arranged in a matrix and a first drive circuit for outputting a scan signal to the display pixel group via a scan signal line. A second drive circuit that outputs a video signal to the display pixel group via a video signal line, wherein at least one of the first and second drive circuits is a display device. A plurality of drive stages that operate based on an input clock signal, and a selection means that selects at least two drive stages, and a clock stop means that stops the clock signal. .

Further, the display device according to the present invention comprises a display pixel group arranged in a matrix, and a first drive circuit for outputting a scanning signal to the display pixel group via a scanning signal line.
A second drive circuit that outputs a video signal to the display pixel group via a video signal line, the display device being an active matrix type, wherein at least the first drive circuit and the second drive circuit are provided. One is characterized in that a plurality of operation modes can be set and the operation mode of each drive stage is set by a shift register.

The display device according to the present invention further comprises a display pixel group arranged in a matrix, and a first drive circuit for outputting a scanning signal to the display pixel group via a scanning signal line.
A second drive circuit that outputs a video signal to the display pixel group via a video signal line, a video signal holding unit that holds the video signals for a plurality of frames, and a video signal held by the video signal holding unit An active matrix type display device including a difference detection unit for detecting a difference between frames, wherein at least one of the first drive circuit and the second drive circuit can set a plurality of operation modes. And the difference information detected by the difference detecting means and the operation mode are associated with each other to operate.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a structural example of an active matrix type liquid crystal display device for a moving body according to a first embodiment of the present invention.

The display device is roughly divided into a display pixel group 10 including a plurality of display pixels 11, a scanning signal drive circuit 30 for supplying a scanning signal to the display pixel group 10, and a video signal to the display pixel group 10. A video signal drive circuit 40 to be supplied,
A control circuit 50 for supplying a predetermined signal to these drive circuits.

Each display pixel 11 has a thin film transistor (T) as in a general active matrix type liquid crystal display device.
The switching element 12 such as FT), the pixel electrode 13, the auxiliary capacitance 14, and the like. Each display pixel 11 has a scanning signal line 21.
And the scanning signal lines 21 are arranged at the intersections of the video signal lines 22 and the scanning signal lines 21 are arranged in the same row.
Further, each video signal line 22 is connected to each switching element 12 arranged in the same column. In addition, each auxiliary capacity 14
The auxiliary capacity feed line 23 is connected to. In this example, the number of pixels of the display pixel group 10 is 320 × 240 dots.

The scanning signal drive circuit 30 includes a shift register 31, an analog buffer 32 and a plurality of scanning signal lines 21.
Is configured by a simultaneous selection circuit 33 and the like for selecting simultaneously, and basically, a scanning signal obtained by boosting a shift pulse from the shift register 31 by the analog buffer 32 is supplied to the scanning signal line 21.

The video signal drive circuit 40 includes a shift register 41, a buffer 42, a signal line 43 to which a video signal subjected to polarity inversion control is supplied, and an analog switch 4 which supplies a video signal potential to a hold capacitor 45 by a shift pulse.
4 and the like, and the potential sampled and held by the analog switch 44 and the hold capacitor 45 is supplied to the video signal line 22.

The control circuit 50 controls the scanning signal drive circuit 30 and the video signal drive circuit 40, and has a start pulse X- as a signal for controlling the video signal drive circuit 40.
START, clock signal X-CLK, polarity signal pol
The video signal Video, the start pulse Y-START and the clock signal Y-CLK are input as signals for controlling the scanning signal drive circuit 30, and the clock stop signal CLK-STP and the selection signal sel are input as described later. .

As shown in FIG. 1, in the present embodiment, the scanning signal drive circuit 30 is provided with a simultaneous selection circuit 33, and one shift pulse outputs a plurality of analog buffers 32.
To a plurality of scanning signal lines 21 at the same time. The simultaneous selection circuit 33 is provided between the shift register 31 and the analog buffer 32, and is composed of a group of branch circuits for transmitting shift pulses from each shift register stage to the next stage analog buffer. The branch circuits are simultaneously selected by the selection signal sel input to the scanning signal drive circuit 30 via the control circuit 50.

For example, when the simultaneous selection circuit 33 is provided from the nth stage of the shift register, the nth and subsequent analog buffers simultaneously select a plurality of scanning lines by the shift pulse of the nth stage. After the simultaneous scanning of the nth stage, the display pixel group performs display by the holding operation until the start timing of the next frame. In other words, by such simultaneous scanning,
In the display period from the nth stage to the final stage (240th stage in this example), no signals other than the signal for holding are needed.

As described above, by providing the simultaneous selection circuit 33, when the simultaneous selection circuit 33 is turned off, the normal display mode in which the entire screen is sequentially scanned line by line is set, and the simultaneous selection circuit 33 is turned on. When set to, the power saving display mode is set in which power consumption is reduced by stopping unnecessary signals.

When the simultaneous selection circuit 33 is provided, two problems may occur. A first problem is that when writing pixels in the nth stage and thereafter at the same time, insufficient writing of potential occurs in the video signal line, the scanning signal line, and the pixel.
The second problem is that the shift pulse of the analog buffer is delayed by the load in the simultaneous selection circuit toward the final stage.

In the present embodiment, in order to avoid the above-mentioned problem, the potential to be written from the video signal line to each pixel of the nth stage and thereafter is set to a predetermined potential corresponding to a predetermined display level, specifically, Is set to a potential corresponding to the white level. In this way, by setting the write signals of the nth stage to the 240th stage to the white level, the insufficient writing can be resolved after a few frames without causing a visual problem. Even if a delay occurs in the shift pulse, the white level is written in each of the pixels in the nth stage to the 240th stage, so such a delay in the shift pulse does not cause a visual problem. The white level may be set by changing the video signal Video input to the control circuit 50 to a signal corresponding to the white level.

FIG. 2 shows a display device 1 according to the present embodiment.
6 is a timing chart of a frame period. In FIG. 2, a clock signal X-CLK for the video signal driving circuit 40, a clock signal Y-CLK for the scanning signal driving circuit 30, a clock stop signal CLK-STP for stopping these clock signals, and scanning for scanning the scanning signal line 21. Signal (in the figure, the scanning signals of the first, second, and nth stages are shown), the video signal output from the video signal drive circuit 40 (inverted about a potential of 5 V for each frame), and display The pixel potential of the pixel 11 is shown.

In this way, in this example, both the clock signals X-CLK and Y-CLK are stopped after the n-th stage simultaneous selective scanning. This clock stop continues through the blanking period until the timing of the start of the next frame. In this example, both the scan signal drive circuit 30 and the video signal drive circuit 40 are configured with shift registers of CMOS clocked inverters, but there is no shoot-through current in these CMOS parts during the clock stop period. The current consumption in the drive circuit is, for example, 70% of the current consumption of the entire LCD
Since it occupies the degree, it is possible to reduce the power consumption by about n / 240 × 70%. The clock may be stopped at least for the scanning signal drive circuit.

As described above, in the present embodiment, a plurality of scanning signal lines are simultaneously selected by the selection signal and the clock signal after the simultaneous selection is stopped, so that, for example, a standby screen of a mobile phone is displayed. By applying such a function when only the minimum display is required, the power consumption can be significantly reduced. Also,
By supplying a potential corresponding to a predetermined display level such as a white level to the pixels selected by the simultaneous selection, it is possible to avoid problems due to insufficient writing and delay of the shift pulse.

(Second Embodiment) In the first embodiment described above, the position where the simultaneous selection circuit is provided is fixed in advance.
In the present embodiment, a non-volatile memory is provided in the simultaneous selection circuit so that the simultaneous selection start position can be changed. The basic configuration is similar to that of the first embodiment, and detailed description thereof is omitted. Hereinafter, FIGS.
This embodiment will be described with reference to FIG.

FIG. 3 is a diagram showing a part of the configuration of the scanning signal drive circuit in this embodiment. Non-volatile memory 6
1 is for holding the data written from the shift register 65 via the switch 62, and the data written to the non-volatile memory 61 is stored in the buffer 66 via the buffer 64 by switching the switch 63. It is being supplied.

4 to 6 are diagrams for explaining the operation of this embodiment. FIG. 4 shows a normal display mode in which the entire screen is sequentially scanned line by line, and FIG. 5 shows a writing mode performed before setting a power saving display mode (a mode in which simultaneous selection scanning and clock stop are performed to reduce power consumption). FIG. 6 shows the power saving display mode. Further, each figure (a) shows the signal supplied to the shift register in each mode, and each figure (b) shows the state of the switch in each mode, where n
It shows from the first stage to the final stage.

FIG. 4 shows the operation in the normal display mode. In the normal display mode, each switch 62
Is on the buffer 66 side for driving the scanning signal line, and each switch 63 is on the non-volatile memory 61 side. Shift pulses are sequentially shifted by the shift register 65, and scanning signals are sequentially output from the buffer 66 to the scanning signal line. It
The figure shows a state in which the nth stage is being scanned.

FIG. 5 shows the operation in the write mode. In the writing mode, a high-level (H-level) signal is written from the shift register 65 to each nonvolatile memory 61 connected to each scanning signal line that is simultaneously scanned in the period one frame before the power saving display mode. The figure shows an example of simultaneous scanning from the n-th stage to the final stage, and an H-level signal is written to the nonvolatile memory 61 from the n-th stage to the final stage-1 stage. The specific operation of this mode will be described below.

First, the shift register 65 sequentially shifts H level signals (write signals) according to the number of stages to be simultaneously scanned. After the H level signal is shifted to the final stage-1 stage, as shown in the figure, the switches 62 are switched to the non-volatile memory 61 side so that the H level signal is changed from the n stage to the final stage-1 stage. Write to the non-volatile memory 61. As a result, the switches 63 from the nth stage to the final stage-1 stage are set to the ON state. In this writing mode, the buffer 66 that drives the scanning signal line needs to be turned off. As a method thereof, the power supply voltage of the buffer 66 may be lowered or a circuit for turning off the buffer 66 may be provided.

FIG. 6 shows the operation in the power saving display mode following the write mode. In the power saving display mode, the data written in the nonvolatile memory 61 causes the switches 63 from the nth stage to the final stage-1 stage to be in the ON state. Therefore, up to the (n-1) th stage, the shift pulse is sequentially shifted by the shift register 65 and the scanning signal is sequentially output from the buffer 66 to the scanning signal line.
The shift pulse is transmitted to the final stage through the buffer 64 from the first stage to the final stage-1 stage, and the scanning signal is output from the buffer 66 that drives the scanning signal lines from the nth stage to the final stage to perform simultaneous scanning. Is done. Note that stopping the clock signals to the scanning signal drive circuit and the video signal drive circuit after the simultaneous scanning is the same as in the first embodiment.

The normal display mode, the writing mode, and the power saving display mode are executed as described above. However, when returning from the power saving display mode to the normal display mode, the processing reverse to the above processing may be performed. . That is, a low-level (L-level) signal may be written to each nonvolatile memory 61 in the period one frame before returning to the normal display mode.

As described above, in the present embodiment, the effect of reducing the power consumption can be obtained as in the first embodiment, and the start positions of the simultaneously selected scanning signal lines can be made variable. Therefore, the degree of freedom in setting the display state can be increased as compared with the first embodiment. Also,
The drive mode (operation mode) of each scanning stage (driving stage) in the power saving display mode is set, that is, scanning is performed sequentially at a different timing from other scanning stages (normal driving mode) or simultaneously with other scanning stages. The setting (setting to the non-volatile memory) as to whether or not (simultaneous selection drive mode) is performed using a shift register. Therefore, the shift register can be shared for both the normal shift pulse shift operation and the mode setting operation, and it is possible to reduce power consumption and suppress an increase in circuit scale.

(Third Embodiment) In the above-described second embodiment, only the start position of simultaneous selection can be changed, but this embodiment makes it possible to simultaneously select arbitrary scanning signal lines. is there. The basic configuration is similar to that of the first embodiment, and detailed description thereof is omitted.

The present embodiment will be described below with reference to FIGS. 7 and 8. In the present embodiment, modes corresponding to the writing mode and the power saving display mode in the second embodiment will be referred to as pre-still mode and still mode, respectively.

FIG. 7 is a diagram showing a configuration example of one stage of the scanning signal drive circuit in this embodiment.

Information regarding whether to perform normal driving or simultaneous selection driving is set in each stage. Therefore, the output signal from the digital memory (nonvolatile memory) 71, the data holding portion 72 of the shift register, and the digital memory 71 is set. Transistor 7 controlled by X (/ X is H level in normal driving)
3 and 74, a transistor 75 controlled by an output signal X from the digital memory 71 (X is an H level in the case of simultaneous selection drive) and a shift / select signal is input, a transistor 76 controlled by a normal signal, and an / X signal. Controlled transistor 77, transistor 78 controlled by the pre-still signal, transistor 7 controlled by the X signal and receiving the still-on signal
9, and buffers 80 and 81.

The shift / select signal is used not only as a shift pulse but also for setting the simultaneous selection drive mode in the digital memory 71 in the pre-still mode. The normal signal is used as a signal for transmitting the output of the shift register to the buffer 81 connected to the scanning signal line in the normal driving state (/ X is at the H level). The pre-still signal is used to set the information of each stage of the shift register in the digital memory 71 in the pre-still mode, and the still-on signal sets each scanning signal line simultaneously selected and scanned in the still mode to the H level. Used for.

The operation of this embodiment will be described below with reference to the timing charts shown in FIGS. 8 (a) to 8 (d).

FIG. 8A shows the operation in the normal display mode. In this mode, the normal signal is at H level and the output / X of the digital memory 71 is at H level.
Since it is at the level, both the transistors 76 and 77 are turned on, and a shift pulse (shift / select signal) is sent from the shift register to the transistors 76 and 77.
Is transmitted to the analog buffer 81 via. As a result, a scanning signal is sequentially sent from each scanning stage to the scanning signal line for each line.

FIG. 8 (b) shows the operation of the scanning stage in which the simultaneous selection drive mode is set in the pre-still mode. Note that in FIG. 8B, the signal indicated by shift / select is not the shift / select signal itself shown in FIG. 7, but the signal output from the transistor 78 according to the shift / select signal (C in FIG. 7). Point signal)
Is shown.

In the pre-still mode, the driving mode is written in the digital memory 71 of each scanning stage in one frame period. That is, "1" (H level) is written in the digital memory 71 for the scanning stage that performs the simultaneous selection drive (still operation), and "0" (L level) is written for the scanning stage that performs the normal drive (normal operation). Written. Specifically, first, information (1 or 0) corresponding to the driving mode of each scanning stage is sequentially shifted as a shift / select signal in the shift register, and finally held in the holding unit 72 of the shift register. Then, by turning on the pre-still signal at the last timing of one frame, the information held in each holding unit 72 is written in the digital memory 71. In this mode, since the normal signal is at the L level and the still-on signal is at the L level, the signal at the point A in FIG. 7 is held at the L level, the writing operation to the display pixel is not performed, and the previous frame is used. The voltage written in each pixel is held in each pixel.

FIG. 8 (c) shows the operation of the scanning stage in which the simultaneous selection drive is performed in the still mode following the pre-still mode. “0” in the digital memory 71
In the scanning stage in which (L level) is written, that is, the scanning stage in which the normal drive mode is set, since the output / X of the digital memory 71 is at the H level, the transistors 73, 74 and 77 are turned on, The shift pulse is sent to the scanning signal line through the transistor 77, the buffer 81, and the like. On the other hand, in the scanning stage in which “1” (H level) is written in the digital memory 71, that is, in the scanning stage in which the simultaneous selection drive mode is set, as shown in FIG. 71 outputs / X
Is at the L level and the output X is at the H level, the transistors 75 and 74 are in the off state, the transistor 75 is in the on state, and the shift pulse is directly transmitted to the point B through the transistor 75.

FIG. 8D shows the operation at the last timing of one frame period of the scanning stage in which the simultaneous selection drive is performed in the still mode. That is, in each scanning stage in which the simultaneous selection driving is performed, the still-on signal (H level) is transmitted to the point A via the transistor 79 and further output to the scanning signal line via the buffer 81. Also, at this timing, for example, a white level signal is output to the video signal line.

As can be seen from the above description, in the still mode, in the scan stage in which the normal drive mode is set, predetermined information is displayed in accordance with the normal drive, and the scan in which the simultaneous selection drive mode is set. In the dan,
Scanning is performed all at once in the last period of one frame, and, for example, white display is performed.

As described above, in the present embodiment, not only the effect of reducing the power consumption can be obtained as in the first embodiment, but also the scanning signal lines for simultaneous selection can be arbitrarily set, so that the second embodiment can be used. It is possible to set the display with a higher degree of freedom than the embodiment. Further, as in the second embodiment, the setting of the scanning signal line for simultaneous selection is performed using the shift register, so that the circuit scale can be suppressed from increasing by sharing the shift register.

Further, since the scanning signal lines for simultaneous selection can be arbitrarily set, the following effects can be obtained.
First, since the scanning signal line for simultaneous scanning can be moved,
It is possible to prevent the burn-in phenomenon of the liquid crystal display device caused by using the same region for a long time. That is, not only the chemical burn-in of the liquid crystal and the alignment film, but also the T
It is possible to prevent physical image sticking such as shift of Vth characteristic of FT. Further, when the present method is applied to an organic EL type element, it is possible to cope with a burn-in phenomenon due to a shift of a brightness lowering curve caused by continuous use of the same element. Secondly, since the scanning signal line for simultaneous scanning can be moved, simultaneous scanning can be applied not only to the lower part of the display screen but also to the upper part or the middle part. Therefore, the present method can be applied not only to the standby screen of the mobile phone but also to the operation screen, for example.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG.

In the present embodiment, the liquid crystal display device main body 101
In addition to the frame memory 111 that supplies image information (video signal) to the display area 102, the scanning signal drive circuit 103, the video signal drive circuit 104, and the control circuit 105,
It has a frame memory 112 for holding image information of a frame before the image information held in the frame memory 111. The image information of the frame memory 111 and the frame memory 112 is sent to the difference detection unit 113, and the difference between frames is detected. The difference information detected by the difference detection unit 113 is sent to the information acquisition unit 114, and the information necessary for controlling the liquid crystal display device body 101 is acquired. Based on the information from the information acquisition unit 114, the control circuit 105 selectively rewrites only the scanning stage for which the difference is detected (that is, the scanning stage where the image information has changed).

For the above-described selective rewriting, the scanning signal drive circuit 103 may have the same configuration as that of the scanning signal drive circuit shown in the third embodiment, for example. That is, with respect to the digital memory 71 shown in FIG. 7, "0" (L level) is set for the scanning stage where rewriting is performed, and "1" (H level) is set for the scanning stage where rewriting is not performed. As a result, similarly to the operation described in the third embodiment, the image signal is written in each pixel by sequential scanning in the scanning stage for rewriting as in the normal case, and the sequential scanning is not performed in the scanning stage without rewriting. Not done However, in the third embodiment, the transistor 79 is turned on at the end of one frame to supply the still-on signal to the scanning signal line. However, in the present embodiment, the scanning stage that is not rewritten does not have the previous frame. In order to hold the display of, the operation of supplying such a still-on signal is not performed. For selective rewriting, it is possible to use a decode type scanning signal drive circuit instead of the shift register type scanning signal drive circuit as described above.

Although the image information is maintained by the holding operation in the pixels which are not rewritten, the pixel constituent elements such as TFT are designed in advance so that the holding operation for several frames can be performed. You can leave it. Further, in the case where the writing operation is not performed for a period longer than the period in which the holding operation can be performed, the refresh operation may be performed to perform the writing every predetermined period. Furthermore, when liquid crystal having a memory effect, such as ferroelectric liquid crystal, is used, such refresh processing is unnecessary.

As described above, in the present embodiment, since the rewriting process is performed only for the scanning stage in which the difference is detected,
As in the first to third embodiments, it is possible to significantly reduce power consumption.

In the above first to fourth embodiments,
The simultaneous selection process and the process without rewriting have been described for the scanning signal drive circuit, but the same can be applied to the video signal drive circuit. For example, as can be seen from FIG. 1, in the scanning signal drive circuit 30, the simultaneous selection circuit 33 is provided between the shift register 31 and the buffer 32. On the other hand, the video signal drive circuit 40 is also provided with a shift register 41 and a buffer 42. Therefore, also for the video signal drive circuit, the simultaneous selection circuit similar to the scanning signal drive circuit and the like is provided between the shift register and the buffer, so that the first to fourth embodiments have been described. It is possible to apply such simultaneous selection processing and processing that does not rewrite. In this case, the clock may be stopped at least for the video signal drive circuit. Further, it is of course possible to apply such processing to both the scanning signal drive circuit and the video signal drive circuit.

Further, in the above first to fourth embodiments,
Although the liquid crystal display device has been described as an example, the above-described method is similarly applicable to a display device of a type that performs display by a potential holding operation, such as an organic EL display device.

Although the embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed constituent features. For example, even if some constituents are deleted from the disclosed constituents, any invention can be extracted as an invention as long as a predetermined effect can be obtained.

[0057]

According to the present invention, it is possible to effectively reduce the power consumption of an active matrix type display device, and to reduce the operating time when applied to a display device for mobile equipment such as a mobile phone. Can be significantly increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a part of a configuration example of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining an operation example of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 5 is a diagram for explaining an operation example of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 6 is a diagram for explaining an operation example of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 7 is a diagram showing a part of a configuration example of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a timing chart showing an operation example of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration example of a liquid crystal display device according to a fourth embodiment of the present invention.

[Explanation of symbols]

10 ... Display pixel group 11 ... Display pixel 12 ... Switching element 13 ... Pixel electrode 14 ... Auxiliary capacitor 21 ... Scan signal line 22 ... Image signal line 23 ... Auxiliary capacitor power supply line 30 ... Scan signal drive circuit 31 ... Shift register 32 ... Analog Buffer 33 ... Simultaneous selection circuit 40 ... Video signal drive circuit 41 ... Shift register 42 ... Buffer 43 ... Signal line 44 ... Analog switch 45 ... Hold capacity 50 ... Control circuit 61 ... Nonvolatile memory 62, 63 ... Switches 64, 66 ... Buffer 65 ... Shift register 71 ... Digital memory 72 ... Shift register data holding unit 73-79 ... Transistors 80, 81 ... Buffer 101 ... Liquid crystal display device main body 102 ... Display area 103 ... Scan signal drive circuit 104 ... Video signal drive circuit 105 ... Control circuits 111, 112 ... Frame memory 113 ... Minute detection unit 114 ... information acquisition unit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 622E 623 623U F term (reference) 2H093 NC09 NC11 NC15 NC22 NC28 ND39 NG20 5C006 AC23 BB16 BC03 BC16 BF02 BF03 BF04 BF24 BF37 FA47 5C080 AA10 BB05 DD26 FF11 JJ02 JJ03 JJ04 KK47

Claims (6)

[Claims] 1. A display pixel group arranged in a matrix, a first drive circuit for outputting a scanning signal to the display pixel group via a scanning signal line, and a display signal group to the display pixel group via a video signal line. A second drive circuit that outputs a video signal, and an active matrix type display device comprising: a first drive circuit and a second drive circuit, wherein at least one of the first and second drive circuits operates based on an input clock signal. A display device comprising: a drive stage, and a selection unit that selects at least two drive stages, and a clock stop unit that stops the clock signal. 2. A means for setting a potential of a display pixel group connected to drive stages simultaneously selected by the selecting means to a potential corresponding to a predetermined display level. Display device described. 3. The drive stage includes a shift register circuit that shifts data for sequentially selecting the drive stage, and a buffer circuit to which the data output from the shift register circuit is input, The display device according to claim 1, wherein the means is provided between the shift register circuit and the buffer circuit. 4. The display device according to claim 3, wherein the selection means has a holding means for holding selection information. 5. A display pixel group arranged in a matrix, a first drive circuit for outputting a scanning signal to the display pixel group via a scanning signal line, and a display signal group to the display pixel group via a video signal line. A second drive circuit that outputs a video signal, and an active matrix display device comprising: a first drive circuit and a second drive circuit, wherein at least one of the first drive circuit and the second drive circuit can set a plurality of operation modes. A display device characterized by being present and configured to set an operation mode of each drive stage by a shift register. 6. A display pixel group arranged in a matrix, a first drive circuit for outputting a scanning signal to the display pixel group via a scanning signal line, and a display signal group to the display pixel group via a video signal line. A second drive circuit that outputs a video signal, a video signal holding unit that holds the video signals for a plurality of frames, and a difference detection unit that detects a difference between frames of the video signal held by the video signal holding unit. And an active matrix type display device including: and at least one of the first drive circuit and the second drive circuit is capable of setting a plurality of operation modes, and is detected by the difference detection means. A display device configured to operate by associating the generated difference information with the operation mode.