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JP2003017754A - Surface mount semiconductor device - Google Patents

Surface mount semiconductor device

Info

Publication number
JP2003017754A
JP2003017754A JP2001203272A JP2001203272A JP2003017754A JP 2003017754 A JP2003017754 A JP 2003017754A JP 2001203272 A JP2001203272 A JP 2001203272A JP 2001203272 A JP2001203272 A JP 2001203272A JP 2003017754 A JP2003017754 A JP 2003017754A
Authority
JP
Japan
Prior art keywords
electrode
bonding electrode
substrate
die bonding
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001203272A
Other languages
Japanese (ja)
Other versions
JP4959071B2 (en
Inventor
Hiromoto Ishinaga
宏基 石長
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2001203272A priority Critical patent/JP4959071B2/en
Publication of JP2003017754A publication Critical patent/JP2003017754A/en
Application granted granted Critical
Publication of JP4959071B2 publication Critical patent/JP4959071B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483Containers
    • H01L33/486Containers adapted for surface mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the density of a surface mount light emitting device mounted on a circuit board. SOLUTION: A front surface-side opening end 14a and a rear surface-side opening end 14b of a first through hole 14 are arranged on the respective surfaces of die bonding electrode 18 and a first surface mount electrode 22 which are formed in a substrate 12, and an LED chip 30 is bonded on the die bonding electrode 18. Thus, a space for forming the die bonding electrode 18 on the substrate 12 and a space for connecting electrically the die bonding electrode 18 and first surface mounting electrode 22 can be used in common, resulting in making the horizontal width of the substrate 12 smaller by common space. Then, the first surface mount electrode 22 can be connected with the wiring pattern 40a of a circuit board 38 with solder 42a, so that no space is needed for soldering excluding mounting of a light emitting device 10 to the circuit board 38.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、面実装型半導体装置
に関し、特にたとえば発光ダイオードやトランジスタ等
が含む基板の表面に形成されたダイボンディング電極お
よびワイヤボンディング電極と、裏面に形成された第1
および第2面実装用電極とが、互いに対応するものどう
しがスルーホール内に形成された接続電極によって電気
的に接続された、面実装型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount semiconductor device, and more particularly to a die bonding electrode and a wire bonding electrode formed on the front surface of a substrate including, for example, a light emitting diode, a transistor and the like, and a first surface formed on the back surface.
Also, the present invention relates to a surface-mounting semiconductor device in which corresponding electrodes are electrically connected to each other by a connection electrode formed in a through hole.

【0002】[0002]

【従来技術】従来の面実装型半導体発光装置の一例を図
3および図4に示す。この面実装型半導体発光装置(以
下、単に「発光装置」と言う。)1は、基板2を含み、
基板2の各端部2aおよび2bには、一対の電極3およ
び4が形成されている。電極3および4は、それぞれ端
子部3aおよび4aを含み、各端子部3aおよび4aの
幅方向中央部には、ワイヤボンディング電極3bおよび
引出し部4bが形成されている。そして、引出し部4b
の先端にはダイボンディング電極4cが形成されてい
る。
2. Description of the Related Art An example of a conventional surface mount semiconductor light emitting device is shown in FIGS. The surface mount semiconductor light emitting device (hereinafter, simply referred to as “light emitting device”) 1 includes a substrate 2,
A pair of electrodes 3 and 4 is formed on each end 2 a and 2 b of the substrate 2. The electrodes 3 and 4 include terminal portions 3a and 4a, respectively, and a wire bonding electrode 3b and a lead-out portion 4b are formed in the center portion in the width direction of each terminal portion 3a and 4a. And the drawer 4b
A die bonding electrode 4c is formed at the tip of the.

【0003】そして、ダイボンディング電極4cには、
半導体発光素子チップ(以下、「LEDチップ」と言
う。)6がダイボンディングされて、その底面電極が電
極4と電気的に接続されている。そして、LEDチップ
6の上面電極と電極3のワイヤボンディング電極3bと
がワイヤ5を介して電気的に接続されている。さらに、
ワイヤボンディング電極3b,引出し部4b,ダイボン
ディング電極4c,ワイヤ5およびLEDチップ6等
が、透光性の合成樹脂からなる被覆部7により封止され
ている。
The die bonding electrode 4c has
A semiconductor light emitting element chip (hereinafter referred to as “LED chip”) 6 is die-bonded, and its bottom electrode is electrically connected to the electrode 4. The upper surface electrode of the LED chip 6 and the wire bonding electrode 3b of the electrode 3 are electrically connected via the wire 5. further,
The wire bonding electrode 3b, the lead-out portion 4b, the die bonding electrode 4c, the wire 5, the LED chip 6 and the like are sealed by a covering portion 7 made of a transparent synthetic resin.

【0004】このような発光装置1は、端子部3aおよ
び4aのそれぞれの側面部3eおよび4eと、回路基板
8の配線パターン8aおよび8bのそれぞれとが半田9
aおよび9bにより電気的に接続される。なお、それぞ
れの端子部3aおよび4aは、基板2の表面に形成され
た表面部3d,4d,基板2の側面に形成された側面部
3e,4e,および基板2の裏面に形成された裏面部3
f,4fからなっている。
In such a light emitting device 1, the side surface portions 3e and 4e of the terminal portions 3a and 4a and the wiring patterns 8a and 8b of the circuit board 8 are soldered 9 respectively.
It is electrically connected by a and 9b. The respective terminal portions 3a and 4a are surface portions 3d and 4d formed on the front surface of the substrate 2, side surface portions 3e and 4e formed on the side surfaces of the substrate 2, and a back surface portion formed on the back surface of the substrate 2. Three
It consists of f and 4f.

【0005】[0005]

【発明が解決しようとする課題】しかし、図4に示すよ
うに、従来の発光装置1では、基板2の各端部2a,2
bが、被覆部7の各側面よりも外側に突出して形成され
ているので、この各端部2a,2bの突出量分L1,L
2が発光装置1の横幅を広くしている一因となってい
る。そして、端子部3a,4aのそれぞれの側面部3
e,4eと、回路基板8の配線パターン8a,8bのそ
れぞれとが半田9a,9bによって電気的に接続される
ので、この半田9a,9bのスペースL3,L4が回路
基板8上に必要とされる。このように、従来の発光装置
1では、横幅がL1,L2だけ広くなっており、しかも
回路基板8上に半田9a,9bのスペースL3,L4を
必要とするので、回路基板8に実装される発光装置1等
の実装密度を上げるための妨げとなっている。
However, as shown in FIG. 4, in the conventional light emitting device 1, the end portions 2a, 2 of the substrate 2 are formed.
Since b is formed so as to project outward from each side surface of the covering portion 7, the protrusion amounts L1 and L of the end portions 2a and 2b are formed.
2 is one of the reasons for widening the width of the light emitting device 1. Then, the side surface portion 3 of each of the terminal portions 3a and 4a
e, 4e and the wiring patterns 8a, 8b of the circuit board 8 are electrically connected by the solders 9a, 9b, the spaces L3, L4 of the solders 9a, 9b are required on the circuit board 8. It As described above, in the conventional light emitting device 1, the lateral width is widened by L1 and L2, and the spaces L3 and L4 of the solders 9a and 9b are required on the circuit board 8. Therefore, the light emitting apparatus 1 is mounted on the circuit board 8. This is an obstacle to increasing the packaging density of the light emitting device 1 and the like.

【0006】それゆえに、この発明の主たる目的は、面
実装型半導体装置の横幅を狭くするとともに、回路基板
上に半田のためのスペースを必要としない、面実装型半
導体装置を提供することである。
Therefore, a main object of the present invention is to provide a surface-mounting type semiconductor device which narrows the lateral width of the surface-mounting type semiconductor device and does not require a space for soldering on a circuit board. .

【0007】[0007]

【課題を解決するための手段】第1の発明は、基板、基
板の表面に形成されたダイボンディング電極およびワイ
ヤボンディング電極、ダイボンディング電極にダイボン
ディングされた半導体素子チップ、半導体素子チップと
ワイヤボンディング電極とを電気的に接続するワイヤ、
基板の裏面に形成された第1および第2面実装用電極、
基板を貫通し、両側のそれぞれの開口端部がダイボンデ
ィング電極および第1面実装用電極のそれぞれの面内に
配置された第1スルーホール、基板を貫通し、両側のそ
れぞれの開口端部がワイヤボンディング電極および第2
面実装用電極のそれぞれの面内に配置された第2スルー
ホール、第1スルーホール内に形成され、ダイボンディ
ング電極と第1面実装用電極とを電気的に接続する第1
接続電極、ならびに第2スルーホール内に形成され、ワ
イヤボンディング電極と第2面実装用電極とを電気的に
接続する第2接続電極を備える、面実装型半導体装置で
ある。
A first invention is a substrate, a die bonding electrode and a wire bonding electrode formed on the surface of the substrate, a semiconductor element chip die-bonded to the die bonding electrode, and a semiconductor element chip and wire bonding. Wires that electrically connect to the electrodes,
First and second surface mounting electrodes formed on the back surface of the substrate,
First through-holes penetrating the substrate and having opening ends on both sides arranged in respective surfaces of the die bonding electrode and the first surface-mounting electrode, penetrating the substrate, and opening ends on both sides. Wire bonding electrode and second
A first through hole is formed in the second through hole and the first through hole arranged in each surface of the surface mounting electrode, and electrically connects the die bonding electrode and the first surface mounting electrode.
It is a surface-mounting type semiconductor device comprising a connection electrode and a second connection electrode formed in the second through hole and electrically connecting the wire bonding electrode and the second surface-mounting electrode.

【0008】[0008]

【作用】この発明によると、第1スルーホールの両側の
それぞれの開口端部がダイボンディング電極および第1
面実装用電極のそれぞれの面内に配置されており、第1
スルーホール内に形成された第1接続電極によってダイ
ボンディング電極と第1面実装用電極とが電気的に接続
されている。これによって、ダイボンディング電極を基
板上に形成するためのスペースと、ダイボンディング電
極と第1面実装用電極とを電気的に接続するためのスペ
ースとを共用することができる。したがって、ダイボン
ディング電極を形成するためのスペース以外に、ダイボ
ンディング電極と第1面実装用電極とを接続するための
スペース(図4に示す端部2bに相当するスペースL
2)を別個に確保する必要がなく、その分だけ基板の面
方向の寸法を小さくすることができる。
According to the present invention, the opening end portions on both sides of the first through hole have the die bonding electrode and the first
First electrodes are arranged on the respective surfaces of the surface mounting electrodes.
The die bonding electrode and the first surface mounting electrode are electrically connected by the first connection electrode formed in the through hole. Thereby, the space for forming the die bonding electrode on the substrate and the space for electrically connecting the die bonding electrode and the first surface mounting electrode can be shared. Therefore, in addition to the space for forming the die bonding electrode, a space for connecting the die bonding electrode and the first surface mounting electrode (a space L corresponding to the end portion 2b shown in FIG. 4).
It is not necessary to separately secure 2), and the dimension in the plane direction of the substrate can be reduced accordingly.

【0009】そして、第2スルーホールの両側のそれぞ
れの開口端部がワイヤボンディング電極および第2面実
装用電極のそれぞれの面内に配置されており、第2スル
ーホール内に形成された第2接続電極によってワイヤボ
ンディング電極と第2面実装用電極とが電気的に接続さ
れている。これによって、ワイヤボンディング電極を基
板上に形成するためのスペースと、ワイヤボンディング
電極と第2面実装用電極とを電気的に接続するためのス
ペースとを共用することができる。したがって、ワイヤ
ボンディング電極を形成するためのスペース以外に、ワ
イヤボンディング電極と第2面実装用電極とを接続する
ためのスペース(図4に示す端部2aに相当するスペー
スL1)を別個に確保する必要がなく、その分だけ基板
の面方向の寸法を小さくすることができる。
The opening end portions on both sides of the second through hole are arranged in the respective surfaces of the wire bonding electrode and the second surface mounting electrode, and the second opening formed in the second through hole is formed. The wire bonding electrode and the second surface mounting electrode are electrically connected by the connection electrode. Thereby, the space for forming the wire bonding electrode on the substrate and the space for electrically connecting the wire bonding electrode and the second surface mounting electrode can be shared. Therefore, in addition to the space for forming the wire bonding electrode, a space for connecting the wire bonding electrode and the second surface mounting electrode (a space L1 corresponding to the end portion 2a shown in FIG. 4) is separately secured. There is no need, and the dimension in the plane direction of the substrate can be reduced accordingly.

【0010】また、基板の裏面に形成された第1および
第2面実装用電極が回路基板に形成された配線パターン
に電気的に接続されるので、この面実装型半導体装置を
実装するためのスペース以外に、図4に示す半田9b,
9aのスペースL4,L3を回路基板上に確保する必要
がない。
Further, since the first and second surface mounting electrodes formed on the back surface of the substrate are electrically connected to the wiring pattern formed on the circuit board, the surface mounting type semiconductor device can be mounted. In addition to the space, the solder 9b shown in FIG.
It is not necessary to secure the spaces L4 and L3 of 9a on the circuit board.

【0011】[0011]

【発明の効果】この発明によれば、図4に示す従来の発
光装置1の端部2a,2bに相当するスペースL1,L
2だけ基板の面方向の寸法を短くすることができるし、
回路基板上において半田9a,9bのスペースL3,L
4を不用とすることができる。したがって、回路基板に
実装される面実装型半導体装置の実装密度を従来よりも
上げることができる。
According to the present invention, the spaces L1 and L corresponding to the ends 2a and 2b of the conventional light emitting device 1 shown in FIG.
The size of the board in the plane direction can be shortened by 2 and
Spaces L3, L for the solder 9a, 9b on the circuit board
4 can be dispensed with. Therefore, the mounting density of the surface-mounting type semiconductor device mounted on the circuit board can be increased more than ever before.

【0012】この発明の上述の目的,その他の目的,特
徴および利点は、図面を参照して行う以下の実施例の詳
細な説明から一層明らかとなろう。
The above-mentioned objects, other objects, features and advantages of the present invention will become more apparent from the detailed description of the embodiments below with reference to the drawings.

【0013】[0013]

【実施例】図1および図2に示すこの実施例の面実装型
半導体発光装置(以下、単に「発光装置」と言う。)1
0は、携帯電話機やPHS等のような携帯用電子機器の
照明等に適したものであり、絶縁性の基板12を含む。
基板12は、ガラスクロスなどに耐熱性のBT樹脂を含
浸させたBTレジン,ガラスエポキシ等からなり、その
サイズ(奥行き×横幅×厚み)は、近年の小型化の要請
に応じて、たとえば1.25mm×2.0mm×0.8
mm、または0.8mm×1.6mm×0.8mm程度
と小さく設定されている。この発光装置10は、10c
m×5cm程度の大きさの基板母材に多数の発光素子チ
ップ(以下、「LEDチップ」と言う。)等を奥行き方
向と横幅方向とにマトリクス状に設け、この基板母材を
切断することにより得られる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A surface mount type semiconductor light emitting device (hereinafter referred to simply as "light emitting device") 1 of this embodiment shown in FIGS.
0 is suitable for illumination of portable electronic devices such as mobile phones and PHS, and includes an insulating substrate 12.
The substrate 12 is made of BT resin, glass epoxy, or the like in which glass cloth or the like is impregnated with heat-resistant BT resin, and the size (depth × width × thickness) thereof is, for example, 1. 25 mm x 2.0 mm x 0.8
mm, or about 0.8 mm × 1.6 mm × 0.8 mm. This light emitting device 10 is 10c
A large number of light emitting element chips (hereinafter, referred to as “LED chips”) and the like are provided in a matrix form in a depth direction and a width direction on a substrate base material of about m × 5 cm, and the substrate base material is cut. Is obtained by

【0014】基板12には、互いに間隔を隔ててこの基
板12を貫通する一対の第1スルーホール14および第
2スルーホール16が形成されている。この第1および
第2スルーホール14,16のそれぞれの基板12の表
面で開口する表面側開口端部14a,16aは、基板1
2の表面に形成されているダイボンディング電極18お
よびワイヤボンディング電極20のそれぞれの面内に配
置されており、それぞれの対応する電極18,20によ
って覆われている。そして、各スルーホール14,16
のそれぞれの表面側開口端部14a,16aは、各電極
18,20のそれぞれの中央に位置している。また、第
1および第2スルーホール14,16のそれぞれの基板
12の裏面で開口する裏面側開口端部14b,16b
は、基板12の裏面に形成されている第1面実装用電極
22および第2面実装用電極24のそれぞれの面内に配
置されており、それぞれの対応する電極22,24によ
って覆われている。そして、各スルーホール14,16
のそれぞれの裏面側開口端部14b,16bも、第1お
よび第2面実装用電極22,24のそれぞれの中央に位
置している。
The substrate 12 is formed with a pair of first through holes 14 and second through holes 16 penetrating the substrate 12 at intervals. The surface-side opening end portions 14a and 16a that open on the surface of the substrate 12 of the first and second through holes 14 and 16 are
The die bonding electrode 18 and the wire bonding electrode 20 formed on the surface of the second electrode 2 are arranged in the respective surfaces and are covered with the corresponding electrodes 18, 20. And each through hole 14, 16
The front surface side open end portions 14a and 16a of the respective electrodes are located at the centers of the respective electrodes 18 and 20. In addition, the back surface side opening end portions 14b and 16b that open on the back surface of the substrate 12 of the first and second through holes 14 and 16 respectively.
Are arranged on the respective surfaces of the first surface-mounting electrode 22 and the second surface-mounting electrode 24 formed on the back surface of the substrate 12, and are covered by the respective corresponding electrodes 22 and 24. . And each through hole 14, 16
The respective rear side opening end portions 14b and 16b are also located at the centers of the first and second surface mounting electrodes 22 and 24, respectively.

【0015】また、第1および第2スルーホール14,
16のそれぞれの内周面には、第1接続電極26および
第2接続電極28が形成されている。この第1接続電極
26は、ダイボンディング電極18と第1面実装用電極
22とを電気的に接続している。そして、第2接続電極
28は、ワイヤボンディング電極20と第2面実装用電
極24とを電気的に接続している。
Also, the first and second through holes 14,
A first connection electrode 26 and a second connection electrode 28 are formed on each inner peripheral surface of 16. The first connection electrode 26 electrically connects the die bonding electrode 18 and the first surface mounting electrode 22. The second connection electrode 28 electrically connects the wire bonding electrode 20 and the second surface mounting electrode 24.

【0016】ダイボンディング電極18の上面には、上
面発光型のLEDチップ30が載置されてダイボンディ
ングされている。このLEDチップ30は、その底面電
極とダイボンディング電極18とが電気的に接続されて
いる。また、LEDチップ30の表面電極30aとワイ
ヤボンディング電極20とが金線等のワイヤ32でワイ
ヤボンディングされている。そして、基板12の上面全
体には、透光性の合成樹脂(たとえばエポキシ樹脂)か
らなる被覆部34が装着され、この被覆部34によって
LEDチップ30,ワイヤ32,ダイボンディング電極
18およびワイヤボンディング電極20が密封され、こ
の被覆部34を通して、主として上面から、光が発光さ
れる。
On the upper surface of the die bonding electrode 18, a top emitting LED chip 30 is placed and die bonded. The bottom electrode of the LED chip 30 and the die bonding electrode 18 are electrically connected. The surface electrode 30a of the LED chip 30 and the wire bonding electrode 20 are wire-bonded with a wire 32 such as a gold wire. A covering portion 34 made of a transparent synthetic resin (for example, epoxy resin) is mounted on the entire upper surface of the substrate 12, and the LED chip 30, the wires 32, the die bonding electrode 18, and the wire bonding electrode are covered by the covering portion 34. 20 is sealed, and light is mainly emitted from the upper surface through the covering portion 34.

【0017】また、図1(B)に示すように、LEDチ
ップ30、ダイボンディング電極18およびワイヤボン
ディング電極20のそれぞれの平面形状は、略正方形で
ある。そして、ダイボンディング電極18の平面形状
は、LEDチップ30およびワイヤボンディング電極2
0の平面形状よりも少し大きく形成されている。そし
て、図2に示すように、第1および第2面実装用電極2
2,24の平面形状は、略正方形であり、ダイボンディ
ング電極18と同じ大きさである。そして、基板12の
平面形状は矩形である。この基板12の横幅方向と平行
する基板12の中心線36上に第1および第2スルーホ
ール14,16のそれぞれの中心が位置している。ま
た、平面方向から見て、第1スルーホール14の中心に
ダイボンディング電極18,第1面実装用電極22およ
びLEDチップ30のそれぞれの中心が位置するように
それぞれが配置されている。さらに、第2スルーホール
16の中心にワイヤボンディング電極20および第2面
実装用電極24のそれぞれの中心が位置するようにそれ
ぞれが配置されている。そして、これら基板12,LE
Dチップ30,ダイボンディング電極18,ワイヤボン
ディング電極20,ならびに第1および第2面実装用電
極22,24は、それぞれを平面方向から見て各辺の対
応するものどうしが互いに平行する状態で配置されてい
る。
As shown in FIG. 1 (B), the LED chips 30, the die bonding electrodes 18 and the wire bonding electrodes 20 each have a substantially square planar shape. The plan shape of the die bonding electrode 18 is the LED chip 30 and the wire bonding electrode 2
It is formed to be slightly larger than the plane shape of 0. Then, as shown in FIG. 2, the first and second surface mounting electrodes 2 are provided.
The planar shapes of 2 and 24 are substantially square and have the same size as the die bonding electrode 18. The plane shape of the substrate 12 is rectangular. The centers of the first and second through holes 14 and 16 are located on the center line 36 of the substrate 12 which is parallel to the lateral width direction of the substrate 12. Further, the die bonding electrodes 18, the first surface-mounting electrodes 22, and the LED chips 30 are arranged so that their respective centers are located at the centers of the first through holes 14 when viewed from the plane direction. Further, the wire bonding electrode 20 and the second surface-mounting electrode 24 are arranged so that their respective centers are located at the centers of the second through holes 16. Then, these substrates 12, LE
The D chip 30, the die bonding electrode 18, the wire bonding electrode 20, and the first and second surface mounting electrodes 22 and 24 are arranged in a state where corresponding ones of the respective sides are parallel to each other when viewed from the plane direction. Has been done.

【0018】ここで、図1(B)に示すように、ダイボ
ンディング電極18の一辺の長さM1をLEDチップ3
0の一辺の長さM2よりも大きくしているが、このよう
に大きくしているのは、LEDチップ30のボンディン
グ位置が多少ずれてもLEDチップ30をダイボンディ
ング電極18上に確実にボンディングできるようにする
ともに、両者を接着する導電性接着剤が基板12上に流
れ落ちないようにするための余裕分であり、最低必要と
される余裕分だけ大きくしている。そして、基板12の
左右の各側面12a,12bと、これら各側面12a,
12bと隣合うダイボンディング電極18およびワイヤ
ボンディング電極20の各側縁との間隔N1,N2は、
基板母材を切断して基板12を形成するときの切断位置
のばらつきを許容するための余裕分であり、最低必要と
される間隔としている。
Here, as shown in FIG. 1B, the length M1 of one side of the die bonding electrode 18 is set to the LED chip 3
The length is longer than the length M2 of one side of 0. However, the length is set so that the LED chip 30 can be reliably bonded onto the die bonding electrode 18 even if the bonding position of the LED chip 30 is slightly displaced. At the same time, it is a margin for preventing the conductive adhesive that adheres the two from flowing down on the substrate 12, and is increased by the minimum margin required. The left and right side surfaces 12a and 12b of the substrate 12 and the side surfaces 12a and 12b
The distances N1 and N2 between the side edges of the die bonding electrode 18 and the wire bonding electrode 20 adjacent to 12b are
This is a margin for allowing a variation in cutting position when the substrate 12 is formed by cutting the substrate base material, and is a minimum required interval.

【0019】図1に示す発光装置10によると、ダイボ
ンディング電極18の上面にLEDチップ30がボンデ
ィングされていて、ダイボンディング電極18および第
1面実装用電極22のそれぞれの面内に第1スルーホー
ル14のそれぞれの表面側開口端部14aおよび裏面側
開口端部14bが位置している。さらに、ダイボンディ
ング電極18と第1面実装用電極22とが、第1スルー
ホール14内に形成された第1接続電極26によって電
気的に接続されている。したがって、ダイボンディング
電極18を基板12上に形成するためのスペースと、ダ
イボンディング電極18と第1面実装用電極22とを電
気的に接続するためのスペースとを共用することができ
る。
According to the light emitting device 10 shown in FIG. 1, the LED chip 30 is bonded to the upper surface of the die bonding electrode 18, and the first through holes are formed in the respective surfaces of the die bonding electrode 18 and the first surface mounting electrode 22. The front surface side open end portion 14a and the back surface side open end portion 14b of each hole 14 are located. Further, the die bonding electrode 18 and the first surface mounting electrode 22 are electrically connected by the first connection electrode 26 formed in the first through hole 14. Therefore, the space for forming the die bonding electrode 18 on the substrate 12 and the space for electrically connecting the die bonding electrode 18 and the first surface mounting electrode 22 can be shared.

【0020】よって、ダイボンディング電極18を形成
するためのスペース以外に、ダイボンディング電極18
と第1面実装用電極22とを電気的に接続するためのス
ペース(図4に示す端部2bに相当するスペースL2)
を別個に確保する必要がなく、その分だけ基板12の面
方向(横幅方向)の寸法を小さくすることができる。さ
らに、基板12の裏面に形成された第1面実装用電極2
2が回路基板38に形成された配線パターン40aに半
田42aを介して電気的に接続されるので、発光装置1
0を実装するためのスペース以外に、図4に示す半田9
bのスペースL4を回路基板38上に確保する必要がな
い。
Therefore, in addition to the space for forming the die bonding electrode 18, the die bonding electrode 18
And a space for electrically connecting the first surface-mounting electrode 22 (a space L2 corresponding to the end portion 2b shown in FIG. 4).
Need not be secured separately, and the dimension of the substrate 12 in the plane direction (widthwise direction) can be reduced accordingly. Further, the first surface mounting electrode 2 formed on the back surface of the substrate 12
2 is electrically connected to the wiring pattern 40a formed on the circuit board 38 via the solder 42a.
0 other than the space for mounting the solder 9 shown in FIG.
It is not necessary to secure the space L4 of b on the circuit board 38.

【0021】そして、ワイヤ32の一端が電気的に接続
されたワイヤボンディング電極20および第2面実装用
電極24のそれぞれの面内に第2スルーホール16のそ
れぞれの表面側開口端部16aおよび裏面側開口端部1
6bが位置している。さらに、ワイヤボンディング電極
20と第2面実装用電極24とが、第2スルーホール1
6内に形成された第2接続電極28によって電気的に接
続されている。これによって、ワイヤボンディング電極
20を基板12上に形成するためのスペースと、ワイヤ
ボンディング電極20と第2面実装用電極24とを電気
的に接続するためのスペースとを共用することができ
る。
Then, in the respective surfaces of the wire bonding electrode 20 and the second surface mounting electrode 24 to which one end of the wire 32 is electrically connected, the front surface side open end portion 16a and the rear surface of the second through hole 16 are formed. Side opening end 1
6b is located. Further, the wire bonding electrode 20 and the second surface mounting electrode 24 are connected to each other by the second through hole 1.
It is electrically connected by the second connection electrode 28 formed in the inside 6. Thereby, the space for forming the wire bonding electrode 20 on the substrate 12 and the space for electrically connecting the wire bonding electrode 20 and the second surface mounting electrode 24 can be shared.

【0022】よって、ワイヤボンディング電極20を形
成するためのスペース以外に、ワイヤボンディング電極
20と第2面実装用電極24とを電気的に接続するため
のスペース(図4に示す端部2aに相当するスペースL
1)を別個に確保する必要がなく、その分だけ基板12
の面方向(横幅方向)の寸法を小さくすることができ
る。そして、この第2面実装用電極24が回路基板38
に形成された配線パターン40bに半田42bを介して
電気的に接続されるので、図4に示す半田9aのスペー
スL3を不用にすることができる。
Therefore, in addition to the space for forming the wire bonding electrode 20, a space for electrically connecting the wire bonding electrode 20 and the second surface mounting electrode 24 (corresponding to the end portion 2a shown in FIG. 4). Space L
It is not necessary to secure 1) separately, and the substrate 12
It is possible to reduce the dimension in the plane direction (width direction). The second surface-mounting electrode 24 is used as the circuit board 38.
Since it is electrically connected to the wiring pattern 40b formed on the substrate via the solder 42b, the space L3 of the solder 9a shown in FIG. 4 can be made unnecessary.

【0023】また、LEDチップ30がボンディングさ
れたダイボンディング電極18の形状を、LEDチップ
30の底面の形状よりも大きくし、かつ底面の形状の相
似形にすることにより、ダイボンディング電極18上に
LEDチップ30をボンディングするときの位置ずれを
許容するための余裕分をダイボンディング電極18の全
周に亘って一定にすることができる。よって、ダイボン
ディング電極18を最低必要とされる余裕分だけ大きく
することができるので、ダイボンディング電極18を比
較的小さくすることができる。
Further, by making the shape of the die bonding electrode 18 to which the LED chip 30 is bonded larger than the shape of the bottom surface of the LED chip 30 and making the shape of the bottom surface similar, the die bonding electrode 18 is formed. It is possible to make the margin for allowing the positional displacement when bonding the LED chip 30 constant over the entire circumference of the die bonding electrode 18. Therefore, the die bonding electrode 18 can be increased by the minimum required margin, so that the die bonding electrode 18 can be made relatively small.

【0024】このように、図4に示す従来の発光装置1
の端部2a,2bに相当するスペースL1,L2だけ基
板12の面方向(横幅方向)の寸法を短くすることがで
きるし、しかも回路基板38上において図4に示す半田
9a,9bのスペースL3,L4を不用とすることがで
きる。したがって、回路基板38に実装される発光装置
10等の実装密度を従来よりも上げることができる。
As described above, the conventional light emitting device 1 shown in FIG.
The space L1 and L2 corresponding to the ends 2a and 2b can reduce the dimension of the board 12 in the plane direction (horizontal width direction), and the space L3 of the solder 9a and 9b shown in FIG. , L4 can be dispensed with. Therefore, the mounting density of the light emitting devices 10 and the like mounted on the circuit board 38 can be increased as compared with the conventional case.

【0025】これにより、回路基板38上に多数の発光
装置10を実装した場合、回路基板38の上面の面積当
たりの各LEDチップ30が発生する光の強さを従来よ
りも大きくすることができるし、基板12の上面の面積
当たりの光の強さを従来よりも大きくすることができ
る。
As a result, when a large number of light emitting devices 10 are mounted on the circuit board 38, the intensity of light generated by each LED chip 30 per area of the upper surface of the circuit board 38 can be made larger than in the conventional case. However, the intensity of light per area of the upper surface of the substrate 12 can be made larger than in the conventional case.

【0026】そして、図1に示すように、LEDチップ
30およびダイボンディング電極18の各中心を互いに
一致させたことにより、LEDチップ30のダイボンデ
ィング電極18に対するボンディングの位置ずれの許容
範囲を大きくすることができる。そして、ダイボンディ
ング電極18,第1面実装用電極22および第1スルー
ホール14のそれぞれの中心を一致させたことにより、
第1スルーホール14に対してダイボンディング電極1
8および第1面実装用電極22を形成するときの位置ず
れによるそれぞれの許容範囲を大きくすることができ
る。同様に、ワイヤボンディング電極20,第2面実装
用電極24および第2スルーホール16のそれぞれの中
心を一致させたことにより、第2スルーホール16に対
してワイヤボンディング電極20および第2面実装用電
極24を形成するときの位置ずれによるそれぞれの許容
範囲を大きくすることができる。
Then, as shown in FIG. 1, the respective centers of the LED chip 30 and the die bonding electrode 18 are made to coincide with each other, whereby the allowable range of the positional deviation of the bonding of the LED chip 30 to the die bonding electrode 18 is increased. be able to. Then, by making the centers of the die bonding electrode 18, the first surface mounting electrode 22 and the first through hole 14 coincide with each other,
The die bonding electrode 1 for the first through hole 14
8 and the first surface mounting electrode 22 can be increased in their respective allowable ranges due to positional deviations. Similarly, by making the centers of the wire bonding electrode 20, the second surface-mounting electrode 24, and the second through-hole 16 coincide with each other, the wire-bonding electrode 20 and the second surface-mounting electrode can be attached to the second through-hole 16. Each allowable range due to the positional deviation when forming the electrode 24 can be increased.

【0027】ただし、上記実施例では、LEDチップ3
0,ダイボンディング電極18,第1面実装用電極22
および第1スルーホール14のそれぞれの中心を一致さ
せたが、それぞれの中心を一致させなくてもよい。ただ
し、この場合でも、第1スルーホール14の表面側開口
端部14aおよび裏面側開口端部14bのそれぞれをダ
イボンディング電極18および第1面実装用電極22の
それぞれの面内に配置する。そして、ワイヤボンディン
グ電極20,第2面実装用電極24および第2スルーホ
ール16のそれぞれの中心を一致させたが、それぞれの
中心を一致させなくてもよい。この場合でも同様に、第
2スルーホール16の表面側開口端部16aおよび裏面
側開口端部16bのそれぞれをワイヤボンディング電極
20および第2面実装用電極24のそれぞれの面内に配
置する。
However, in the above embodiment, the LED chip 3 is used.
0, die bonding electrode 18, first surface mounting electrode 22
Although the centers of the first through holes 14 are made to coincide with each other, the centers may not be made to coincide with each other. However, even in this case, the front surface side opening end portion 14a and the back surface side opening end portion 14b of the first through hole 14 are arranged on the respective surfaces of the die bonding electrode 18 and the first surface mounting electrode 22. Then, although the centers of the wire bonding electrode 20, the second surface-mounting electrode 24, and the second through hole 16 are aligned with each other, the centers may not be aligned with each other. In this case as well, similarly, the front surface side open end portion 16a and the rear surface side open end portion 16b of the second through hole 16 are arranged on the respective surfaces of the wire bonding electrode 20 and the second surface mounting electrode 24.

【0028】そして、上記実施例では、LEDチップ3
0の底面の形状を略正方形としたので、ダイボンディン
グ電極18の形状を略正方形としたが、LEDチップ3
0の底面の形状がたとえば矩形であるときは、ダイボン
ディング電極18をそれよりも少し大きいその形状の相
似形とするとよい。
In the above embodiment, the LED chip 3
Since the bottom surface of 0 has a substantially square shape, the die bonding electrode 18 has a substantially square shape.
When the shape of the bottom surface of 0 is, for example, a rectangle, the die bonding electrode 18 may be similar to that shape, which is slightly larger than that.

【0029】また、上記実施例では、ダイボンディング
電極18の形状をLEDチップ30の底面の形状の相似
形としたが、相似形としなくてもよい。要は、LEDチ
ップ30をダイボンディング電極18上にボンディング
できる大きさと形状であればよい。
Further, in the above embodiment, the shape of the die bonding electrode 18 is similar to the shape of the bottom surface of the LED chip 30, but the shape is not limited to the similar shape. The point is that the LED chip 30 has a size and shape that can be bonded onto the die bonding electrode 18.

【0030】さらに、上記実施例では、LEDチップ3
0を使用する発光装置にこの発明を適用したが、これ以
外のたとえば半導体レーザ等を使用する発光装置にこの
発明を適用することができるし、トランジスタ等の他の
面実装型半導体装置にもこの発明を適用することができ
る。
Further, in the above embodiment, the LED chip 3
Although the present invention is applied to a light emitting device using 0, the present invention can be applied to other light emitting devices using, for example, a semiconductor laser, and other surface mounting type semiconductor devices such as transistors. The invention can be applied.

【0031】そして、上記実施例では、図1に示すよう
に、ダイボンディング電極18,ワイヤボンディング電
極20,ならびに第1および第2面実装用電極22,2
4が、第1および第2スルーホール14,16のそれぞ
れと対応する表面側開口端部14a,16aおよび裏面
側開口端部14b,16bを覆うように形成されている
が、これに代えて、ダイボンディング電極18,ワイヤ
ボンディング電極20,ならびに第1および第2面実装
用電極22,24のそれぞれの中央に貫通孔を形成し、
それぞれの貫通孔がそれぞれと対応する第1および第2
スルーホール14,16の表面側開口端部14a,16
aおよび裏面側開口端部14b,16bと連通するよう
にしてもよい。なお、それぞれの貫通孔の直径は、第1
および第2スルーホール14,16のそれぞれ内面に形
成されている第1および第2接続電極26,28の内径
と同一とする。
In the above embodiment, as shown in FIG. 1, the die bonding electrode 18, the wire bonding electrode 20, and the first and second surface mounting electrodes 22, 2 are formed.
4 is formed so as to cover the front surface side open end portions 14a, 16a and the rear surface side open end portions 14b, 16b corresponding to the first and second through holes 14, 16, respectively, but instead of this, A through hole is formed in the center of each of the die bonding electrode 18, the wire bonding electrode 20, and the first and second surface mounting electrodes 22 and 24,
First and second corresponding through holes respectively
Front side opening end portions 14a, 16 of the through holes 14, 16
It may be made to communicate with a and the back side opening end portions 14b and 16b. The diameter of each through hole is the first
And the inner diameters of the first and second connection electrodes 26 and 28 formed on the inner surfaces of the second through holes 14 and 16, respectively.

【図面の簡単な説明】[Brief description of drawings]

【図1】(A)はこの発明の一実施例に係る発光装置が
配線基板上に実装されている状態を示す縦断面図、
(B)は図1(A)実施例の発光装置を示す平面図であ
る。
FIG. 1A is a vertical cross-sectional view showing a state in which a light emitting device according to an embodiment of the present invention is mounted on a wiring board;
FIG. 1B is a plan view showing the light emitting device of the embodiment of FIG.

【図2】図1(A)実施例の発光装置を示す底面図であ
る。
FIG. 2 is a bottom view showing the light emitting device of the embodiment of FIG.

【図3】従来の発光装置が配線基板上に実装されている
状態を示す斜視図である。
FIG. 3 is a perspective view showing a state in which a conventional light emitting device is mounted on a wiring board.

【図4】従来の発光装置が配線基板上に実装されている
状態を示す縦断面図である。
FIG. 4 is a vertical cross-sectional view showing a state in which a conventional light emitting device is mounted on a wiring board.

【符号の説明】[Explanation of symbols]

10 …発光装置 12 …基板 14 …第1スルーホール 14a,16a …表面側開口端部 14b,16b …裏面側開口端部 16 …第2スルーホール 18 …ダイボンディング電極 20 …ワイヤボンディング電極 22 …第1面実装用電極 24 …第2面実装用電極 26 …第1接続電極 28 …第2接続電極 30 …LEDチップ 32 …ワイヤ 34 …被覆部 38 …回路基板 40a,40b …配線パターン 10 ... Light emitting device 12 ... Substrate 14 ... 1st through hole 14a, 16a ... Front side opening end 14b, 16b ... Back side opening end 16… Second through hole 18 ... Die bonding electrode 20 ... Wire bonding electrode 22 ... First surface mounting electrode 24 ... Second surface mounting electrode 26 ... First connection electrode 28 ... Second connection electrode 30 ... LED chip 32 ... Wire 34 ... Covering part 38 ... Circuit board 40a, 40b ... Wiring pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板、 前記基板の表面に形成されたダイボンディング電極およ
びワイヤボンディング電極、 前記ダイボンディング電極にダイボンディングされた半
導体素子チップ、 前記半導体素子チップと前記ワイヤボンディング電極と
を電気的に接続するワイヤ、 前記基板の裏面に形成された第1および第2面実装用電
極、 前記基板を貫通し、両側のそれぞれの開口端部が前記ダ
イボンディング電極および前記第1面実装用電極のそれ
ぞれの面内に配置された第1スルーホール、 前記基板を貫通し、両側のそれぞれの開口端部が前記ワ
イヤボンディング電極および前記第2面実装用電極のそ
れぞれの面内に配置された第2スルーホール、 前記第1スルーホール内に形成され、前記ダイボンディ
ング電極と前記第1面実装用電極とを電気的に接続する
第1接続電極、ならびに前記第2スルーホール内に形成
され、前記ワイヤボンディング電極と前記第2面実装用
電極とを電気的に接続する第2接続電極を備える、面実
装型半導体装置。
1. A substrate, a die bonding electrode and a wire bonding electrode formed on a surface of the substrate, a semiconductor element chip die-bonded to the die bonding electrode, and the semiconductor element chip and the wire bonding electrode electrically. Wires to be connected, first and second surface mounting electrodes formed on the back surface of the substrate, open ends of the die bonding electrode and the first surface mounting electrode that penetrate the substrate and are on both sides, respectively. A first through hole arranged in the plane of the second through hole, the second through hole penetrating the substrate and having opening ends on both sides arranged in the respective planes of the wire bonding electrode and the second surface mounting electrode. A hole, which is formed in the first through hole and electrically connects the die bonding electrode and the first surface mounting electrode. Surface-mounting semiconductor device including a first connection electrode connected to the wire bonding electrode and a second connection electrode formed in the second through hole and electrically connecting the wire bonding electrode and the second surface-mounting electrode. .
【請求項2】前記半導体素子チップは、上面発光型の発
光素子チップであって、透光性樹脂からなる被覆部によ
って封止された、請求項1記載の面実装型半導体装置。
2. The surface mounting type semiconductor device according to claim 1, wherein the semiconductor element chip is a top emission type light emitting element chip and is sealed by a covering portion made of a translucent resin.
JP2001203272A 2001-07-04 2001-07-04 Surface mount semiconductor device Expired - Lifetime JP4959071B2 (en)

Priority Applications (1)

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JP2001203272A JP4959071B2 (en) 2001-07-04 2001-07-04 Surface mount semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001203272A JP4959071B2 (en) 2001-07-04 2001-07-04 Surface mount semiconductor device

Publications (2)

Publication Number Publication Date
JP2003017754A true JP2003017754A (en) 2003-01-17
JP4959071B2 JP4959071B2 (en) 2012-06-20

Family

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Country Status (1)

Country Link
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EP2128939A3 (en) * 2008-05-29 2012-01-25 Ricoh Company, Ltd. Light emitting apparatus, optical scanning apparatus, and image forming apparatus
KR101769632B1 (en) * 2009-07-08 2017-08-18 오스람 옵토 세미컨덕터스 게엠베하 Electronic component
KR101236086B1 (en) * 2010-09-17 2013-02-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Thermally efficient packaging for a photonic device
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JP2014204027A (en) * 2013-04-08 2014-10-27 日亜化学工業株式会社 Light-emitting device and manufacturing method therefor

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