JP2003086689A - Cad tool for failure analysis of semiconductor and failure analysis method of semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely execute a fault defining process of semiconductor in a short time in a CAD tool for presuming a defect and a failure analysis method using the CAD tool, by collating abnormal reaction information obtained by light emission analysis and OBIRCH analysis and layout data. SOLUTION: Information of plurality of abnormal reactions obtained by physically analyzing a semiconductor device is collected. Overlapping portions of the information are extracted and collated with the layout data on CAD. Wiring and defect portions each having the possibility of fault which are obtained by the collation on the layout data are converged.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a program such as a CAD tool for estimating a defective position which is a factor of a reaction from a reaction site detected by a physical analysis device such as a light emission microscope or an OBIRCH (Optical Beam Induced Resistance Change) analysis device, and The present invention relates to a failure analysis method using this.

[0002]

2. Description of the Related Art In recent years, with the demand for higher speed and more diversified functions of semiconductor devices, miniaturization and higher integration of semiconductor elements and wiring have been advanced, and it is difficult to manufacture this semiconductor device without defects. Is coming. In order to reduce the defects, it is necessary to identify the defective portion in the highly integrated semiconductor device, estimate the failure mechanism of the semiconductor device, and remove the cause. Among them, in order to identify the defective portion, an emission microscope or OBIRC
A method of analyzing a semiconductor device using an H analysis device has been used.

For example, in a light emission microscope, a voltage can be applied to a semiconductor device to detect abnormal light emission from a semiconductor element (transistor), which can be used as a clue for identifying a defective portion. Here, the method of superimposing the coordinates of the light emitting point detected by the light emitting microscope with the layout pattern, which is the design data, and reading the coordinates as the layout pattern coordinates to calculate the coordinates of the abnormal point is used. The analysis time can also be shortened.

[0004]

[Problem 1] In many cases, a light emitting portion is not necessarily a defect generating portion. For example,
When the signal wiring is short-circuited with other wiring, light may be emitted by inputting an abnormal potential to a normal transistor.
As described above, the position of the transistor that emits light is not always defective, and after the analysis by the light emission microscope, a troublesome work of sequentially tracking with an electron beam tester or the like is required. [Problem 2] Light emission may occur at several locations at the same time. Although it is possible to obtain the positional information on the layout pattern from the individual light emitting positions as described above, it is not possible to examine the relationship between them using the current CAD tools. [Problem 3] In a semiconductor device having a fine wiring pattern, it is difficult to clearly decompose the pattern even with a high-power microscope. The emission microscope uses an objective lens with a long working distance because it requires a probe needle for voltage application between the objective lens and the semiconductor device.
Since the numerical aperture is small and the image resolution is low, it is becoming difficult to specify up to one transistor. Similarly, in the OBIRCH analysis device as well, it is becoming difficult to identify a single wiring that has caused an abnormal phenomenon.

An object of the present invention is to accurately identify the location of a defect in such a situation in a short time and in a short time.

[0006]

In order to achieve the above object, the present invention has the following features.

That is, according to the present invention, when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device, a step of receiving reaction information for each pattern acquired by a physical analysis device, The reaction information is collated with the layout pattern information of the semiconductor device, and the wiring path is traced back to the voltage application position direction from the transistor existing in the range of the position indicated by the reaction information. And a step of identifying a wiring range in which the paths of the upstream wirings corresponding to the respective transistors match or are adjacent to each other and displaying the wiring range on the display means. Is a CAD tool.

Further, according to the present invention, when a voltage based on a voltage setting pattern is applied to a semiconductor device, a step of receiving input of reaction information of a plurality of positions acquired by a physical analysis device, and the reaction information of each of the A step of identifying each run-up wire by the arithmetic processing means by matching with the layout pattern information of the semiconductor device, and going up the wire path from the transistor existing within the range of the position of the reaction information in the direction of the voltage application position; , A CAD tool for semiconductor defect analysis, characterized by executing a step of specifying a wiring range in which the path of the upstream wiring corresponding to each transistor matches or is adjacent and displaying it on a display means. .

Further, according to the present invention, when a plurality of transistors exist within the range of the position indicated by the reaction information, the wiring upstream from the transistor located in the range of high emission intensity within the range is subjected to the arithmetic processing. This is a CAD tool for semiconductor defect analysis characterized by performing.

Further, the present invention is a CAD tool for semiconductor defect analysis, characterized in that an emission microscope is used as the physical analysis device.

Further, according to the present invention, when the wiring path is traced back in the direction of the voltage application position, a wiring having a high possibility of failure is referred to by referring to a failure dictionary which models an intermediate potential propagation phenomenon due to a defect in advance. This is a CAD tool for semiconductor defect analysis, which is characterized by selecting and going upstream.

Further, according to the present invention, a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device is obtained as reaction information for each pattern by using an emission microscope, and each reaction information is obtained. Is checked with the layout pattern information of the semiconductor device, and the wiring route is traced back from the transistor existing within the range of the position indicated by the reaction information in the direction of the voltage application position to extract each traced wiring by the arithmetic processing means. Then, the semiconductor defect analysis method is characterized in that a wiring range in which the paths of the upstream wirings corresponding to the respective transistors match or are adjacent to each other is specified and displayed on the display means.

According to the present invention, the reaction state when a voltage based on the voltage setting pattern is applied to the semiconductor device is used to acquire reaction information using an emission microscope. The reaction information is collated with the layout pattern information of the semiconductor device, and the wiring paths are traced back in the voltage application position direction from the transistors existing within the range of the position of the reaction information, whereby each of the traced wirings is processed by the arithmetic processing means. The semiconductor defect analysis method is characterized in that a wiring range in which the path of the upstream wiring corresponding to each transistor is matched or adjacent is specified and displayed on the display means.

Further, in the present invention, when a plurality of transistors are present within the range of the position indicated by the reaction information, the wiring upstream from the transistors located in the range of high emission intensity within the range is subjected to arithmetic processing. This is a semiconductor defect analysis method characterized by being performed.

Further, according to the present invention, when the wiring path is traced back in the direction of the voltage application position, a wiring having a high possibility of failure is referred to by referring to a failure dictionary which models an intermediate potential propagation phenomenon due to a defect in advance. This is a semiconductor defect analysis method characterized by selecting and going upstream.

Further, according to the present invention, when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device, a step of receiving input of reaction information for each pattern acquired by the physical analysis device, and each of the above. Forming a template representative of a reaction shape corresponding to the reaction information; and matching the template with layout pattern information of the semiconductor device to extract a wiring path on the layout by an arithmetic processing means, A CAD tool for semiconductor defect analysis, characterized by executing the step of displaying the wiring route corresponding to a pattern on a display means.

Further, according to the present invention, when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device, a step of receiving the reaction information for each pattern acquired by the physical analysis device, Forming a template representative of a reaction shape corresponding to the reaction information; and matching the template with layout pattern information of the semiconductor device to extract a wiring path on the layout by an arithmetic processing means, A CAD tool for semiconductor defect analysis, characterized in that when the extracted wiring paths corresponding to a pattern are superimposed, a step of displaying a dense distribution based on the degree of wiring density on a display means is executed. .

Further, according to the present invention, when the wiring paths are overlapped with each other, a portion where the wiring paths having the same potential are dense is deleted and a density distribution as a result of arithmetic processing is displayed to display a semiconductor defect analysis. Is a CAD tool for.

Further, the present invention is a CAD tool for semiconductor defect analysis, characterized in that an OBIRCH analysis device is used as the physical analysis device.

Further, according to the present invention, a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device is acquired as reaction information for each pattern by a physical analysis device, and the respective reaction information is obtained. By forming a template representing the corresponding reaction shape and matching the template with the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means, and the wiring path corresponding to each pattern is extracted. Is displayed on the display means.

Further, according to the present invention, a reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device is acquired as reaction information for each pattern by a physical analysis device, and the reaction information is obtained for each of the reaction information. By forming a template representing a corresponding reaction shape and matching the template with the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means, and the extracted corresponding to each pattern is extracted. When the wiring paths are overlapped with each other, a dense distribution based on the degree of wiring density is displayed on the display means.

Further, according to the present invention, when the wiring paths are overlapped with each other, a portion where the wiring paths having the same potential are dense is deleted and the density distribution of the result of the arithmetic processing is displayed to display the semiconductor defect analysis. Is the way.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) A CAD apparatus and a system thereof according to a first embodiment of the present invention will be described with reference to FIG. The CAD device 1 includes a data storage unit 10, a data calculation unit 11, and a program storage unit 12. Through the network 15, the layout data 8, the netlist 9, the schematic (not shown), the additional design information (technology file, not shown), etc. accumulated in the design database 7 are file-transferred to the data storage unit 10.
The desired pre-processing is performed and stored. On the other hand, the light emitting microscope 2 is mounted with the sample 3 for which the failure position is to be identified, and the tester 4 is driven based on the pre-programmed test pattern 5 to apply a desired voltage to the sample 3. The emission microscope image 6 obtained at this time is stored in the data storage unit 10 via the network 15. Therefore, based on the program stored in the program storage unit 12 in advance, the data calculation unit 11 performs the layout data 8,
The failure position specifying operation is performed using the design information such as the netlist 9 and the emission microscope image 6 (detailed procedure will be described later). As an alternative to the network 15, DAT
Data communication may be performed using a recording medium (not shown) or the like.
The input device 13 and the output device connected to the CAD device 1 enable the interface with the user. The user may interlock with the CAD device 1 via the input device 13 to drive and control the light emission microscope 2. Further, the calculation result (coordinates of the failure position, etc.) obtained by the data calculation unit 11 may be stored in a database (not shown).

Next, a specific fault location identifying method will be described. FIG. 1 is a diagram illustrating a failure position identifying method when a plurality of test patterns (a plurality of types of voltage setting patterns) are input. 1A and 1B show overlay images of the layout data 8 and the emission microscope image 6 when the test patterns A and B are input, respectively.
First, when the test pattern A is input in FIG.
A luminescent image 2 of the lit points on the layout pattern 20
2 can be displayed. At this time, the transistor 21 located in the area of the emission image 22 is specified. Here, the transistor 21 itself may be defective, but the transistor 21 is normal and the wiring route leading to the transistor 21 may be the cause of the failure. Therefore, first, the run-up wiring path 23 obtained by going back to the signal input side of the transistor 21 is highlighted on the layout pattern displayed on the output device 14. The connection information described in the netlist 9 may be used for this run-up, or the graphic shape and layout information of the layout data 8 may be used. Further, the data storage unit 10 may store the wiring connection information of the upstream wiring route 23. Next, in FIG. 1B, the same work as in FIG. 1A is performed using the test pattern B. Here, the emission image 24 and the upstream route wiring 25 are obtained. Here, as shown in FIG. 1C, test patterns A and B
In, the emission image and the upstream wiring route are superimposed. It is estimated that the overlapping wiring 26 (the thickest portion shown) of the upstream wiring paths 23 and 25 is most likely to be in failure, and the coordinate position of this overlapping wiring 26 and the wiring net shown in the netlist are shown. Specify the name of. If it is confirmed that the duplicated wiring 26 is defective, the potential state can be confirmed by an electron beam tester or the like.
If no defect is found here, the faulty wiring may be specified by further going up to the test pattern signal input side. Even when there are a plurality of light emitting points in one test pattern, the failure points can be narrowed down by overlapping the run-up paths. In addition, at this time, it is effective to create a software program so that the user can set the number of stages of transistors to be traced back.
Note that the condition to be extracted because the failure probability is high is not limited to the case of overlapping (matching) as described above, and the condition that the wires are adjacent to each other can be realized. This is because there is a high possibility that a short circuit will occur if they are adjacent.

Next, a method for identifying the transistor existing in the light emitting portion based on the light emitting image will be described.
First, a method for assisting the user in identifying the transistor on the screen will be described. FIG. 3 is a diagram showing a method of extracting defective transistors on the screen of the CAD device. After the user confirms the superimposed image of the luminescent image 22 and the layout pattern 20, the user designates the designated area frame 31 by dragging with the cursor 30 using the input device 13 such as a mouse. The transistors 21 existing within the coordinate area of this frame are automatically extracted. The result may be output to the output device 14, or the coordinates and name of the transistor in which the defect is found and the wiring net may be stored in the data storage unit. The transistor can be specified by using the layout data 8, the netlist 9 and the schematic, or can be specified by the software program installed in the CAD device only by the layout data 8.

Further, the light emitting transistor can be automatically specified by a software program installed in the CAD device. FIG. 4 is a diagram showing a method of automatically identifying a transistor from a light emission image. As shown in FIG. 4A, after superimposing the luminescent image 24 on the layout pattern 20, as shown in FIG. 4B, the image of the luminescent part is binarized with an arbitrary threshold value, and this binarization is performed. The luminescent image 40 is shown in FIG.
Clustering is performed in (c). The clustering is for recognizing the binarized light emitting image 40 as a group of light emitting areas, and can be framed as shown in FIG. 4C. Further, as shown in FIG. 4C ', it is also possible to calculate a rectangle surrounding the outermost peripheral pixels of the binarized light emission image 40. If the light emitting region can be defined as data in FIGS. 4C and 4C ′, it is easy to define the transistors existing in the region. The above clustering is effective in the case where abnormal light emission occurs at two locations at the same time.

Further, a method of weighting defective transistors by utilizing the emission intensity will be described. Figure 5
It is a figure which shows the system which extracts a defective transistor based on light emission intensity distribution. The dark part of the luminescent image 22 is the part with high luminescence intensity. The light emission phenomenon generally has an arbitrary intensity distribution like this, and the center thereof is highly likely to be a place where abnormal light is generated. Here, the light emission intensity increases in the order of the transistors 27 and 28. Therefore, from the viewpoint of suspicion of a defect, the priority order to be analyzed is the order of the transistors 27 and 28. For example, if the light emission intensity distribution is expressed by a gray scale of 16 gradations, priority can be set by specifying the transistors existing in the areas having the respective gradations in order from the gradation having the highest brightness. . (Second Embodiment) Next, a second embodiment of the present invention will be described. Here, a failure location identifying method when an OBIRCH analyzer is used instead of the light emission microscope will be described. Regarding the CAD device and its system, the emission microscope of FIG. 2 may be replaced with an OBIRCH analysis device.

FIG. 6 is a diagram showing a method for identifying a wiring having an abnormal reaction from an OBIRCH image. OBIRC
After the user confirms the superimposed image of the H image 50 and the layout pattern 20, the layout wiring overlapping the OBIRCH image is designated by the cursor 30 using the input device 13 such as a mouse. The result is output device 1
4 may be highlighted and output, or the coordinates of the wiring where the abnormality is found and the wiring net name may be stored in the data storage unit. At this time, the wiring net may be specified by using the layout data 8 and the net list 9, or the coordinates may be output by specifying only the layout data 8.

OBI obtained from OBIRCH analyzer
The RCH image has a low resolution as compared with the wiring pitch and appears with a wide width, so that it may not be possible to identify it as one wiring (exemplified by the thick line portion in FIG. 7). A method for solving this will be described below. FIG. 7 to FIG. 10 are diagrams showing a method of extracting a wiring having a suspicion of abnormality from an OBIRCH image. First, the layout pattern 20 and OBI
With the RCH images 50 superposed, as shown in FIG. 7, the first designated area frame 51 is designated by the input device 13 and the cursor 30 so as to surround a part of the OBIRCH image.
Thereby, as shown in FIG. 8, one or a plurality of failure suspect wirings 52 passing through this area can be specified. OBIRCH image 50 when it is possible to specify one wiring net
After confirming that the failure suspect wiring 52 matches, the process ends. Here, when a plurality of wiring nets are output, the second designated area frame 53 is designated as shown in FIG. Here, by searching the wiring net under the condition that the first designated area frame 51 is passed and the second designated area frame 53 is passed,
Further, the failure candidates can be narrowed down. In FIG.
The case where only one faulty wiring 54 can be identified is shown.

Next, a method for automatically narrowing down failure candidates from OBIRCH images will be described. FIG. 11 shows OB
It is a figure which shows the fault wiring narrowing-down method from an IRCH image. First, the OBIRCH image 50 is acquired in FIG. In FIG. 11B, the template 5 that can reproduce the shape of the wiring path by removing the noise component of the OBIRCH image 50 by image processing.
Mold to 5. As shown in FIG. 11C, a wiring path that matches this template is extracted from the layout,
The faulty wiring 56 can be identified.

A method for identifying a location where a defect exists by utilizing the above-described faulty wiring identifying method will be described. FIG. 12 is a diagram showing a method of narrowing down a failure portion when a plurality of test patterns are input. In FIG. 12, four types of test patterns are input in FIGS. 12A to 12D. In each test pattern, the wiring 60 having an OBIRCH reaction was obtained by using the OBIRCH fault wiring identification method as shown in FIGS. 6 to 11.
To 63 specify. In FIG. 12 (e), OBIRCH
It is possible to specify the location of the defect 70 by overlapping the reacted wirings 60 to 63 and specifying the intersecting or dense area 64. At this time, the operator may visually judge the dense area, and it is also effective to emphasize the area in order to support this operation. FIG. 13 is a diagram showing a display method of this density distribution. FIG. 13A shows
It is the figure which overlap | superposed the wiring 60 to 63 which had OBIRCH reaction. As shown in FIG. 13B, if this layout is divided into orthogonal grids and the occupancy of the wirings in which the OBIRCH reaction is matched with respect to each grid area is calculated, the density distribution map 65 is displayed easily. It becomes possible. After that, the coordinates of this dense region or the coordinates of the center of gravity with high density can be automatically calculated, and the subsequent analysis work time can be shortened.

On the other hand, considering the case where a defect causes a short circuit, the accuracy of specifying a defective portion can be supported by the following expression method of the density distribution. FIG. 14 is a diagram showing a method of expressing the density of different wirings. FIG. 14 (a)
In the figure, wirings having an OBIRCH reaction are superposed. Of these, the wirings 66 and 67 that have undergone the OBIRCH reaction are densely packed with the same potential.
Even if it is short-circuited, it may not affect the function unless it is short-circuited to another wiring. Therefore, FIG.
In the method of expressing the density of wirings described in Section 3,
As shown in FIG. 14 (b), a plurality of areas with high density (the portion with the highest hatching) appear, and the defect identification accuracy decreases. Therefore, as shown in FIG. 14C, the true critical region 69 can be specified by identifying the wires and calculating only the density of different wires.

The software program stored in the program storage unit 12 mounted on the CAD device 1 will be described. FIG. 15 is a diagram showing an algorithm. Here, a typical algorithm is described, and the procedures described in the embodiments of the present invention can be incorporated as appropriate. First, the layout data 8, netlist 9, schematic (not shown), additional design information (technology file, etc., not shown), etc. are stored in the data storage unit 1.
0 is subjected to desired preprocessing and stored (step 1).
Next, the tester 4 is driven based on the test pattern 5 to apply a desired voltage to the sample 3 which is a semiconductor device such as a wafer (step 2). In this state, the light emission microscope 2 is driven, and the light emission microscope image 6 obtained at this time is stored in the data storage unit 10 (step 3). Here, the emission microscope image 6 and the layout data 8 are overlaid (step 4). Next, the transistors existing in the light emitting region are specified (step 5). The wiring path on the input side of this transistor is traced back (step 6). At this time, the number of upstream stages of the transistors may be stored in the program in advance, or an operator may be prompted in advance before traveling upstream. When a plurality of test patterns are input, the light emission analysis is continued (step 7) and steps 2 to 6 are repeated. After inputting the test pattern, the overlapping wiring route is specified, stored and output (step 8). (Third Embodiment) In the above embodiment, a light emission microscope,
Although an example is shown in which each OBIRCH analyzer estimates the defective portion, in the actual analysis, it is possible to estimate the defective portion by combining the information of both. One of the methods is a defect candidate narrowed down by the OBIRCH analysis device (for example,
This is a method of narrowing down the defective portion by collating the wiring and the transistor element) with the defective candidate obtained by going up from the light emitting point detected by the light emitting microscope. By doing this,
It is possible to improve the accuracy of defect location identification and further reduce the number of trial and error times of analysis by an electron beam tester for narrowing down the defect location or FIB processing for preparation thereof. (Fourth Embodiment) A description will be given of a method of accurately narrowing down a defective portion in a shorter time when the defective portion is identified by the light emission microscope. In order to describe the present embodiment, first, a light emission phenomenon of a MOS transistor due to application of an intermediate potential will be described with reference to FIG. This phenomenon of intermediate potential generation is one of the causes of a typical light emission phenomenon. The wiring (A) 101 and the wiring (B) 102 connected to the gate of the MOS (A) 103 have a short circuit defect 104.
Consider the case of a short circuit due to. In a certain state, when the wiring (A) 101 and the wiring (B) 102 have different voltages to be originally set, this short circuit influences each other's potential, and becomes an intermediate potential of the set potential of each wiring. This is called intermediate potential. When the wiring (A) 101 has an intermediate potential, the MOS (A) 103 has an incomplete input potential for turning the gate on and off, causing a contact failure. At this stage, a transient abnormal current may flow through the MOS (A) 103 to cause light emission. Further, the contact failure state of the MOS (A) 103 causes an unstable state of the gate potential of the MOS (B) 105 on the output side thereof, so that a transient abnormal current flows in the MOS (B) 105. Thus, light emission can be seen in the MOS (B) 105. The above is the light emission phenomenon due to the intermediate potential.

Next, in the logic circuit, how the light emission phenomenon due to the intermediate potential is propagated will be considered. FIG. 17 shows a NAND which is one of basic logic circuits.
The circuit is taken up and the propagation phenomenon of the intermediate potential is explained. In FIG. 17, the X terminal 11 that is the input of the NAND circuit
In the original state where 0 is a Low potential and Y terminal 111 is a High potential, one of these terminals has an intermediate potential. FIG. 17A shows the X terminal 1
17B shows the case where the Y terminal 111 has the intermediate potential. First, in FIG. 17A, since the intermediate potential is input to the pMOS 112, (1) the output of the pMOS 112 is the intermediate potential or H level.
It becomes a potential state swaying to high / Low. (2) The pMOS 113 has a high Y terminal 111 High
Since it is turned off by the h potential, the output of the pMOS 113 becomes a floating potential. (3) The intermediate potential of the X terminal 110 is nMOS 115,
This causes the operation instability of the nMOS 114 to occur (potential state swaying High / Low).

In the NAND circuit as a whole, these
Since it is determined from the potential states of (1), (2), and (3), the potential state of the output terminal 116 eventually becomes a wandering state.

On the other hand, with respect to FIG. 17B, (4) p is set by the normal input of the low potential of the X terminal 110.
The MOS 112 is turned on, and the output becomes High. (5) pMOS113 by setting the intermediate potential of the Y terminal 111
The behavior of is staggered to ON / OFF, and when it is ON, it is High
When the output is off, the potential is floating. (6) Also, by inputting an intermediate potential to the Y terminal 111, n
The MOS 114 fluctuates, but eventually, due to the OFF state of the nMOS 115 due to the low potential of the X terminal 110,
It becomes a floating potential.

According to the above (4), (5) and (6), pMO
Since the High output of S112 becomes dominant, NAND
The output of the entire circuit becomes High. Due to the above phenomenon,
When the output of the NAND circuit is at an intermediate potential, the original set voltage is Low for the X terminal and High for the Y terminal, and when the defective portion causing the problem is traced back, the case of FIG. It is only necessary to go up to the side of. As described above, in the case of a basic logic circuit, if a fault dictionary (database) of intermediate potential propagation characteristics is created, the fault dictionary is referred to when going up the route (corresponding to step 6 in FIG. 15). As a result, the number of candidates for route suspicion can be halved, and the failure analysis time can be shortened. further,
When the basic logical solution is traced up in multiple stages, it is possible to reduce the failure analysis time to (1/2) ⁿ . This shortening of the failure analysis TAT shortens the product development period and customer return failure. Leads to resource reduction for analysis.

FIG. 18 shows an outline of a failure analysis system that traces the route up by the intermediate potential propagation characteristic. Failure dictionary 120
Include cells such as various basic logic circuits and IP (Intel)
Data describing the intermediate potential propagation characteristics for each of the electrical properties is stored. The fault dictionary 120 is connected to the CAD device 1. This fault dictionary 1
All 20 or necessary data can be loaded into the data storage unit 10 inside the CAD device 1, and the data computation unit 11 can perform computation processing for going up while narrowing down. FIG. 19 is a diagram for explaining the structure of data registered in the failure dictionary 120. The cell name means the name of a basic logic circuit such as NAND or NOR or the name of IP. For the input number (input 1 to input N),
Register the state of potential (HIGH or LOW). Further, a file is created by associating the intermediate potential propagation output number corresponding to the output through which the intermediate potential has propagated with the trace number indicating the input number to be traced. By doing this,
In the circuit of arbitrary cell name, in the case of arbitrary input potential state,
If the intermediate potential output number is given, the most suspicious run-up number can be extracted when going up, so that the failure candidates can be narrowed down and the failure position specifying time can be shortened. This dictionary may define a failure model in advance and associate simulation results of arbitrary circuits in arbitrary potential states, or may be based on actual data obtained from actual product failure analysis results (yes. In the circuit, the intermediate potential output number of the intermediate potential output and the trace-up input number of which the cause is confirmed are stored in association with each other.

[0039]

As described above, according to the present invention, it is possible to narrow down the wiring and the defective portion which are more likely to be defective, so that the accuracy of the defective portion and the time for identifying the defective portion can be shortened.
As a result, it is possible to quickly analyze a defective portion of the semiconductor product, and it is possible to promptly improve the yield by estimating the mechanism.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a failure location identifying method when a plurality of test patterns are input.

FIG. 2 is a diagram showing a CAD device and its system.

FIG. 3 is a diagram showing a method of extracting defective transistors on the screen of a CAD device.

FIG. 4 is a diagram showing a method for automatically identifying a transistor from a light emission image.

FIG. 5 is a diagram showing a method for extracting defective transistors based on a light emission intensity distribution.

FIG. 6 is a diagram showing a method of identifying a wiring having an abnormal reaction from an OBIRCH image.

FIG. 7 is a diagram showing a method of extracting a wiring suspected of being abnormal from an OBIRCH image.

FIG. 8 is a diagram showing a method of extracting a wiring suspected of being abnormal from an OBIRCH image.

FIG. 9 is a diagram showing a method of extracting a wiring having a suspicion of abnormality from an OBIRCH image.

FIG. 10 is a diagram showing a method of extracting a wiring suspected of being abnormal from an OBIRCH image.

FIG. 11 is a diagram showing a fault wiring narrowing method from an OBIRCH image.

FIG. 12 is a diagram showing a method of narrowing down a failure portion when a plurality of test patterns are input.

FIG. 13: Display method of density distribution

FIG. 14 is a diagram showing a method of expressing the density of different wirings.

FIG. 15 is a diagram showing an algorithm.

FIG. 16 is a diagram showing a light emission phenomenon due to application of an intermediate potential.

FIG. 17 is a diagram showing a propagation characteristic of an intermediate potential.

FIG. 18 is a schematic diagram of a fault analysis system in which a route is traced up by an intermediate potential propagation characteristic

FIG. 19 is a diagram for explaining the structure of data registered in the failure dictionary.

[Explanation of reference numerals] 20 ... Layout pattern, 21 ... Transistor, 22
… Luminescent image, 23… Upward wiring route, 24… Luminescent image, 2
5 ... run-up wiring route, 26 ... duplicated wiring

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Claims (16)

[Claims] 1. A step of receiving input of reaction information for each pattern acquired by a physical analysis device when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device; A step of collating with the layout pattern information of the semiconductor device, and tracing back the wiring path from the transistor existing within the range of the position indicated by the reaction information in the direction of the voltage application position to extract the respective traced wirings by the arithmetic processing means. And a step of specifying a wiring range in which the path of the upstream wiring corresponding to each transistor matches or is adjacent and displaying the wiring range on the display means. 2. A step of receiving, when a voltage based on a voltage setting pattern is applied to a semiconductor device, input of reaction information at a plurality of locations acquired by a physical analysis device, and a layout of the semiconductor device for each reaction information. The step of extracting each run-up wire by the arithmetic processing means by matching with the pattern information and running the wire path from the transistor existing within the range of the position of the reaction information in the direction of the voltage application position; A CAD tool for semiconductor defect analysis, which is characterized by executing a step of specifying a wiring range in which the paths of the corresponding upstream wiring match or adjacent to each other and displaying the wiring range on a display means. 3. The CAD tool for semiconductor defect analysis according to claim 1 or 2, wherein when a plurality of transistors are present within the range of the position indicated by the reaction information, the emission intensity within the range. A CAD tool for semiconductor defect analysis, which performs arithmetic processing upstream from the transistors located in the high range of 4. The CAD tool for semiconductor defect analysis according to claim 1, wherein a light emission microscope is used as the physical analysis device. 5. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device is acquired as reaction information for each pattern using an emission microscope, and each reaction information is obtained by the semiconductor device. Of the layout pattern information, and the wiring path is traced back in the direction of the voltage application position from the transistor existing within the range of the position indicated by the reaction information to extract each traced wiring by the arithmetic processing means. The method for analyzing a semiconductor defect is characterized in that a wiring range in which the routes of the upstream wirings corresponding to or adjacent to each other are specified and displayed on the display means. 6. A reaction state obtained when a voltage based on a voltage setting pattern is applied to a semiconductor device is obtained by using a light emission microscope. By collating with the layout pattern information of the semiconductor device and tracing back the wiring path from the transistor existing within the range of the position of the reaction information in the direction of the voltage application position, each traced wiring is extracted by the arithmetic processing means. A semiconductor defect analysis method, characterized in that a wiring range in which the paths of the upstream wirings corresponding to the transistors match or are adjacent to each other is specified and displayed on a display means. 7. The semiconductor failure analysis method according to claim 5, wherein in the case where a plurality of transistors exist within the range of the position indicated by the reaction information, a range of high emission intensity within the range. A semiconductor failure analysis method, characterized in that a wiring upstream operation processing is performed from a transistor located at. 8. A step of receiving reaction information for each of the patterns acquired by a physical analysis device when a voltage based on a plurality of types of voltage setting patterns is applied to the semiconductor device, and corresponding to each of the reaction information. Forming a template representing a reaction shape, and extracting the wiring route on the layout by the arithmetic processing means by matching the template with the layout pattern information of the semiconductor device, and corresponding to each pattern. A CAD tool for semiconductor defect analysis, characterized by executing the step of displaying the wiring path on a display means. 9. A step of receiving reaction information for each pattern obtained by a physical analysis device when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device, and corresponding to each of the reaction information. Forming a template representing a reaction shape, and extracting the wiring route on the layout by the arithmetic processing means by matching the template with the layout pattern information of the semiconductor device, and corresponding to each pattern. A CAD tool for semiconductor defect analysis, which is characterized in that, when the extracted wiring paths are superposed, a step of displaying a dense distribution based on the degree of wiring density on a display means. 10. The CA for semiconductor defect analysis according to claim 9.
A CAD tool for semiconductor defect analysis, characterized by displaying a density distribution of a result of arithmetic processing by deleting a portion where the wiring paths of the same potential are dense when the wiring tools are overlapped. tool. 11. The CAD tool for semiconductor defect analysis according to claim 8 or 9, wherein an OBIRCH analysis device is used as the physical analysis device. 12. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device is acquired as reaction information for each pattern by a physical analysis device, and a reaction shape corresponding to each reaction information is acquired. Forming a template, and by matching the template with the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means, and the wiring path corresponding to each pattern is displayed on the display means. A semiconductor failure analysis method characterized by displaying. 13. A reaction state when a voltage based on a plurality of types of voltage setting patterns is applied to a semiconductor device is acquired as reaction information for each pattern by a physical analysis device, and a reaction shape corresponding to each reaction information is acquired. Forming a template, and by matching the template with the layout pattern information of the semiconductor device, the wiring path on the layout is extracted by the arithmetic processing means, and the extracted wiring path corresponding to each pattern is extracted. A semiconductor failure analysis method characterized by displaying a dense distribution based on the degree of wiring density on a display means when superposed. 14. The semiconductor failure analysis method according to claim 13, wherein, when the wiring paths are overlapped with each other, a density distribution obtained as a result of arithmetic processing by deleting a portion where the wiring paths of the same potential are dense is deleted. A semiconductor defect analysis method characterized by displaying. 15. The CAD tool according to any one of claims 1 to 4, wherein when the wiring path is traced back in the direction of the voltage application position, a fault dictionary that models an intermediate potential propagation phenomenon due to a defect in advance is referred to. A CAD tool for semiconductor defect analysis, which selects wirings with a high possibility of failure and goes up. 16. The semiconductor failure analysis method according to claim 5, further comprising a failure dictionary that models an intermediate potential propagation phenomenon due to a defect when the wiring path is traced back in the voltage application position direction. A semiconductor failure analysis method, characterized in that a wiring having a high possibility of failure is selected and traced back with reference to the wiring.