JP2002531952A - MOS field-effect transistor with auxiliary electrode - Google Patents

Abstract

(57) Abstract: The present invention relates to a MOS field-effect transistor having a low on-resistance R _on , wherein an auxiliary electrode is provided in a drift section between a plurality of semiconductor regions (3) of one conductivity type. (11) is provided, and the auxiliary electrode (11) is made of polycrystalline silicon (12), and the polycrystalline silicon (12) is surrounded by an insulating layer (5).

Description

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a MOS field effect transistor comprising: a semiconductor body of one conductivity type having a first main surface and a second main surface;
At least one first semiconductor zone of another conductivity type diametrically opposite to the first conductivity type is embedded in the semiconductor body on the side of the first main surface, at least one second zone of one conductivity type A second semiconductor zone is provided in the first semiconductor zone; a gate electrode in a region at least above the first semiconductor zone between the second semiconductor zone and the semiconductor body; A MOS field effect transistor having a first electrode connected to the semiconductor body at a second main surface, and having at least a second electrode connected to the second semiconductor zone.

As is well known, the possibility of reducing the on-resistance R _on of power MOS field-effect transistors (FETs) has been studied particularly before. For example, US Pat. No. 5,216,275 describes a power semiconductor device constructed in principle as mentioned at the beginning. In the drift section of this semiconductor device, a so-called “voltage sustaining layer (Voltag
e sustaining layer) ". The voltage sustaining layer consists of vertical p-type and n-type regions arranged side by side, the p-type and n-type regions being arranged alternately with each other, and between the p-type and n-type regions. Is provided with an insulating layer made of silicon dioxide. FIG. 4 shows a MOSFET as an example of such a normal semiconductor device.

This known MOSFET has an n ⁺ -type drain contact zone 2, alternating n-type semiconductor zones and p-type semiconductor zones 3 or 4, a p-type semiconductor zone (“
It comprises a semiconductor body 1 having a "body" zone 6 and an n-type semiconductor zone 7 embedded in this zone 6. The n-type semiconductor zone and the p-type semiconductor zone 3 or 4 are separated from one another by an insulating layer 5 made of, for example, silicon dioxide.

The semiconductor body 1 is usually made of silicon, although other materials can be used in some cases. In some cases, the above conduction types can be reversed.

A gate electrode 9 made of doped polycrystalline silicon is embedded in an insulating layer 8 made of, for example, silicon dioxide or silicon nitride, and a connection terminal G is provided. A metal layer 10, for example made of aluminum, is connected to the n-type zone 7 and provided with a grounded source terminal S. Drain voltage + U _D is applied to the n ⁺ -type semiconductor layer 2 in which the drain terminal D is provided.

[0006] Voltage + U _D is applied, the zone 3 and 4 are depleted by another charge carriers. These zones 3, which extend in a columnar manner between the two main surfaces of the semiconductor body 1,
4, the total amount of n-doping and p-doping is substantially the same, or
If the total amount of n-doping and p-doping in these zones 3, 4 is so small that these zones 3, 4 are completely depleted by charge carriers before breakdown occurs, such MOSFETs will have a high voltage. , And nonetheless has a low on-resistance R _on . In this case, n-type zone 3 and p
If these zones are not completely depleted by charge carriers due to the insulating layer 5 between them and the p-type zone 4 provided below the zone 6,
Used as grounded field plate for shape zone 3.

A MOSFET having the structure shown in FIG. 4 is relatively expensive in its manufacture, which is due in particular to the insulating layer 5 in the n-type semiconductor body 1 and the p surrounding the insulating layer 5. Due to shape zone 4.

Accordingly, an object of the present invention is to provide a MOSFET which has a low on-resistance like the existing MOSFET but can be manufactured much more easily.

According to the invention, the semiconductor body is provided with at least one auxiliary electrode having an insulating layer, wherein the auxiliary electrode is provided on a first of the semiconductor body. The problem is solved by extending in a direction between the main surface and the second main surface and being electrically connected to the first semiconductor zone.
Advantageously, the auxiliary electrode is provided directly below the first semiconductor zone.

In this case, it is also possible to provide a plurality of such auxiliary electrodes below each first semiconductor zone. These auxiliary electrodes are in some cases "pencil-shaped". The auxiliary electrode may extend as far as the heavily doped layer of one conductivity type in the region of the second main surface, i.e. close to the drain contact zone. However, the auxiliary electrode only reaches a lightly doped layer of one conductivity type,
It is also possible for this lightly doped layer to be provided between the semiconductor body and a highly doped semiconductor layer of one conductivity type connected to the first electrode.

The auxiliary electrode itself preferably consists of highly doped polycrystalline silicon, while silicon dioxide is preferably used for the insulating layer.

The depth of the auxiliary electrode is for example between 5 μm and 40 μm, while the width of this auxiliary electrode is on the order of approximately 1-5 μm. The thickness of the insulating layer on the polycrystalline silicon of the auxiliary electrode is between 0.1 μm and 1 μm. The thickness of this insulating layer increases towards the second main surface or up to the center of the auxiliary electrode between the two main surfaces.

The MOSFET according to the invention can be manufactured in a particularly simple manner. That is, for example, a trench is provided in the n-type semiconductor body, for example, by etching. An insulating layer is provided on the wall and bottom of these trenches. This is done by oxidation. As a result, a silicon dioxide layer is formed as an insulating layer in the semiconductor body made of silicon. The trenches are then filled with n ⁺ or p ⁺ polycrystalline silicon. This does not cause any problems.

In this case, ^{p.sup. +} Doping is advantageous for the polysilicon of the auxiliary electrode: that is, if there is a hole in the insulating layer, after the p-type diffusion, this hole causes the n-type semiconductor body. A pn junction occurs at On the other hand, in the case of n ⁺ doping of the polysilicon of the auxiliary electrode, such a hole causes a short circuit to the n-type semiconductor body.

The auxiliary electrode itself can have a columnar, grid-like or strip-like or other shape.

The n-type semiconductor zone is also heavily doped first as the auxiliary electrodes are arranged closer to each other. However, in this case, the following is considered.
That is, if the auxiliary electrodes extend parallel to one another, the surface charge on the sides of the n-type semiconductor zone must not exceed the amount of doping material corresponding to twice the breakdown charge.

The n ⁺ or p ⁺ doping of the polysilicon of the auxiliary electrode does not need to be uniform. Rather, in this case, fluctuations in the doping concentration are allowed. Also, the depth of the auxiliary electrode or the depth of the trench is not important: they may reach the heavily doped drain contact zone, but this need not be the case.

For example, instead of an n-type semiconductor body, it is also possible to provide a layer with different doping for this semiconductor body.

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a MOSFET according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a MOSFET according to a third embodiment of the present invention.

FIG. 4 is a sectional view of an existing MOSFET.

FIG. 4 has already been described at the outset. 1 to 3 use the same reference numerals as in FIG. 4 for corresponding parts. Also, as in FIG. 4, the conduction types described may be diametrically opposite.

FIG. 1 shows an embodiment of a MOSFET according to the present invention. Unlike the conventional MOSFET of FIG. 4, a p-type zone 4 surrounded by an insulating layer 5 is not provided here. Rather, the MOSFET of the embodiment of FIG. 1 is provided with auxiliary electrodes 11, each composed of n ⁺ -doped or p ⁺ -doped polycrystalline silicon 12 and surrounded by an insulating layer 5. Have been. Instead of polycrystalline silicon, it is also possible, if appropriate, to use other electrically conductive materials. The insulating layer 5 can also be composed of a material other than silicon dioxide, for example silicon nitride, or of various insulating films, for example silicon dioxide or silicon nitride.

These auxiliary electrodes have a similar effect to the p-type zone 4 in the conventional MOSFET of FIG. That is, when the drain voltage + U _D is applied to the drain terminal D, n-type Thorn 3 is depleted by charge carriers. In this case, a larger electric field intensity is generated in the insulating layer 5 than in the case of the MOSFET having the conventional structure of FIG. However, this has no effect on the depletion performed by the charge carriers.

An important advantage of the present invention is that the MOSFET of FIG. 1 is much easier to manufacture than the MOSFET of FIG. That is, the width is about 1-5 μm and the depth is about 5-
Only a 40 .mu.m trench 13 has to be etched into the semiconductor body 1 down to approximately the layer 2, and the walls of the trench 13 are then covered by oxidation with an insulating layer 5 of silicon dioxide having a layer thickness of 0.1 to 1 .mu.m. . In this case, the thickness of the insulating layer 5 is not particularly important. Rather, this thickness may increase from top to bottom or to the center in trench 13.

Subsequently, these trenches are filled with p ⁺ doped or n ⁺ doped polycrystalline silicon 12. However, p ⁺ doping for the auxiliary electrode 11 should preferably be chosen. This is because, taking into account possible holes in the insulating layer 5, this p ⁺ doping results in a higher yield, as already explained.

The arrangement of the auxiliary electrodes 11 does not need to match the arrangement of the individual semiconductor cells. Rather, the auxiliary electrodes 11 are provided in a columnar, grid-like or strip-like or other form.

The n-type zone 3 is advantageously more heavily doped, the closer the auxiliary electrodes 11 are to one another. The only important thing is that if the auxiliary electrodes 11 extend parallel to one another, the surface charge on the sides of the n-type zone 3 will not exceed twice the amount of doping material corresponding to the breakdown charge.

Instead of the n-type zone 3 (or the semiconductor body 1), it is also possible to provide a plurality of layers with different doping. Further, n ⁺ form Zone 2 may also be replaced by n-p ⁺ stratigraphic or n ⁺ -p ⁺ stratigraphic, which is indicated by the dashed line 15 in FIG. 1. In this case, it becomes an IGBT (IGBT = bipolar transistor having an insulated gate).

Finally, the doping of the polycrystalline silicon 12 of the auxiliary electrode 11 does not need to be uniform.

FIG. 2 shows another embodiment of the present invention. In this embodiment, unlike the embodiment of FIG. 1, two auxiliary electrodes 11 are assigned to each cell. Of course, in some cases, three or more auxiliary electrodes 11 can be provided for each cell.

Finally, it is not necessary for the auxiliary electrode 11 to reach the heavily doped n ^{+ -type} layer 2 on the side of the drain terminal D. Similarly, it is possible that these auxiliary electrodes 11 terminate in an n ⁻ -type layer 14 provided between the n ^{+ -type} layer 2 and the n-type zone 3.

The invention enables a MOSFET which can be manufactured in such a simple manner. This MOSFET only requires the usual steps in semiconductor technology in the formation of a trench and nevertheless guarantees a low on-resistance R _on .

In the above embodiment, the vertical structure of the MOS field effect transistor of the present invention has been described. Naturally, the invention is also applicable to lateral structures, in which the auxiliary electrodes 11 extend laterally in the semiconductor body.

[Brief description of the drawings]

FIG. 1 is a sectional view of a MOSFET according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a MOSFET according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a MOSFET according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view of an existing MOSFET.

[Explanation of symbols]

Reference Signs List 1 semiconductor body 2 n ^{+ type} drain contact zone 3 n type semiconductor zone 4 p type semiconductor zone 5 insulating layer 6 p type semiconductor zone (“body” zone) 9 gate electrode G connection terminal 10 metal layer S source terminal D drain terminal + U _D drain voltage 11 auxiliary electrode 12 of polycrystalline silicon 13 trenches 15 dashed 14 n ^- type layer

Claims (14)

[Claims] 1. A MOS field effect transistor comprising a semiconductor body (1) of one conductivity type having a first main surface and a second main surface, wherein said first semiconductor body (1) has a first main surface and a second main surface. At least one first semiconductor zone (6) of another conductivity type diametrically opposite to the first conductivity type is embedded on the side of the main surface of the at least one second conductivity type. Zone (7), said second semiconductor zone (7) being provided in said first semiconductor zone (6), said second semiconductor zone (7) and said semiconductor body (1) A first electrode (D) having a gate electrode (9) at least in a region above the first semiconductor zone (6) and connecting to the semiconductor body (1) at the second main surface.
) And having at least a second electrode (10; S) connected to the second semiconductor zone (7), wherein the semiconductor body (1) has an insulating layer ( At least one auxiliary electrode (11) having 5) is provided, the auxiliary electrode (11) being oriented in a direction between the first main surface and the second main surface of the semiconductor body (1). A MOS field effect transistor extending and electrically connected to said first semiconductor zone (6). 2. The MOS field-effect transistor according to claim 1, wherein one or more auxiliary electrodes are provided immediately below each first semiconductor zone. 3. The MOS field effect transistor according to claim 1, wherein the auxiliary electrode is formed in a pencil shape. 4. The semiconductor device according to claim 1, wherein the auxiliary electrode extends to a highly doped layer of one conductivity type in the region of the second main surface.
2. The MOS field effect transistor according to claim 1. 5. The auxiliary electrode (11) is a lightly doped layer of one conductivity type.
14), said layer (14) comprising a semiconductor body (1) and a heavily doped semiconductor layer (2) of one conductivity type connected to a first electrode (D). 4. The MOS according to claim 1, wherein the MOS is provided between the MOS transistors.
Field effect transistor. 6. The auxiliary electrode comprises highly doped polycrystalline silicon (12), the polycrystalline silicon (12) being surrounded by an insulating layer (5) composed of silicon dioxide. The MO according to any one of claims 1 to 5,
S field effect transistor. 7. The MOS field effect transistor according to claim 1, wherein the auxiliary electrode has a depth of 5 to 40 μm. 8. The MOS field effect transistor according to claim 1, wherein the width of the auxiliary electrode is approximately 1 to 5 μm. 9. The MOS field effect transistor according to claim 1, wherein the thickness of the insulating layer is between 0.1 μm and 1 μm. 10. The MOS field-effect transistor according to claim 1, wherein the thickness of the insulating layer increases in the direction of the second main surface. 11. A MOS field-effect transistor according to claim 1, wherein the thickness of the insulating layer increases up to the center of the auxiliary electrode. . 12. The auxiliary electrode (11) is manufactured by etching a trench (13) and filling said trench (13) with an insulating layer (5) and polycrystalline silicon (12). The MOS field effect transistor according to claim 1, wherein: 13. The MOS field-effect transistor according to claim 6, wherein the polycrystalline silicon is not uniformly doped. 14. In the semiconductor body (1) in the region of the second main surface, a highly doped layer (2) of one conductivity type or a layer of said one conductivity type and another conductivity type Or a stratigraphy comprising a heavily doped layer of said one conductivity type and a heavily doped layer of said another conductivity type. 14. The MOS field effect transistor according to claim 1, wherein: