JP2002217721A - Pll control method and pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(Phase Locked Loop) control method and a PLL circuit which can solve a problem of an unstable output of a voltage controlled oscillator when the frequency of an input signal is not within a variable range of the voltage controlled oscillator or when the input signal is absent and which can give a stable output even when the input signal includes sudden fluctuations. SOLUTION: The PLL control method and PLL circuit can discriminate whether the frequency of the input signal resides within a variable range of a voltage controlled oscillator, and when the frequency of the input signal is within the variable range, supply a result of multiplication between the input signal and the output of the voltage controlled oscillator to the voltage controlled oscillator as its control voltage to conduct PLL operations, and when the frequency of the input signal is at the outside of the variable range, supply a fixed voltage to the voltage controlled oscillator as its control voltage to product PLL operations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lo
More particularly, the present invention relates to a PLL control method and a PLL circuit that can output a stable clock even if there is a sudden change in an input signal.

[0002]

2. Description of the Related Art A conventional PLL circuit will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of a conventional PLL circuit. As shown in FIG. 4, a conventional PLL circuit includes a voltage controlled oscillator (in the figure, a voltage controlled oscillator).
A low pass filter (low pass filter: LPF) 3 in the figure. The voltage controlled oscillator 1 is a general oscillator whose oscillation frequency can be varied by an input voltage (control voltage).
The multiplier 2 is a general multiplier that multiplies two input signals and outputs the result. The low-pass filter 3 is a general low-pass filter that removes high-frequency components and outputs only low-frequency components.

The operation of a conventional PLL circuit is such that an input signal a and an output signal b of a voltage controlled oscillator (VCO) 1 are
And the multiplication result c is a low-pass filter (LPF)
3, a signal d from which high-frequency components have been removed is output,
The signal d becomes the control voltage of the voltage controlled oscillator VCO1,
The output frequency of the voltage controlled oscillator 1 is controlled.

In the conventional PLL circuit shown in FIG.
When the frequency of the input signal is within the variable range of the voltage-controlled oscillator 1, the PLL loop converges and the oscillation frequency of the voltage-controlled oscillator 1 gradually approaches the frequency of the input signal, and as shown in FIG. a becomes equal to the frequency (period) of the output signal b of the voltage controlled oscillator 1, and the input voltage d to the voltage controlled oscillator 1 becomes a constant value as shown in FIG. On the other hand, when the frequency of the input signal is not in the variable range of the voltage controlled oscillator 1, the PLL loop diverges without converging,
The frequency (period) of the input signal a and the output signal b of the voltage-controlled oscillator 1 are not equal, and the input voltage d to the voltage-controlled oscillator 1 is not constant and unstable as shown in FIG. It is. FIG. 5 is an explanatory diagram showing an operation at the time of PLL convergence in a conventional PLL circuit, and FIG.
FIG. 4 is an explanatory diagram showing an operation of the circuit when PLL has not converged.

The prior art of the PLL control method and the PLL circuit is disclosed in Japanese Unexamined Patent Application Publication No.
No. 190449 “DPPLL circuit” (applicant: Toyo Tsushinki Co., Ltd., inventor: Takanori Ohno). In this conventional technique, the relationship between the control voltage of the VCO and the oscillation frequency is stored in a memory, and when the reference signal is interrupted, the VCO control voltage output at that time is held and when the reference signal is supplied again. A DPPLL circuit that detects a frequency difference between a VCO output frequency and a reference signal due to the held control voltage and determines a control voltage to be applied to the VCO based on the frequency difference and information stored in a memory. When the reference signal is supplied again after the output frequency largely fluctuates due to the interruption of the signal, the output frequency can be quickly recovered from the fluctuated output frequency within a specified frequency range.

As another prior art of a PLL control method and a PLL circuit, Japanese Patent Application Laid-Open No. H11-274922, “Phase Synchronous Circuit” published on Oct. 8, 1999 (applicant: Fuji Denso Co., Ltd., inventor) : Keisuke Kanayama). This prior art determines whether the input signal frequency is higher or lower than the center frequency at the time of synchronization pull-in, selects the control voltage of the lower limit frequency if higher, selects the control voltage of the upper limit frequency if lower, This is a phase-locked loop that is input to the voltage-controlled oscillator instead of the control voltage via the loop filter, and determines the difference between the input signal frequency and the frequency-divided output signal frequency at the start of synchronization pull-in when power is turned on or when the input signal is restored. By increasing the value, the speed of synchronization pull-in can be increased.

[0007]

However, in the above-mentioned conventional PLL control method and PLL circuit, the PLL loop diverges when the frequency of the input signal is not within the variable range of the voltage controlled oscillator 1 or when there is no input signal. As a result, there has been a problem that the output from the voltage controlled oscillator 1 is not stable.

The present invention has been made in view of the above circumstances, and has a problem that the output of a voltage controlled oscillator is not stable when the frequency of the input signal is not within a variable range of the voltage controlled oscillator or when there is no input signal. And an object of the present invention is to provide a PLL control method and a PLL circuit that can obtain a stable output even when a sudden change occurs in an input signal.

[0009]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art changes the control voltage of the voltage controlled oscillator based on the result of multiplication of the input signal and the output signal of the voltage controlled oscillator. A PLL control method for changing an output frequency of a voltage-controlled oscillator, wherein it is determined whether or not the frequency of an input signal is within a variable range of the voltage-controlled oscillator. Since the result of the multiplication with the control oscillator output is supplied to the voltage controlled oscillator as a control voltage to perform the PLL operation, and when the voltage is outside the variable range, the fixed voltage is supplied to the voltage controlled oscillator as the control voltage to perform the PLL operation. Thus, a stable output can be obtained even if there is a sudden change in the input signal.

The present invention for solving the above-mentioned problems of the prior art comprises a multiplier for multiplying an input signal and an output signal of a voltage controlled oscillator, and a voltage controlled oscillator whose oscillation frequency changes using the output of the multiplier as a control voltage. A switch for switching a control voltage supplied to a voltage-controlled oscillator to the multiplier output or a fixed voltage in accordance with a switching instruction, a switch for receiving an input signal, and a frequency of the input signal. It is determined whether or not is within the variable range of the voltage-controlled oscillator, if it is within the variable range, a switch is output to output a switching instruction to make the control voltage supplied to the voltage-controlled oscillator a multiplier output, A frequency determination circuit that outputs a switching instruction so that the control voltage supplied to the voltage-controlled oscillator is set to a fixed voltage when the switch is outside the variable range. There is a sudden change in the input signal can also obtain a stable output.

[0011]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

A PLL control method and a PLL circuit according to the present invention determine whether or not the frequency of an input signal is within a variable range of a voltage-controlled oscillator. The result of the multiplication with the output is supplied as a control voltage to the voltage controlled oscillator to perform the PLL operation. If the output voltage is out of the variable range, the fixed voltage is supplied to the voltage controlled oscillator as the control voltage to perform the PLL operation. Even if there is a sudden change in the signal, a stable output can be obtained.

First, the configuration of a PLL circuit according to the present invention will be described with reference to FIG. FIG. 1 shows a PL according to the present invention.
FIG. 3 is a configuration block diagram of an L circuit. Parts having the same configuration as in FIG. 4 are described with the same reference numerals. The PLL circuit of the present invention (this circuit) includes a voltage-controlled oscillator (VCO in the figure) 1 as a portion similar to a conventional PLL circuit.
, A multiplier 2 and a low-pass filter (LPF in the figure) 3
The switch 4 and the frequency determination circuit 10 are further provided as characteristic parts of the present invention.

Next, each part of the circuit will be described in detail. The voltage controlled oscillator 1, the multiplier 2, and the low-pass filter 3 are completely the same as those in the prior art, so that the description is omitted, and the features of the present invention are omitted. Will be described. The switch 4 is a switch that switches the control voltage supplied to the voltage controlled oscillator 1 with the output (A) of the low-pass filter 3 or the fixed voltage (B), and is switched according to an output from a frequency determination circuit 10 described later.

The frequency determination circuit 10 determines whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator 1, and outputs a switching signal g of the switch 4 according to the determination result. Specifically, the frequency determination circuit 10 determines whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator 1. If the frequency is determined to be within the variable range, the switch 4 outputs the low-pass filter 3 output. A signal for switching the switch 4 to the fixed voltage side (B) is output when a signal for switching the switch 4 to the fixed voltage side (B) is output.

Here, the internal configuration of the frequency determination circuit 10 of the PLL circuit of the present invention will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration example of the frequency determination circuit 10 of the PLL circuit according to the present invention. The frequency determination circuit 10 of the PLL circuit according to the present invention includes a frequency divider 11, a frequency determination clock generator 12, a counter 13, and a frequency calculator 14. The frequency divider 11 is a general frequency divider that divides an input signal. The frequency determining clock generator 12 is a clock generator that generates a frequency counting clock for determining the length of one cycle of a signal obtained by dividing the input clock.

The counter 13 is a counter for counting the length of one cycle of a signal obtained by dividing the input clock. Specifically, the counter 13 includes the frequency determination clock generator 1.
The counter is incremented according to the clock from 2 and the count value (count number) f while the counter is cleared at the falling edge of the signal from the frequency divider 11, for example.
Is output.

The frequency calculation unit 14 regards the maximum value of the count number f output from the counter 13 as the length of one cycle of a signal obtained by dividing the input clock, and adjusts the frequency of the input signal to the variable range of the voltage controlled oscillator 1. Is determined, and a switching signal g of the switch 4 is output according to the determination result. It should be noted that the switching signal g is regarded as a normal state when the frequency of the input signal is within the variable range of the voltage controlled oscillator 1 and as an abnormal state when the frequency is outside the variable range or when the input signal is not input. It can also be used as an input signal alarm that detects and reports an abnormal state of the input signal.

A method for determining a frequency in the frequency calculation unit 14 will be described with reference to FIG. FIG. 3 is an explanatory diagram illustrating a method of determining a frequency in the frequency calculator 14. Assume that the signal e from the frequency divider 11 input to the frequency calculator 14 is a clock as shown in FIG. 3A, and that the counter 13 is cleared at the falling edge of the signal from the frequency divider 11. At time t0, the signal e from the frequency divider 11 falls, the counter 13 is cleared, and thereafter, the count is incremented by the clock from the clock generator 12 for frequency determination. Then, the next falling time t1
Up to this point, the counter value is incremented until the frequency calculation unit 14 determines that the maximum value of the count value from the counter 13 is the counter value (Cmax) at the frequency upper limit corresponding to the variable range of the voltage controlled oscillator 1 and the frequency lower limit. If the time is within the range of the counter value (Cmin), a switching signal g for setting the switch 4 to input the output from the low-pass filter 3 to the voltage-controlled oscillator 1 is output. Further, the maximum value of the count value from the counter 13 is equal to the counter value (C
max) and the counter value (Cmin) at the lower frequency limit, the switch 4 is set to a fixed voltage by the voltage-controlled oscillator 1
And outputs a switching signal g that is set so as to be input to.

Next, the operation of the PLL circuit according to the present embodiment will be described with reference to FIGS. 1, 2 and 3. In the PLL circuit of the present invention, the input signal a and the voltage controlled oscillator (VC
O) The output signal b of 1 is multiplied by the multiplier 2, and the multiplication result c is output as a signal d from which high-frequency components have been removed by a low-pass filter (LPF) 3. On the other hand, the input signal d
Is input to the frequency determination circuit 10 and it is determined whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator 1. If the frequency is determined to be within the variable range, the switch 4 is switched to the low-pass filter. A switching signal g for switching to the 3 output side (A) is output, and the switch 4
On the output side (A), the output signal d from the low-pass filter 3 is supplied to the voltage controlled oscillator 1 as a control voltage d '. When it is determined that the frequency of the input signal is outside the variable range of the voltage controlled oscillator 1, a switching signal g for switching the switch 4 to the fixed voltage side (B) is output, and the switch 4 is switched to the fixed voltage side (B). ), The fixed voltage is supplied to the voltage controlled oscillator 1 as the control voltage d '.

According to the PLL control method of the embodiment of the present invention, it is determined whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator. The result of multiplication of the signal and the output of the voltage-controlled oscillator is supplied to the voltage-controlled oscillator as a control voltage to perform a PLL operation. Therefore, even if the input clock signal becomes abnormal or suddenly becomes non-input, the output frequency is kept constant by preventing the divergence of the PLL loop, and a stable PLL operation can be performed. This has the effect of maintaining the clock output.

Further, according to the PLL circuit of the embodiment of the present invention, the frequency judgment circuit 10 judges whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator. Switches the switch 4 so that the result of multiplication of the input signal and the output of the voltage controlled oscillator is supplied to the voltage controlled oscillator as a control voltage as in the conventional case. Since the PLL operation is performed by switching the switch 4 so that the input clock signal is supplied, even if the input clock signal becomes abnormal or suddenly becomes uninput, the output frequency is kept constant by preventing the divergence of the PLL loop. Thus, there is an effect that a stable PLL operation can be performed and a stable clock output can be maintained.

[0023]

According to the present invention, it is determined whether or not the frequency of the input signal is within the variable range of the voltage controlled oscillator. If the frequency is within the variable range, the multiplication of the input signal and the output of the voltage controlled oscillator is performed. The result is supplied to a voltage controlled oscillator as a control voltage, and P
When the LL operation is performed and the voltage is outside the variable range, the PLL is controlled by supplying the fixed voltage as a control voltage to the voltage controlled oscillator to perform the PLL operation. There is an effect that a desired output can be obtained.

According to the present invention, there is provided a switch for switching the control voltage supplied to the voltage controlled oscillator to a multiplier output or a fixed voltage in accordance with a switching instruction,
It takes in the input signal, determines whether the frequency of the input signal is within the variable range of the voltage controlled oscillator, and if it is within the variable range, switches the switch to the control voltage supplied to the voltage controlled oscillator with the output of the multiplier. And a frequency determination circuit that outputs a switching instruction so that the control voltage supplied to the voltage-controlled oscillator is a fixed voltage when the switch is outside the variable range. There is an effect that a stable output can be obtained even if there is a sudden change in the input signal.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a PLL circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a frequency determination circuit of a PLL circuit according to the present invention.

FIG. 3 is an explanatory diagram illustrating a method of determining a frequency in a frequency calculation unit.

FIG. 4 is a block diagram illustrating a configuration of a conventional PLL circuit.

FIG. 5 is an explanatory diagram showing an operation at the time of PLL convergence in a conventional PLL circuit.

FIG. 6 is an explanatory diagram showing an operation of a conventional PLL circuit when PLL has not converged.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Voltage controlled oscillator, 2 ... Multiplier, 3 ... Low pass filter, 4 ... Switch, 10 ... Frequency judgment circuit,
11: frequency divider, 12: clock generator for frequency judgment,
13: counter, 14: frequency calculator

Claims (2)

[Claims] 1. A PLL control method for changing a control voltage of the voltage-controlled oscillator based on a result of multiplication of an input signal and an output signal of the voltage-controlled oscillator, thereby changing an output frequency of the voltage-controlled oscillator. It is determined whether or not the frequency of the input signal is within the variable range of the voltage-controlled oscillator.If the frequency is within the variable range, the result of multiplication of the input signal and the output of the voltage-controlled oscillator is used as the control voltage as the voltage-controlled oscillator. And performing a PLL operation by supplying the fixed voltage as a control voltage to the voltage controlled oscillator when the voltage is outside the variable range. 2. A PLL having a multiplier for multiplying an input signal and an output signal of a voltage controlled oscillator, and a voltage controlled oscillator whose oscillation frequency changes using the multiplier output as a control voltage.
A circuit for switching whether the control voltage supplied to the voltage-controlled oscillator is the multiplier output or the fixed voltage according to a switching instruction; and taking in an input signal, wherein the frequency of the input signal is It is determined whether or not it is within the variable range of the voltage controlled oscillator, and if it is within the variable range, a switch instruction is output so that the switch sets the control voltage supplied to the voltage controlled oscillator to the multiplier output. And a frequency determination circuit that outputs a switching instruction so that the control voltage supplied to the voltage controlled oscillator is set to a fixed voltage when the switch is outside the variable range.