JP2002217198A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, an interlayer film for which is made of organic polymer material, porous inorganic material, or porous organic polymer material, of a small relative dielectric constant, where the moisture resistance of elements themselves of the semiconductor device is improved more reliable. SOLUTION: When interlayer insulation films 213, 216 are made of organic polymer material, porous inorganic material, or porous organic polymer material, the lower part of a partition (guard ring) 227 is formed in an inner part 206 of a semiconductor substrate so as to surround an element, where the partition (guard ring) 227 is made of material from which a wiring layer is formed so as to surround the periphery of the element in order to prevent moisture from coming into and getting through from the periphery of the element. Otherwise, a passivation film 225 formed on the top surface on the element is formed up to the outer periphery of an end of the element, so as to coat the element, or the passivation film 225 is formed at the outer periphery of an end of the element so as to embed the element in the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a structure suitable for improving moisture resistance reliability of a semiconductor device using an organic insulating film or a porous inorganic film which is a low dielectric constant material having a relative dielectric constant of 3.0 or less as an interlayer insulating film.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices and the reduction in chip size, finer wirings, narrower pitches, and multilayers have been promoted. On the other hand, as the design rule becomes finer, the ratio of the wiring delay to the signal delay of the entire device increases.

The signal speed is determined by the product (RC) of the wiring resistance (R) and the capacitance between wirings (C), and it is possible to reduce RC by lowering the wiring resistance R or reducing the capacitance C between wirings. This is a technique necessary to reduce wiring delay.

[0004] For this reason, a reduction in the dielectric constant of the interlayer insulating film for suppressing the capacitance C between wirings is indispensable in accordance with demands for lower power consumption and higher speed of the semiconductor device.

Therefore, as an interlayer insulating film of a semiconductor device,
Instead of the silicon oxide film formed by the conventional CVD method (chemical vapor deposition method), a material having a lower dielectric constant is required, and an interlayer insulating film material having a relative dielectric constant of 3.0 or less is actively used. Are being considered. Examples of such a material include an organic aromatic polymer material, a porous inorganic material having a reduced density in a film, and a porous organic polymer.

A method for forming a wiring of a semiconductor device when an organic polymer, which is one of such materials, is used as an interlayer insulating film will be sequentially described with reference to the process chart of FIG.

First, an aluminum wiring 102 is formed on an insulating substrate 101 (step (a) in FIG. 1), and then an organic polymer low dielectric constant film 103 is applied and heated to form a film (FIG. 1 (b)). )
Process).

Next, a silicon nitride film 104 is formed by a CVD method (FIG. 1C). Next, the silicon nitride film 104
An opening (via hole) 105 is formed in the organic polymer low dielectric constant film 103 using the silicon nitride film as a hard mask (step (d) in FIG. 1).

Next, after forming the TiN barrier layer 106,
The tungsten wiring 107 is buried in the opening to form a wiring layer (FIG. 1E).

At this time, when the tungsten wiring 107 is buried in the via hole 105, moisture is degassed in the via hole 105 due to the moisture permeation of the organic polymer insulating film 103, and the inside of the via hole 105 due to a poor filling of the wiring called a poisoned via is generated. Therefore, the moisture permeability of the organic polymer insulating film 103 is a problem.

[0011] Incidentally, those related to this kind of technology include, for example, the 2000 International Interconnect Technology Conference Lecture Book, P1
58-P160 (Proceedings of the 2000 Internatio
nal Interconnect Technology Conference, P158-P16
8).

[0012]

In the above-described conventional device forming method, only the permeation and degassing of moisture when the upper tungsten wiring 107 is buried is a problem, but the density in the organic aromatic polymer material or film is reduced. When a reduced porous inorganic material or porous organic polymer is used as an interlayer insulating film for a semiconductor device, not only the moisture permeability of the interlayer insulating film when forming wiring, but also the moisture resistance of the device itself after formation. Sex is an important issue.

Unlike an insulating film such as a silicon oxide film or a silicon nitride film formed by a CVD method, the organic insulating film itself does not have a function of blocking the permeation of moisture or suppressing the adsorption of moisture. In addition, even with a porous inorganic material, there is a concern about permeation and adsorption of moisture into the pores.

Further, in the case of semiconductor products for consumer use,
Most semiconductor elements are used as resin-sealed package products. The main component of the sealing resin is an epoxy-based material, which itself permeates and adsorbs moisture, and thus has no effect of blocking the permeation of moisture to the internal semiconductor element.

The permeation and adsorption of moisture as described above cause corrosion of wiring inside the semiconductor element, and the poor reliability of the semiconductor element becomes an important problem.

The present invention is proposed in view of such a problem, and is necessary for reducing the dielectric constant of an interlayer insulating film, suppressing the capacitance between wirings, and promoting low power consumption and high speed. Indispensable organic polymer materials and porous inorganic materials,
Alternatively, it is an object of the present invention to provide a semiconductor device using a porous organic polymer for an interlayer insulating film, which solves the above problems and improves the humidity resistance of the element itself.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
The following problems are solved by the following. That is, in a semiconductor device including a wiring layer and an interlayer insulating film layer, in order to prevent moisture absorption and moisture permeation from a peripheral portion, a partition wall portion formed of a material for forming a wiring layer so as to surround an element periphery (in the present invention, a guard portion) The lower portion of the ring portion is formed so as to be embedded in the semiconductor substrate.

It is needless to say that the periphery of the element on which the partition wall is formed refers to the periphery with respect to the main surface on which transistors, capacitors, etc. are formed. This shields moisture permeating the inside of the interlayer insulating film from around the element or from the interface between the substrate and the interlayer insulating film, thereby improving the humidity resistance reliability of the element itself.

Further, the semiconductor device of the present invention is characterized in that a passivation film formed on the outermost surface of the element for preventing moisture absorption and moisture permeation is formed so as to cover the element up to the outer peripheral portion of the element end. And This shields the moisture permeating the inside of the interlayer insulating film not only from the element surface but also from the element periphery, thereby improving the humidity resistance reliability of the element itself.

Further, in the semiconductor device of the present invention, a passivation film formed on the outermost surface of the element for preventing moisture absorption and moisture permeation is formed so as to be buried in the inside of the semiconductor substrate at the outer periphery of the element end. The element is covered with the element. This shields not only the element surface but also the moisture permeating through the inside of the interlayer insulating film from around the element and from the interface between the substrate and the interlayer insulating film, thereby improving the humidity resistance reliability of the element itself.

Further, in the semiconductor device of the present invention, the lower part of the guard ring around the semiconductor element is formed so as to be embedded in the inside of the semiconductor substrate, and the passivation film on the outermost surface extends the element to the outer peripheral part of the element end. It is characterized by being formed so as to cover.

Further, in the semiconductor device of the present invention, the lower part of the guard ring around the semiconductor element is formed so as to be embedded in the semiconductor substrate, and the guard ring is embedded inside the semiconductor substrate at the outer periphery of the element end. Formed so as to cover the element.

The interlayer insulating film used in the present invention is:
It is characterized by being formed using an organic polymer material, a porous inorganic material whose density in the film is reduced, or a porous organic polymer.

Examples of the organic polymer material include materials such as polyimide, polyparaxylylene, polyarylene ether, polyarylene, benzcyclobutene, and polynaphthalene.

Examples of porous inorganic materials include Hydrogen
Silesquioxane (H-SiO) structured inorganic SOG (S
pin on Glass) material or Methyl Silsesquioxan
A material whose relative dielectric constant is reduced to less than 3.0 by making the inside of the film porous based on an organic SOG having an e (CH ₃ —SiO) structure is exemplified.

Further, the present invention is characterized in that the passivation film used in the present invention is formed mainly of silicon nitride. It is well known that silicon nitride blocks moisture, and is an optimal material for a film for covering an element to prevent moisture from permeating.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings.

[0028]

<Embodiment 1> FIG. 2 is a sectional view for explaining a semiconductor DRAM (Dynamic Random Access Memory) element according to a first embodiment. A groove 202 having a depth of about 300 to 400 nm is selectively formed in a device isolation region on a p-type semiconductor substrate 201 by using a well-known dry etching method.

Next, in order to remove the etching damage layer formed on the inner wall of the groove 202, for example, 850 ° C. to 900 ° C.
A thin oxide film (about 10 nm) 203 is formed by a wet oxidation method at about
01 is formed on the main surface by plasma CVD using, for example, ozone and tetraethoxysilane as a source gas.
An oxide film 204 of about 00 nm is formed.

Next, the oxide film 204 is subjected to chemical mechanical polishing (CM).
Polishing is performed using the P) method to remove the oxide film 204 in a region other than the groove 202 and leave the oxide film 204 in the groove 202.

Next, phosphorus is selectively ion-implanted into the memory array formation region of the substrate 201 to form an n-type well region 205. Thereafter, boron is selectively ion-implanted into the main surface of the n-type well region 205 to form a p-type well region 206. Next, a wet oxidation process at about 850 ° C.
Gate insulating film 20 made of an oxide film of about 7 nm
7 is formed. Then, a gate electrode 208 is formed over the gate insulating film 207. In this step, a word line integrated with the gate electrode 208 is also formed.

Gate electrode 208 and word line (WL)
Is to form a polycrystalline silicon film into which phosphorus of about 70 nm is introduced by a CVD method, and then form a tungsten nitride film of about 50 nm and a tungsten film of about 100 nm thereon by a sputtering method. Then, a cap insulating film 209 made of a silicon nitride film of about 150 nm is further formed thereon by a CVD method, and then these films are patterned to complete the process. Next, after a silicon nitride film of about 50 nm to 100 nm is formed on the main surface of the p-type well region 206 by a CVD method, anisotropic etching is performed on the silicon nitride film using well-known RIE (Reactive Ion Etching). To form a sidewall spacer 211 on the side wall of the gate electrode 208. In this step, the side wall spacers 211 are connected to the word lines (W
L) is also formed on the side wall.

Next, arsenic is ion-implanted into the main surface of the n-type semiconductor region 210 to form an n-type semiconductor region 212. By this step, the LDD structure (Lightly Doped Drai
The n) field effect transistor for memory cell selection is formed.

Next, a first interlayer insulating film 213 is formed on the main surface of the p-type semiconductor substrate 201. First interlayer insulating film 2
No. 13 is formed by spin coating using a porous inorganic SOG material (trade name: OCL-T32, manufactured by Tokyo Ohka Co., Ltd.) and heating at 400 ° C. for 60 minutes as a final heating condition.

Next, the first interlayer insulating film 213 on the n-type semiconductor region 212 is selectively removed. That is, a resist TDUR-P for forming a connection hole is formed on the first interlayer insulating film 213.
Using 036 (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.), a resist pattern for forming the connection holes 1214A and 1214B is formed.

Next, using the resist pattern as a mask, a first gas is formed using a plasma gas containing at least CF ₄ .
Is etched to form a connection hole 214A and a connection hole 214B. Thereafter, the resist film is completely removed by oxygen ashing, and the connection holes 214A,
A conductive plug 215 is formed inside each of the connection holes 214B. At this time, the removal by ashing uses a high frequency inductive coupling type ashing device.

The conductive plug 215 is formed on the first interlayer insulating film 2.
13 is a polycrystalline silicon film doped with impurities.
After being formed by the method, the polycrystalline silicon film is selectively formed only in the connection hole by polishing using a CMP method.

Next, the conductive plug 21 in the connection hole 214A
Then, a bit line (BL) electrically connected to the bit line 5 is formed.
Then, the first interlayer insulating film 2 including on the bit line (BL)
A second interlayer insulating film 216 is formed on 13. This second
Is formed in the same manner as the first interlayer insulating film 213.

Next, the second interlayer insulating film 216 on the conductive plug 215 is selectively removed by a dry etching method to form a connection hole 217, and thereafter, a conductive plug 218 is formed inside the connection hole 217. . The conductive plug 218 is formed in the same manner as the conductive plug 215.

Next, a capacitor 219 is formed on the second interlayer insulating film 216 including the conductive plug 218 by a known method.
To form Next, Si is used as the third interlayer insulating film 220.
LK (trade name, manufactured by Dow Chemical Co., USA) is spin-coated, heated on a hot plate at 180 ° C. and 320 ° C. for 1 minute each, and then heated in a furnace heating furnace for 400 minutes.
Heat cured at 60 ° C. for 60 minutes (film thickness: 600 nm).

Next, on the third interlayer insulating film 220, a fourth interlayer insulating film 221 (film thickness 100
m). Next, a resist pattern for forming a connection hole is formed on the fourth interlayer insulating film 221 using a resist TDUR-P036 (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for forming a connection hole. An opening is formed in the fourth interlayer insulating film 221 using the resist pattern as a mask.

Next, using the fourth interlayer insulating film 221 as a mask, an opening is formed in the third interlayer insulating film 220 using an etching gas containing ammonia gas as a main component. Next, tungsten 222 is buried in the connection hole by using the CVD method. And SEMI-SPERSE as an abrasive
(R) Unnecessary tungsten on the fourth interlayer insulating film 221 is removed by performing chemical mechanical polishing (CMP) using W2000 (trade name of Cabot). As a result, the surface of the fourth interlayer insulating film 221 is hardly polished, that is, the fourth interlayer insulating film 221 functions as a polishing stopper, and the polishing is substantially performed when the fourth interlayer insulating film 221 is exposed. Stop.

Next, an aluminum alloy film is formed as the uppermost wiring, and the aluminum alloy film is patterned to form an upper wiring 223. Next, the fourth layer including the upper wiring 223 is formed.
An SiO insulating film 224 (thickness: 1000 nm) is formed by a CVD method so as to cover the surface of the interlayer insulating film 221.

Then, as a passivation film, Si
SiN film 225 so as to cover the surface of O insulating film 224
(Thickness: 1200 nm), and a photosensitive polyimide film PL-H708 as a chip coat film is further formed thereon.
(Trade name of Hitachi Chemical Co., Ltd.) 226 is formed.
The polyimide film 226 has an opening formed in advance corresponding to the scribe line and the bonding pad portion.

Finally, by a well-known blade dicing method, individual chips are cut out along the aforementioned scribe lines to complete a semiconductor memory device.

At this time, as a feature of the memory device of the present invention, a guard ring portion 227 serving as a partition surrounding the inside of the element is formed in a peripheral portion thereof. That is, the guard ring portion 227 includes the first insulating film 213, the second insulating film 216,
It is formed of the same material as a conductive plug or wiring provided through the third insulating film 220 and the fourth insulating film 221. One end is in the SiO insulating film 224, and the other end is a p-type well. It is formed so as to be embedded inside the region 206.

By the structure of the guard ring 227, it is possible to completely block moisture permeating from the end into the inside of the interlayer insulating film and the lower surface with respect to the substrate, so that moisture can enter the element internal region. Disappears. This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 2> FIG. 3 shows a semiconductor DRA according to a second embodiment.
It is sectional drawing of M. The difference from the first embodiment is that one end of the guard ring 327 provided at the peripheral portion (the end of the element) is p
Si which is provided in contact with the mold well region 306 and is a passivation film
It is characterized by being covered with the N film 325.

With the structure of the passivation film 325, it is possible to completely block moisture that permeates the inside of the interlayer insulating film from the end of the device, and it is impossible for the moisture to enter the inside of the device. This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 3> FIG. 4 is a sectional view of a semiconductor logic device according to a third embodiment. A known S on a semiconductor substrate 401
An element isolation film region 402 is formed using TI (Shallow Trench Isolation), and a MOS transistor 403 is formed inside the element isolation film region 402.

Then, 50 nm is formed using a known CVD method.
Silicon oxide film 404 and BPS of about 500 nm
G (boron phosphorus silicate glass) film 405
After sequentially forming on the surface of the semiconductor substrate 401 including the MOS transistor 403, reflow annealing is performed in a nitrogen atmosphere at, for example, 800 to 900 ° C.

Next, the surface of the BPSG film 405 is flattened and polished using, for example, a chemical mechanical polishing method (CMP method) using silica abrasive grains, and then a contact hole is formed. To form conductive plugs 406. At this time,
Unnecessary tungsten existing on the surface of the BPSG film 405 has been removed by a known etch-back method.

Next, an upper wiring layer 407 made of a patterned aluminum alloy is formed on the BPSG film 405. Next, using a porous inorganic SOG material (trade name: OCL-T32 manufactured by Tokyo Ohka Co., Ltd.), spin coating is performed, and heating is performed at 400 ° C. for 60 minutes as a final heating condition, so that the first insulating film 408 ( (Thickness: 500 nm).

Wiring forming resist TDUR-P080
An opening is formed in the first insulating film 408 in the same manner as in the first embodiment using (trade name of Tokyo Ohka Kogyo Co., Ltd.). Next, tungsten is buried in the above-mentioned connection hole by using the CVD method, and a conductive plug 409 is formed.

Next, a patterned upper wiring 410 made of an aluminum alloy is formed so as to be electrically connected to the conductive plug 409. Hereinafter, the above steps are repeated to form a second layer interlayer insulating film 411 (second interlayer insulating film).

Next, an SiO insulating film 414 (thickness: 1000 nm) is formed as a third interlayer insulating film by a normal CVD method so as to cover the surface of the second interlayer insulating film 411 including the upper wiring 413.

Then, a passivation film 415 (1200 nm thick) made of a SiN film is formed by using a normal CVD method.
m) and a photosensitive polyimide PL-H708 (trade name, manufactured by Hitachi Chemical Co., Ltd.)
(2.5 μm) are sequentially formed so as to cover the above-mentioned laminated interlayer insulating film.

Openings are formed in the chip coat film 416 in advance at positions corresponding to the scribe lines and the bonding pad portions, and individual chips are cut out and separated by a known blade dicing method, thereby forming a semiconductor logic. The device is completed.

At this time, in the semiconductor logic device,
A guard ring portion 417 is formed in a peripheral portion (device end portion) as a partition surrounding the inside of the device. That is, BPS
G film 405, first insulating film 408, second insulating film 41
First, the first insulating film 414 is formed of the same material as the conductive plug and the wiring provided through the third insulating film 414. One end is in the SiO insulating film 414 and the other end is in contact with the semiconductor substrate 401. Have been.

Then, the same SiN415 as the passivation film formed on the uppermost surface of the element is formed so as to be buried in the inside of the semiconductor substrate at the outer peripheral portion of the element end in order to prevent moisture absorption and moisture permeation, and integrated with the passivation film. And is formed so as to cover the entire element.

With the structure of the passivation film 415, it is possible to completely shut off the moisture permeating the inside of the interlayer insulating film from the end of the element, and it is impossible for the moisture to enter the inside of the element. This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 4> FIG. 5 is a sectional view of a semiconductor logic device according to a fourth embodiment. The difference from the third embodiment is that one end of the guard ring 517 at the end of the element is connected to the semiconductor substrate.
That is, it is formed so as to be embedded inside the 501. That is, in the third embodiment, one end of the plug 406 is formed so as to be in contact with the semiconductor substrate 401, whereas in the present embodiment, one end of the conductive plug 506 forming a part of the guard ring portion 517 is connected to the semiconductor substrate 501. Embedded inside.

By the structure of the guard ring and the structure of the passivation film, it is possible to completely block moisture permeating from the end of the device into the inside of the interlayer insulating film and the lower surface of the substrate, and the moisture enters the inside of the device. You can't do that. This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 5> FIG. 6 is a sectional view of a semiconductor logic element according to a fifth embodiment. A known S on a semiconductor substrate 601
An element isolation film region 602 is formed by using TI (Shallow Trench Isolation), and a MOS transistor 603 is formed inside the element isolation film region 602.

Then, 50 nm is formed by using a known CVD method.
Silicon oxide film 604 and BPS of about 500 nm
G (boron phosphorus silicate glass) film 605
After sequentially forming on the surface of the semiconductor substrate 601 including the MOS transistor 603, reflow annealing is performed in a nitrogen atmosphere at 800 to 900 ° C., for example.

Next, the surface of the BPSG film 605 is flattened and polished by using, for example, a chemical mechanical polishing method (CMP method) using silica abrasive grains, and then a contact hole is formed. To form a conductive plug 606. At this time,
Unnecessary tungsten existing on the surface of the BPSG film 605 has been removed by a known etch-back method.

Next, on the BPSG film 605,
Upper wiring layer 607 made of coated aluminum alloy
I do. Thereafter, the organic insulating film material FLARE (Hone, US)
ywell Co., Ltd.) and spin-coat 150
℃, 200 ℃, 250 ℃ on a hot plate for each one
Heat treatment for 10 minutes, and the oxygen concentration is 10 ppm or less.
_TwoAfter heating at 400 ° C for 60 minutes in the atmosphere,
The first insulating film 608 (film thickness 50
0 nm).

Next, on the first insulating film 608, an SiN film (thickness: 100 nm) 6 serving as a hard mask for opening is formed.
18 is formed by a CVD method. Next, a resist pattern for forming a connection hole is formed on the SiN film 618 using a resist TDUR-P036 (trade name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for forming a connection hole. Using the resist pattern as a mask, an opening is formed in the SiN film 618 by a dry etching method using CF ₄ gas as a main component.

Next, using the SiN film 618 as a mask, an opening is formed in the first insulating film 608 using an etching gas containing ammonia gas as a main component. Next, tungsten is buried in the above-mentioned connection hole by using the CVD method, and a conductive plug 609 is formed. At this time, unnecessary tungsten existing on the SiN film 618 is removed by a known etch-back method.

Next, a patterned upper wiring 610 made of an aluminum alloy is formed so as to be electrically connected to the conductive plug 609.

Thereafter, the above steps are repeated to form a second-layer interlayer insulating film 611 (second insulating film) and an upper wiring layer 613.

Next, the SiN film 61 including the upper wiring 613
A third insulating film SiOF insulating film 614 (thickness: 1000 nm) is formed by a normal CVD method so as to cover the surface of No. 9.

Then, a passivation film 615 (1200 nm thick) made of a SiN film is formed by using a normal CVD method.
m) and photosensitive polyimide PL-H708 (trade name, manufactured by Hitachi Chemical Co., Ltd.)
(2.5 μm) are sequentially formed so as to cover the above-mentioned laminated interlayer insulating film.

Openings are formed in the chip coat film 616 at positions corresponding to the scribe lines and the bonding pad portions, and individual chips are cut out and separated by a known blade dicing method, thereby forming a semiconductor logic. The device is completed.

At this time, in the semiconductor logic device,
A guard ring portion 617 serving as a partition surrounding the inside of the element is formed in the peripheral portion. That is, the BPSG film 605,
The first insulating film 608, the second insulating film 611, and the third insulating film 614 are formed of the same material as a conductive plug or a wiring provided therethrough, and one end is in the SiOF insulating film 614, One end of the guard ring portion 617 is formed so as to be embedded inside the semiconductor substrate 601.

Then, as shown in the figure, a SiN film 6 as a passivation film is formed up to the element surface and the periphery of the element end.
15. With the structure of the guard ring portion 617 and the passivation film 615, it is possible to completely block moisture permeating the inside of the interlayer insulating film from the end of the device, so that moisture cannot enter the inside of the device.
This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 6> FIG. 7 is a sectional view of a semiconductor logic device according to a sixth embodiment. SOI on semiconductor substrate 701
(Silicon on Insulator) layer 71
8 on which a known STI (Shallow Trench I
An element isolation film region 702 is formed by using the MOS transistor 70 inside the element isolation film region 702.
Form 3

Then, 50 nm is formed using a known CVD method.
Silicon oxide film 704 and BPS of about 500 nm
G (boron phosphorus silicate glass) film 705
After the MOS transistors 703 are sequentially formed on the surface of the semiconductor substrate 701 including the MOS transistors 703, reflow annealing is performed in a nitrogen atmosphere at 800 to 900 ° C., for example.

Next, the surface of the BPSG film 705 is flattened and polished by, for example, a chemical mechanical polishing method (CMP method) using silica abrasive grains, and then a contact hole is formed. To form a conductive plug 706. At this time,
Unnecessary tungsten existing on the surface of the BPSG film 705 has been removed by a known etch-back method.

Next, on the BPSG film 705,
Upper wiring layer 707 made of coated aluminum alloy
I do. Next, the porous inorganic SOG material XLK-25 (Rice Do
w Coming product name) and spin coating
And, as the final heating condition, N 2 _Two
Heating is performed at 400 ° C. for 60 minutes in an atmosphere.
An insulating film 708 (thickness: 500 nm) is formed.

Wiring forming resist TDUR-P080
As in the first embodiment, an opening is formed in the first insulating film 708 as a connection hole using (trade name of Tokyo Ohka Kogyo Co., Ltd.). Next, tungsten is buried in the above-described connection hole by using the CVD method, and a conductive plug 709 is formed.

Next, a patterned upper wiring 710 made of an aluminum alloy is formed so as to be electrically connected to the conductive plug 709.

Thereafter, the above steps are repeated to form a second interlayer insulating film 711. Next, a normal C is formed so as to cover the surface of the second insulating film 711 including the upper wiring 713.
A third insulating film SiOF insulating film 714 (thickness: 1000 nm) is formed by the VD method.

Then, a passivation film 715 (1200 nm thick) made of a SiN film is formed by using a normal CVD method.
m) and a photosensitive polyimide PL-H708 (trade name, manufactured by Hitachi Chemical Co., Ltd.)
(2.5 μm) are sequentially formed so as to cover the above-mentioned laminated interlayer insulating film. In the chip coat film 716,
Openings are formed in advance at positions corresponding to the scribe lines and the bonding pad portions, and individual chips are cut out and separated using a known blade dicing method, thereby completing a semiconductor logic device.

At this time, in the present embodiment, the guard ring 7
One end of a conductive plug 706 constituting a part of the SOI layer 17 is formed so as to be embedded in the SOI layer 718.

In this embodiment, by using the SOI substrate, the characteristics of the element can be improved, and a high-speed and high-performance semiconductor device can be obtained.

In such a semiconductor device, the structure of the guard ring 717 shown in this embodiment makes it possible to completely block moisture permeating from the element end into the inside of the interlayer insulating film and the lower surface with the substrate. Water cannot enter the inside of the device. This effectively acts to improve the humidity resistance reliability of the element itself. <Embodiment 7> FIG. 8 is a sectional view of a resin-sealed semiconductor logic device according to a seventh embodiment. The semiconductor logic device 801 obtained in the third embodiment or the fourth, fifth and sixth embodiments is fixed to a separately provided lead frame in a die bonding step.

Thereafter, the gold wire 80 is connected between the bonding pad portion provided on the semiconductor logic device 801 and the external terminal 806 of the lead frame 805 by a wire bonder.
Wired at 4.

Next, using a commercially available silica-containing biphenyl-based epoxy resin, a resin sealing portion 803 was formed so as to surround the semiconductor logic device 801 and the external terminals 806 and the like. The sealing conditions are a molding temperature of 180 ° C. and a molding pressure of 70 kg.
/ Cm ² , but is not limited thereto.

Finally, by bending the external terminal 806 into a predetermined shape, a completed resin-sealed semiconductor logic device is obtained.

In a resin-sealed semiconductor logic device,
Moisture that permeates from the edge of the internal element to the inside of the interlayer insulating film or the lower surface with the substrate can be completely blocked,
Since the inside of the element has a structure in which moisture cannot enter, it is needless to say that the same effect as that described in the third embodiment or the fourth, fifth and sixth embodiments is obtained. Furthermore, since it is sealed with resin, it is possible to exhibit stable high-speed operation characteristics with respect to an external environment.

The above has been described in detail using the embodiments.
The conditions for achieving the present invention and the examples are not limited to these examples.

[0088]

As described above, the semiconductor device according to the present invention is indispensable for lowering the dielectric constant of the interlayer insulating film, suppressing the capacitance between wirings, and promoting low power consumption and high speed. Organic polymer materials and porous inorganic materials,
Alternatively, when the porous organic polymer is used for the interlayer insulating film, it is possible to completely block moisture permeating from the end portion into the inside of the interlayer insulating film or the lower surface portion with the substrate, and the moisture enters the inside of the element. This makes it possible to obtain a semiconductor device in which the humidity resistance reliability of the element itself is improved.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing an example of a conventional semiconductor device.

FIG. 2 is a sectional view of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor logic device according to a third embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor logic device according to a fourth embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor logic device according to a fifth embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor logic device according to a sixth embodiment of the present invention.

FIG. 8 is a sectional view illustrating a resin-sealed semiconductor device according to a seventh embodiment of the present invention.

[Explanation of symbols]

101, 401, 501, 601, 701: substrate, 102: wiring, 103: organic polymer low dielectric constant film, 104: hard mask, 105: opening (via hole), 106: barrier layer, 107: tungsten wiring, 201, 301 ... p-type semiconductor substrate, 202, 302 ... trench, 203, 303, 204, 304 ... oxide film, 205, 305 ... n-type well region, 206, 306 ... p-type well region, 207, 307 ... gate insulating film, 208 , 308 gate electrode, 209, 309 cap insulating film, 210, 310 n-type semiconductor region, 211, 311 sidewall spacer, 212, 312 n-type semiconductor region, 213, 313 first interlayer insulating film , 214A, 214B, 314A, 314B, 217, 3
Reference numeral 17: connection hole, 215, 315, 218, 318: conductive plug, BL: bit line, 216, 316: second interlayer insulating film, 219, 319: capacitor, 220, 320 ... third interlayer insulating film, 221 , 321: SiN film, 222, 322: connection plug, 223, 323: upper wiring, 224, 324: insulating film, 225, 325, 415, 515, 615, 715: passivation film, 226, 326, 416, 516, 616, 716, 8
02: chip coat film, 227, 327, 417, 517, 617, 717: guard ring portion, 402, 502, 602, 702: element isolation film region, 403, 503, 603, 703: MOS transistor, 404, 504, 604, 704: silicon oxide film, 405, 505, 605, 705: BPSG, 406, 506, 606, 706, 409, 509, 6
09, 709, 412, 512, 612, 712 ... conductive plug, 407, 507, 607, 707, 410, 510, 6
10, 710, 413, 513, 613, 713: wiring layer, 408, 508, 608, 708: first insulating film, 411, 511, 611, 711: second insulating film, 414, 514, 614, 714 ... Third insulating film, 718 SOI layer, 801 semiconductor element, 803 epoxy sealing resin, 804 gold wire, 805 lead frame, 806 external terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Miharu Otani 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi, Ltd. Production Technology Research Institute (72) Inventor Katsuhiko Hotta 5--22 Kamimizuhoncho, Kodaira-shi, Tokyo No. 1 Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Yasumichi Suzuki 5-20-1, Josuihoncho, Kodaira-shi, Tokyo F-term in the Hitachi, Ltd. Semiconductor Group (reference) 5F033 HH04 HH08 HH19 HH34 JJ04 JJ19 KK01 KK04 LL04 MM08 MM13 PP06 QQ09 QQ12 QQ37 QQ48 QQ74 QQ75 RR04 RR06 RR09 RR15 RR21 RR22 RR25 SS11 SS22 TT04 VV16 XX18 XX24 A02B04A08 MA08 PR33 PR39 PR40

Claims (8)

[Claims] In a semiconductor device including a semiconductor element, a wiring layer, and a plurality of interlayer insulating film layers on a semiconductor substrate, a partition portion made of a material forming the wiring layer so as to surround a periphery of the semiconductor element. Wherein a lower portion of the semiconductor device is disposed so as to penetrate at least a plurality of interlayer insulating film layers on the semiconductor substrate. 2. A semiconductor device comprising a semiconductor element, a wiring layer, and an interlayer insulating film layer on a semiconductor substrate, wherein a lower portion of a partition wall made of a material forming the wiring layer surrounds the periphery of the semiconductor element. A semiconductor device formed so as to penetrate through the interlayer insulating film layer and be embedded in a semiconductor substrate. 3. A semiconductor device including a semiconductor element, a wiring layer, and a plurality of interlayer insulating film layers on a semiconductor substrate, wherein a passivation film formed on the outermost surface of the semiconductor element includes:
A semiconductor device extending to an outer peripheral portion of an end of the semiconductor element and covering the semiconductor element so as to cover at least a depth of a lowermost layer of the plurality of interlayer insulating film layers. . 4. A semiconductor device including a semiconductor element, a wiring layer, and an interlayer insulating film layer on a semiconductor substrate, wherein a passivation film formed on an outermost surface of the semiconductor element is formed on an outer peripheral portion of an end of the semiconductor element. A semiconductor device which is formed so as to extend and be embedded in a semiconductor substrate. 5. In a semiconductor device including a semiconductor element, a wiring layer, and a plurality of interlayer insulating film layers on a semiconductor substrate, a partition portion made of a material forming the wiring layer so as to surround a periphery of the semiconductor element. Is disposed through at least a plurality of interlayer insulating film layers on the semiconductor substrate, and a passivation film formed on the outermost surface of the semiconductor element is formed on an outer peripheral portion of an end of the semiconductor element. A semiconductor device, wherein the semiconductor device is formed so as to extend and cover at least a depth of a lowermost layer of the plurality of interlayer insulating film layers to cover the semiconductor element. 6. A semiconductor device including a semiconductor element, a wiring layer, and an interlayer insulating film layer on a semiconductor substrate, wherein a lower portion of a partition wall made of a material forming the wiring layer surrounds the periphery of the semiconductor element. A passivation film formed so as to be embedded in the semiconductor substrate through the interlayer insulating film layer and formed on the outermost surface of the semiconductor element, extending to an outer peripheral portion of an end of the semiconductor element A semiconductor device formed to be embedded in a semiconductor substrate. 7. The semiconductor according to claim 1, wherein said interlayer insulating film layer is formed of at least one kind of insulating film of an organic insulating film and a porous inorganic film. apparatus. 8. The semiconductor device according to claim 3, wherein said passivation film is formed mainly of silicon nitride.
6. The semiconductor device according to any one of items 1 to 5,