JP2002190598A - Thin-film transistor array substrate and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film transistor array substrate, used in a liquid crystal display or the like which has superior characteristics and a low defective rate, having no increase in the number of manufacturing processes, and to provide a method of manufacturing the same. SOLUTION: Using gray-tone exposure technology, interconnections which are partially different in thickness are formed, without having to increase the number of processes. In a part where electrical interconnections, such as scanning lines and signal lines intercross, difference in level between the interconnections can be reduced, resulting in improving the step coverage of an insulation film and reducing defects, such as short-circuitings and disconnections between the interconnections. Since a gate insulation film can be formed thinner than in the conventional one, an on-state current of the thin film transistor is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type display device such as a liquid crystal display device.
The present invention relates to a thin film transistor array substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a pixel of an active matrix type display device such as a liquid crystal display device has a thin film transistor (T
FT). As a method of manufacturing a thin film transistor array substrate in which the TFTs are arranged in a matrix, the following methods have conventionally been used. FIG. 8 is a schematic view of a manufacturing process of a thin film transistor array substrate using a bottom gate type TFT as a TFT. Hereinafter, a conventional method for manufacturing a thin film transistor array substrate will be specifically described with reference to FIG.

First, Ti, Mo, W, Al, Ta, Cr
A gate electrode is formed by forming a metal film made of a single layer film or a stacked film of these alloys with a thickness of 300 to 500 nm and etching the metal film using a photoresist patterned by photolithography as a mask ( FIG. 8 (a)).

Next, a gate insulating film, an active layer, and a contact layer are successively formed by a plasma CVD method. In this embodiment mode, a silicon nitride film as a gate insulating film, an amorphous silicon film as an active layer, and an n + silicon film as a contact layer are formed by changing a source gas and plasma conditions.

For example, a silicon nitride film is made of SiH ₄ gas,
NH ₃ gas, H ₂ gas and N ₂ gas are used as raw materials, the amorphous silicon film is made of SiH ₄ gas diluted to about 10% by H ₂ gas, and the n + silicon film is made of PH ₃ gas as the raw material gas of the amorphous silicon film. It can be formed by mixing gases.

The thickness of each layer is 30 gate insulating films.
The active layer is formed to have a thickness of 100 to 300 nm, and the contact layer is formed to have a thickness of 20 to 80 nm. Next, the active layer and the contact layer are patterned into an island shape by a photolithography process (FIG. 8B).

Then, Ti, Mo, W, Al, Ta, C
A source / drain electrode is formed by forming a metal film composed of a single layer film or a laminated film of r and an alloy thereof with a thickness of 200 to 400 nm and etching the metal film using a photoresist patterned by photolithography as a mask. Form. At this time, the contact layer on the channel region of the active layer is simultaneously etched to separate the channel region from the contact region (FIG. 8C).

Next, an insulating film such as a silicon nitride film serving as a passivation film is formed by plasma CVD or the like.
The passivation film is formed with a thickness of 0 to 500 nm, and thereafter, a hole is formed in the passivation film by photolithography and etching to make contact with the source / drain regions (FIG. 8D).

Finally, a transparent conductive film such as an ITO film is formed and processed as a pixel electrode by photolithography and etching to complete a thin film transistor array substrate (FIG. 8E).

FIG. 7 is a plan view of a conventional thin film transistor array substrate.

In recent years, with the increase in size and definition of display devices, there has been a demand for an improvement in the driving capability of the TFTs constituting the thin film transistor array substrate. The pixel driving capability of the TFT is determined by the mobility () of the TFT, the ratio (W / L) of the channel width (W) to the channel length (L), the capacitance of the gate insulating film (C _ins ), and the like. As a result, the pixel driving capability is improved. The mobility of the TFT is improved by improving the characteristics of the semiconductor film or the interface between the semiconductor film and the gate insulating film. Further, the improvement of the gate insulating film capacity can be realized by using an insulating material having a high dielectric constant as the insulating film or by reducing the thickness of the gate insulating film.

In addition, when viewed on the entire thin film transistor array substrate, the resistance of the wiring such as the scanning line and the signal line also affects the driving capability of the pixel. In particular, a large thin film transistor array substrate is required to have low wiring resistance.

[0013]

In order to improve the driving capability of the TFT, it is effective to reduce the thickness of the gate insulating film. It is also desirable to reduce the thickness of the gate insulating film in terms of improving productivity. However, the gate insulating film covers the thickness difference of the gate electrode, and also plays a role of preventing a short circuit between the gate electrode and the source / drain electrode. Therefore, when the thickness of the gate insulating film is reduced, defects such as poor insulation between a gate electrode and a source / drain electrode in a thin film transistor, short-circuit of a storage capacitor, short-circuit of a scanning line and a signal line, and the like, increase, and the yield decreases. I do. This problem,
The problem can be solved by reducing the thickness of the gate electrode, but on the other hand, the wiring resistance of the entire thin film transistor array substrate is increased, which causes a problem that the driving capability of the pixel is reduced. Therefore, it has been difficult to achieve both a reduction in the thickness of the gate insulating film and a reduction in the wiring resistance.

The present invention solves the above-mentioned problems, and improves the characteristics and productivity without increasing defects such as an increase in wiring resistance, a short circuit of a thin film transistor, a short circuit of a storage capacitor, and a short circuit between wirings. It is an object of the present invention to provide a thin film transistor array substrate and a method of manufacturing the same.

[0015]

In order to achieve the above object, a thin film transistor array substrate according to the present invention is characterized in that a scanning line serving also as a gate electrode has at least two film thicknesses, and at least a thin film transistor of the scanning line has It is characterized in that the film thickness of a portion corresponding to the channel portion is thinner than other portions. Thus, the thickness of the gate insulating film can be reduced without increasing the short-circuit failure of the thin film transistor, so that the characteristics and productivity of the thin film transistor array substrate are improved. Also, the wiring resistance hardly changes.

Further, in the thin film transistor array substrate according to the present invention, the scanning line serving also as the gate electrode and the storage capacitor electrode has at least two film thicknesses, and the film thickness of at least a portion of the scanning line corresponding to the storage capacitor electrode is provided. However, it is characterized by being thinner than other parts. As a result, the thickness of the gate insulating film can be reduced without increasing the short-circuit failure of the storage capacitor, so that the characteristics and productivity of the thin film transistor array substrate are improved. Also, the wiring resistance hardly changes.

Further, in the thin film transistor array substrate according to the present invention, the scanning line has at least two film thicknesses,
At least a portion of the scanning line that intersects with the signal line is thinner than other portions. Thus, the thickness of the gate insulating film can be reduced without increasing short-circuit defects between the wirings, so that the characteristics and productivity of the thin film transistor array substrate are improved. Further, since the length of the portion where the film thickness of the scanning line is thin is shorter than that of the scanning line, the wiring resistance does not change much.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the step of forming a scanning line serving also as a gate electrode and a storage capacitor electrode includes a step of forming at least one metal film, and a step of forming a metal film on the metal film. The method is characterized by including at least a step of forming a resist pattern having at least two thicknesses and a step of forming a metal film pattern having at least two thicknesses by etching using the resist pattern as a mask. This enables a scanning line which also serves as a gate electrode and a storage capacitor electrode having at least two thicknesses without increasing the number of manufacturing steps, without increasing the manufacturing cost.
A thin film transistor array substrate having excellent characteristics and productivity can be manufactured.

Further, in another thin film transistor array substrate according to the present invention, the signal line has at least two film thicknesses,
At least a portion of the signal line that intersects with the scanning line has a smaller thickness than other portions. Thus, the thickness of the gate insulating film can be reduced without increasing short-circuit defects between the wirings, so that characteristics and productivity of the thin film transistor array substrate are improved. In addition, since the length of the thin portion of the signal line is shorter than the length of the signal line, the wiring resistance does not change much.

In another thin film transistor array substrate according to the present invention, a signal line serving also as a source electrode has at least two film thicknesses, and the signal line has a film thickness at least at a contact portion of the source electrode with the thin film transistor. It is characterized by being thinner than other parts. Thus, the thickness of the gate insulating film can be reduced without increasing the short-circuit failure of the thin film transistor, so that the characteristics and productivity of the thin film transistor array substrate are improved. Also, the wiring resistance hardly changes.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the step of forming a signal line also serving as a source electrode and the step of forming a drain electrode include the step of forming one or more conductive films and the step of forming at least one conductive film on the conductive film. The method is characterized by including at least a step of forming a resist pattern having two thicknesses and a step of forming a conductive film pattern having at least two thicknesses by etching using the resist pattern as a mask. Accordingly, a signal line serving as a source electrode having at least two thicknesses can be formed without increasing the number of manufacturing steps.
A thin film transistor array substrate having excellent characteristics and productivity can be manufactured without increasing the manufacturing cost.

According to the structure of the thin film transistor array substrate of the present invention, defects and defects can be reduced as compared with the prior art. Alternatively, its characteristics and productivity can be improved. Further, according to the method for manufacturing a thin film transistor array substrate of the present invention, defects and defects can be reduced as compared with the conventional method without increasing the number of manufacturing steps. Alternatively, its characteristics and productivity can be improved.

Further, according to the liquid crystal display device of the present invention, the thin film transistor array substrate for driving the pixel has few defects and defects, and the pixel driving capability is improved, so that the display quality of the liquid crystal display device is improved.

Further, according to the electroluminescent display device of the present invention, the defects and defects of the thin film transistor array substrate for driving the pixel are reduced and the pixel driving capability is improved, so that the display quality of the electroluminescent display device is improved.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described more specifically with reference to examples.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the resist film is exposed by using a mask provided with a light-shielding portion, a semi-light-transmitting portion, and a light-transmitting portion in some photolithography steps. After developing the film, form a resist pattern with irregularities on the surface,
A so-called gray-tone exposure technique is used. This exposure technique is disclosed in JP-A-7-49411 and JP-A-11-307780.

As an embodiment of the present invention, for example, a first resist region and a second resist region having a smaller thickness than the first resist region are formed on a metal film by using the above-mentioned gray tone exposure technique. The formed resist pattern having two film thicknesses is formed. Then, the metal film is etched using the resist pattern as a mask. Here, the second resist region and the second metal region under the resist are etched so that a part of the metal film is also etched.
By appropriately setting the resist film thickness of the resist region, a metal film pattern having two film thicknesses can be formed.

At this time, in the first resist area,
The thickness may be set so that the resist remains.

According to the above-described method, a plurality of patterns can be formed in one photolithography step, so that the number of steps is not increased.

(Embodiment 1) The present embodiment relates to a first example of a thin film transistor array substrate and a method of manufacturing the same.

FIGS. 1 and 2 are a schematic plan view and a schematic sectional view, respectively, of a thin film transistor array substrate according to a first embodiment of the present invention. A scanning line 1 serving also as a gate electrode and a storage capacitor electrode having two thicknesses is formed on a translucent substrate having an insulating surface such as glass, and an island is formed on the scanning line 1 via a gate insulating film. The converted semiconductor film, a signal line 5 also serving as a source electrode, and a drain electrode 6 are sequentially formed. Then, a passivation film 7 for protecting the thin film transistor is formed in a region excluding a contact hole with each electrode, and a pixel electrode 8 connected to a drain electrode is formed on the outermost surface.

In the present embodiment, the thickness of the scanning line at the intersection of the gate electrode 9, the storage capacitor electrode 10, and the signal line is smaller than the thickness of the other portions. I have. The fact that the gate electrode is thinner than other parts
Since the coverage of the gate electrode step with the gate insulating film is improved, defects due to a short circuit between the gate and the source in the thin film transistor are preferably reduced. In addition, the fact that the storage capacitor electrode is thinner than the other portions improves coverage of the electrode step with the gate insulating film, and therefore, a failure due to a short circuit of the storage capacitor formed between the scanning line and the pixel electrode is eliminated. Reduced and desirable. When the storage capacitor is short-circuited, a pixel defect occurs in the liquid crystal display device. In addition, the fact that the film thickness of the scanning line at the intersection with the signal line is thinner than that of the other portion means that the coverage of the electrode step by the gate insulating film is improved, so that a short circuit between the scanning line and the signal line can be prevented. It is desirable that defects due to disconnection of the signal line be reduced.

The method of manufacturing the thin film transistor array substrate according to the present embodiment is as follows. FIG. 3 is a schematic view showing a manufacturing process of the thin film transistor array substrate according to the first embodiment of the present invention.

First, a metal film made of an Al alloy was
Then, a resist pattern having two film thicknesses is formed by a photolithography process using the above-described gray tone exposure technique. Then, a scanning line 1 serving as both a gate electrode and a storage capacitor electrode is formed by etching. In this embodiment mode, a resist pattern (second resist region) having a smaller thickness than other portions is formed in a portion of the scan line which intersects with the signal line after the gate electrode portion and the storage capacitor portion. At the time of the etching, at a portion of the scanning line that intersects with the signal line after the gate electrode portion and the storage capacitor portion, the resist pattern and a part of the metal film thereunder are etched, and the other resist film thicknesses In a thick portion (first resist region), the resist film thickness of the first and second regions is set so that only the resist is etched. As a result, the thickness of the 300-nm-thick scanning line, which intersects with the signal line after the gate electrode portion and the storage capacitor portion, is as thin as 150 nm. (FIG. 3 (a)).

Further, since the gray-tone exposure technique is used for patterning the resist film and the etching is performed at one time, the number of photomasks and the number of steps are not increased as compared with the related art.

Next, a silicon nitride film is formed to a thickness of 200 nm as the gate insulating film 2, an amorphous silicon film is formed to a thickness of 200 nm as the active layer 3, and an n + amorphous silicon film is formed to a thickness of 30 nm as the contact layer 4 by the plasma CVD method. For example, a silicon nitride film is SiH ₄
Gas, NH ₃ gas, H ₂ gas and N ₂ gas as raw materials,
The amorphous silicon film can be formed by using a SiH ₄ gas diluted to about 10% with H ₂ gas as a raw material, and the n + silicon film can be formed by a plasma CVD method in which a PH ₃ gas is mixed with a raw material gas of the amorphous silicon film.

In this embodiment, since the gate electrode portion and the storage capacitor portion of the scanning line are thinner, the gate insulating film covering the gate electrode portion and the storage capacitor portion is 30% smaller than the conventional one.
From 50% thinner. Thereby, the characteristics (for example, the ON current of the TFT) and the productivity of the thin film transistor array substrate are improved. Further, if the thickness of the gate insulating film is set as usual, it is possible to reduce defects such as short circuit and disconnection.

Next, the active layer and the contact layer are patterned into an island shape by a photolithography process (FIG. 3B).

Next, a metal film made of MoW alloy is
A signal line 5 also serving as a source electrode and a drain electrode 6 are formed by etching the metal film using a photoresist patterned by a photolithography process as a mask. At this time,
The contact layer 4 on the channel region of the active layer is simultaneously etched to separate the channel region from the contact region (FIG. 3C).

Next, a silicon nitride film to be a passivation film 7 is formed to a thickness of 400 nm by a plasma CVD method or the like, and then the passivation film is formed by a photolithography process and etching to make contact with source / drain regions. (Fig. 3
(d)).

Finally, an ITO film is formed as a conductive film, and a photolithography process and etching are performed.
By processing it as the pixel electrode 8, a thin film transistor array substrate is completed (FIG. 3E).

In this embodiment, the Al alloy is used as the gate electrode and the MoW alloy is used as the source / drain electrodes. However, the present invention is not limited to these materials, and Ti, Mo,
A single-layer film or a laminated film of W, Al, Ta, Cr and their alloys may be used. Further, the other conductive films, semiconductor films, and insulating films are not limited to the materials described in this embodiment, and may be films that fulfill these functions. Also, their film thicknesses may be set in the same range as in the prior art.

(Embodiment 2) The present embodiment relates to a second embodiment of a thin film transistor array substrate and a method of manufacturing the same.

FIGS. 4 and 5 are a schematic plan view and a schematic sectional view, respectively, of a thin film transistor array substrate according to a second embodiment of the present invention. A signal line 5 also serving as a source electrode having two thicknesses and a drain electrode 6 are formed on a light-transmitting substrate having an insulating surface such as glass, and an islanded semiconductor film, A gate insulating film and a scanning line serving also as a gate electrode and a storage capacitor electrode are sequentially formed. Then, a passivation film for protecting the thin film transistor is formed in a region except for a contact hole with each electrode, and a pixel electrode 8 connected to the drain electrode 6 is formed on the outermost surface.

In the present embodiment, at least the portion of the signal line and the drain electrode, which is located below the active layer, intersects with the scanning line, has a thickness smaller than those of the other portions. And thin. At least a portion of the signal line and the drain electrode, which is arranged below the active layer, is thinner than the other portion, so that the coverage of the signal line and the drain electrode step with the semiconductor film to be the active layer is improved. Therefore, it is desirable to reduce defects due to a short circuit between the gate and the source in the thin film transistor. In addition, the fact that the film thickness of the signal line at the intersection with the scanning line is smaller than the film thickness of the other portion means that the coverage of the electrode step by the gate insulating film is improved, so that a short circuit between the scanning line and the signal line can be prevented. It is desirable that defects due to disconnection of scanning lines be reduced.

The method of manufacturing the thin film transistor array substrate according to the present embodiment is as follows. FIG. 6 is a schematic view showing a manufacturing process of a thin film transistor array substrate according to a second embodiment of the present invention.

First, an n + silicon film and a metal film made of a MoW alloy are sequentially laminated in a thickness of 100 nm and 200 nm, respectively, to form a conductive film. Next, a resist pattern having two film thicknesses is formed on the conductive film by a photolithography process using the above-described gray tone exposure technique. Then, the signal line 5 also serving as the source electrode and the drain electrode 6 are formed by etching.
In this embodiment, of the drain electrode and the signal line,
A portion of the drain electrode, a portion of the source electrode portion of the signal line, and a portion that intersects the scanning line later have a resist pattern (second resist region) having a smaller film thickness than other portions, At the time of etching the conductive film, which is a laminated film of an n + silicon film and a metal film, a part of the drain electrode and a part of the signal line, a part of the source electrode part, and a part that intersects the signal line later have a resist pattern. And only the metal film in the upper layer of the conductive film thereunder is etched, and in other thick portions of the resist (the first resist region), only the resist is etched in the first and second regions. The resist film thickness is set. As a result, in the signal line having a thickness of 300 nm, at a portion where a part of the source electrode intersects with the scanning line later, the thickness is reduced to 100 nm and the n + silicon film is exposed (FIG. 6).
(a)).

Further, since the gray-tone exposure technique is used for patterning the resist film and the etching is performed in a single operation, the number of photomasks and the number of steps are not increased as compared with the related art.

Next, after forming an amorphous silicon film with a thickness of 150 nm as the active layer 3 by a plasma CVD method or the like, the active layer is patterned into an island shape by a photolithography process (FIG. 6B).

Next, a 250 nm-thick silicon nitride film is sequentially formed as a gate insulating film 2 by a plasma CVD method or the like, and a MoW alloy film is formed to a thickness of 250 nm as a metal film serving as a scanning line also serving as a gate electrode by a sputtering method or the like. Next, the metal film is etched using a photoresist patterned by a photolithography process as a mask, thereby forming a scanning line 1 also serving as a gate electrode (FIG. 6C).

In this embodiment, since the thickness of a part of the source electrode part and the part of the drain electrode of the signal line is small, the thickness of the active layer formed so as to cover the part is small. Need not be thicker than necessary. This allows
The productivity of the thin film transistor array substrate is improved. If the thickness of the active layer is set as usual, it is possible to reduce defects such as a short circuit between the gate and the source.

Further, in this embodiment, since the film thickness at the portion intersecting the scanning line after the signal line is smaller than that at the other portions, the gate insulating film for maintaining the insulation from the scanning line is formed. If set as before, it is possible to reduce defects such as a short circuit between the scanning line and the signal line and a disconnection of the scanning line.

Next, a silicon nitride film to be a passivation film 7 is formed to a thickness of 300 nm by a plasma CVD method or the like, and thereafter, the passivation film for contacting a scanning line, a signal line and a drain electrode is formed by photolithography. A hole is formed by a lithography process and etching (FIG. 6D).

Finally, an ITO film is formed as a conductive film, and a photolithography process and etching are performed.
By processing as the pixel electrode 8, a thin film transistor array substrate is completed (FIG. 6E).

In the present embodiment, the MoW alloy is used as the metal film for the scanning lines, the signal lines, and the drain electrodes. However, the present invention is not limited to this material.
A single-layer film or a laminated film of 1, Ta, Cr and their alloys may be used. Further, the other conductive films, semiconductor films, and insulating films are not limited to the materials described in this embodiment, and may be films that fulfill these functions. Also, their film thicknesses may be set in the same range as in the prior art.

(Embodiment 3) The present embodiment relates to a liquid crystal display device of the present invention.

FIG. 9 is a schematic view of a liquid crystal display device according to a third embodiment of the present invention. FIG. 10 is an equivalent circuit of a liquid crystal display device according to a third embodiment of the present invention. After a thin film transistor array substrate was manufactured using the method described in Embodiment Mode 1 or 2, an alignment film was applied thereon, and rubbing treatment was performed. FIG. 9 illustrates an example in which a thin film transistor array substrate is manufactured by the method described in Embodiment 1. Then, an alignment film was similarly applied to the counter substrate 11 on which the counter electrode 13 and the color filter 12 were formed, and an alignment process was performed by rubbing. The two substrates are attached to each other, a liquid crystal 14 is injected between the substrates, and a polarizing plate 15 is disposed before and after the substrates. Then, a liquid crystal display device is completed by connecting a drive circuit 17 for driving each switching transistor.

By driving the pixels of the liquid crystal display by the thin film transistor array substrate of the present invention,
Since defects such as short-circuit and disconnection of wirings and switching transistors are reduced, display defects such as point defects and line defects are reduced.

(Embodiment 4) The present embodiment relates to the electroluminescent display device of the present invention.

FIG. 11 is a schematic view of an electroluminescent display device according to a fourth embodiment of the present invention. FIG. 12 is an equivalent circuit of an electroluminescent display device according to a fourth embodiment of the present invention. After manufacturing a thin film transistor array substrate using a polycrystalline silicon film as an active layer by using the method described in Embodiment 1 or 2,
On the pixel electrode, for example, polyethylenedioxythiophene (PEDT) and a polydialkylfluorene derivative that actually emits light are formed as the conductive polymer 23, and finally a Ca cathode 25 is deposited to complete the electroluminescent display device. The operation is as follows. First, when a display signal is applied to the signal line 19 when a pulse signal is applied to the scanning line 18 so that the switching transistor is turned on, the driving transistor 27 is turned on, and current flows from the current supply line 28, The electroluminescent cell emits light.

In this embodiment, a polydialkylfluorene derivative is used as the electroluminescent material. However, another organic material, for example, another polyfluorene-based material, polyphenylvinylene-based material, or an inorganic material may be used. As a method for forming the electroluminescent material, a method such as coating, vapor deposition, or ink jet may be used.

By driving the pixels of the electroluminescence display device by the thin film transistor array substrate of the present invention, defects such as short-circuiting and disconnection of wirings and switching transistors are reduced, and display defects such as point defects and line defects are reduced. Reduced.

[0063]

According to the structure of the thin film transistor array substrate of the present invention, defects such as short-circuiting between wires and disconnection are reduced as compared with the prior art. Further, since the thickness of the gate insulating film can be reduced, characteristics and productivity of the thin film transistor array substrate are improved. Therefore, the practical effect of the present invention is great.

According to the method of manufacturing a thin film transistor array substrate of the present invention, it is possible to reduce defects such as short-circuiting between wires and disconnection without increasing the number of manufacturing steps. And the practical effect is great.

Further, according to the liquid crystal display device of the present invention, display defects due to short-circuiting or disconnection of wirings and transistors are reduced, and the practical effect is great.

Further, according to the electroluminescent display device of the present invention, display defects due to short-circuiting or disconnection of wirings and transistors are reduced, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 3 is a schematic diagram of a manufacturing process of the thin film transistor array substrate according to the first embodiment of the present invention.

FIG. 4 is a schematic plan view of a thin film transistor array substrate according to a second embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a thin film transistor array substrate according to a second embodiment of the present invention.

FIG. 6 is a schematic view illustrating a manufacturing process of a thin film transistor array substrate according to a second embodiment of the present invention.

FIG. 7 is a schematic plan view of a conventional thin film transistor array substrate.

FIG. 8 is a schematic diagram of a manufacturing process of a conventional thin film transistor array substrate.

FIG. 9 is a schematic diagram of a liquid crystal display device of the present invention.

FIG. 10 is a diagram showing an equivalent circuit of the liquid crystal display device of the present invention.

FIG. 11 is a schematic diagram of an electroluminescent display device according to the present invention.

FIG. 12 is a diagram showing an equivalent circuit of the electroluminescent display device of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 scanning line 2 gate insulating film 3 active layer 4 contact layer 5 signal line 6 drain electrode 7 passivation film 8 pixel electrode 9 gate electrode unit 10 storage capacitor electrode unit 11 counter substrate 12 color filter 13 counter electrode 14 liquid crystal 15 polarizing plate 16 back Light 17 Drive circuit 18 Scan line 19 Signal line 20 Switching transistor 21 Liquid crystal cell 22 Storage capacitor 23 Conductive polymer 24 Polyfluorene derivative 25 Ca cathode 26 Electroluminescence cell 27 Driving transistor 28 Current supply line

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) H01L 21/768 H01L 21/90 W 29/78 612C F term (reference) 2H092 JA25 JA26 JA28 JA38 JA42 JA44 JB13 JB23 JB32. 5F110 AA01 AA03 AA26 BB02 CC01 CC07 DD02 EE03 EE04 EE06 EE14 EE25 EE37 EE44 FF03 FF30 GG02 GG15 GG24 GG45 HK03 HK04 HK06 HK09 HK16 HK21 HK35 HL07 NN04 NN24 NN35 NN72

Claims (18)

[Claims] 1. A scanning line, a signal line intersecting with the scanning line, and a gate electrode disposed at a portion where the scanning line intersects with the signal line and connected to the scanning line on a substrate having an insulating surface. A thin film transistor having a source electrode and a drain electrode connected to a gate insulating film, a semiconductor film, and a signal line; and a thin film transistor array substrate having a pixel electrode connected to a drain electrode of the thin film transistor. At least 2 scan lines
A thin film transistor array substrate having two film thicknesses, wherein at least a portion of the scanning line corresponding to a channel portion of the thin film transistor is thinner than other portions. 2. A scanning line, a signal line intersecting with the scanning line, and a gate electrode arranged at a portion where the scanning line intersects with the signal line and connected to the scanning line on a substrate having an insulating surface. A thin film transistor including a source electrode and a drain electrode connected to a gate insulating film, a semiconductor film, and a signal line; a pixel electrode connected to a drain electrode of the thin film transistor; In a thin film transistor array substrate including a part of a storage capacitor, a scan line serving also as a gate electrode and a storage capacitor electrode has at least two film thicknesses, and a film thickness of at least a portion of the scan line corresponding to the storage capacitor electrode. However, a thin film transistor array substrate characterized by being thinner than other parts. 3. The semiconductor device according to claim 1, wherein the scanning line serving also as the gate electrode has at least two film thicknesses, and that at least a portion of the scanning line corresponding to a channel portion of the thin film transistor is thinner than other portions. 3. The thin film transistor array substrate according to claim 2, wherein: 4. A scanning line disposed on a substrate having an insulating surface, a scanning line, a signal line intersecting at least with an insulating film on the scanning line, and a portion where the scanning line intersects with the signal line. A thin film transistor including a gate electrode connected to a line, a gate insulating film, a semiconductor film, and a source electrode and a drain electrode connected to a signal line; and a thin film transistor array substrate including a pixel electrode connected to a drain electrode of the thin film transistor. Wherein the scanning line has at least two film thicknesses, and a film thickness of at least a portion of the scanning line intersecting the signal line is thinner than other portions. 5. The semiconductor device according to claim 1, wherein the scanning line serving also as the gate electrode has at least two film thicknesses, and that at least a portion of the scanning line corresponding to a channel portion of the thin film transistor is thinner than other portions. The thin film transistor array substrate according to claim 4, wherein 6. A scanning line having a storage capacitor in which a part of the scanning line is at least part of an electrode on one side, wherein the scanning line serving also as a gate electrode and a storage capacitor electrode has at least two film thicknesses. 6. The thin film transistor array substrate according to claim 4, wherein at least a portion of the line corresponding to the storage capacitor electrode has a smaller film thickness than other portions. 7. A semiconductor device comprising: a step of forming a scan line having a gate electrode over a substrate having an insulating surface; a step of forming a gate insulating film; a step of forming a semiconductor film; and a source electrode or a drain electrode. A method of manufacturing a thin film transistor array substrate including at least a step of forming a signal line, wherein the step of forming a scan line having the gate electrode includes the steps of: forming a metal film on a substrate having an insulating surface; A thin film transistor comprising: a step of forming a resist pattern having at least two thicknesses thereon; and a step of forming a metal film pattern having at least two thicknesses by etching using the resist pattern as a mask. An array substrate manufacturing method. 8. A scanning circuit which is arranged on a substrate having an insulating surface, a signal line, a scanning line intersecting at least with an insulating film on the signal line, and a portion where the signal line intersects with the scanning line. A thin film transistor including a gate electrode connected to a line, a gate insulating film, a semiconductor film, and a source electrode and a drain electrode connected to a signal line; and a thin film transistor array substrate including a pixel electrode connected to a drain electrode of the thin film transistor. A thin film transistor array substrate, wherein the signal line has at least two film thicknesses, and at least a portion of the signal line intersecting the scanning line is thinner than other portions. 9. A scanning device which is arranged on a substrate having an insulating surface, a signal line, a scanning line crossing over the signal line at least via an insulating film, and a portion where the signal line intersects with the scanning line. A thin film transistor including a gate electrode connected to a line, a gate insulating film, a semiconductor film, and a source electrode and a drain electrode connected to a signal line; and a thin film transistor array substrate including a pixel electrode connected to a drain electrode of the thin film transistor. A signal line having a source electrode has at least two film thicknesses, and a film thickness of at least the signal line at a contact portion of a source electrode with the thin film transistor is smaller than other portions. . 10. The signal line according to claim 9, wherein the signal line has at least two film thicknesses, and the film thickness of at least a portion of the signal line intersecting the scanning line is smaller than other portions. Thin film transistor array substrate. 11. A method comprising: forming a scan line having a gate electrode on a substrate having an insulating surface; forming a gate insulating film; forming a semiconductor film; and forming a source electrode or a drain electrode. Forming a signal line including a source electrode or a drain electrode, wherein a step of forming a conductive film on a substrate having an insulating surface, At least two layers on the conductive film
Forming a resist pattern having two thicknesses,
A method of manufacturing a thin film transistor array substrate, comprising at least a step of forming a conductive film pattern having at least two thicknesses by etching using the resist pattern as a mask. 12. The semiconductor device according to claim 11, wherein said conductive film comprises a laminated film of a semiconductor film doped with impurities and a metal film.
3. The method for manufacturing a thin film transistor array substrate according to item 1. 13. The photolithography step of transferring a mask pattern of a reticle having a light transmitting part, a semi-light transmitting part, and a light shielding part onto a resist, wherein the resist pattern is formed. 13. A method for manufacturing a thin film transistor array substrate according to claim 12. 14. The method according to claim 13, wherein the semi-light-transmitting portion of the reticle is formed of a light-shielding pattern having a size smaller than a resolution limit. 15. The thin film transistor array substrate according to claim 1, wherein said substrate is a translucent substrate. 16. The method according to claim 7, wherein the substrate is a light-transmitting substrate. 17. A liquid crystal display device, wherein pixels are driven by the thin film transistor array substrate according to any one of claims 1 to 6 or 8 to 10 or 15. 18. An electroluminescence display device, wherein pixels are driven by the thin film transistor array substrate according to any one of claims 1 to 6 or 8 to 10 or 15.