CN113889489A - Array substrate, preparation method thereof and display device - Google Patents
Array substrate, preparation method thereof and display device Download PDFInfo
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- CN113889489A CN113889489A CN202111176523.8A CN202111176523A CN113889489A CN 113889489 A CN113889489 A CN 113889489A CN 202111176523 A CN202111176523 A CN 202111176523A CN 113889489 A CN113889489 A CN 113889489A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract
The invention discloses an array substrate, a preparation method thereof and a display device, wherein the preparation method comprises the following steps: sequentially forming a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer on a substrate, wherein the gate structure layer comprises a gate and a gate line which are arranged on the same layer; sequentially forming a first semiconductor material layer and a light resistance pattern on one side of the interlayer insulating layer, which is far away from the substrate, wherein the light resistance pattern corresponds to a source electrode, a drain electrode and a data line to be formed; etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line; forming a flat layer, a pixel defining layer and a light-emitting device layer in sequence on the source electrode, the drain electrode and one side of the data line far away from the substrate; the side of the grid line back to the substrate is provided with a groove, an overlap area is formed between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlap area is positioned in the orthographic projection area of the groove on the substrate.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method thereof and a display device.
Background
In a display device, especially in an LTPS (Low Temperature polysilicon) product, it is inevitable that there are crossing metal driving traces (such as Gate lines and data lines) in each area, wherein a Top Gate (Top Gate) structure is a key direction for development.
In the existing Top Gate structure, a Gate insulating layer (GI) covers a Gate metal layer (Gate) including a Gate and a Gate line, so that the influence of a short channel effect is reduced, the portion of the GI edge which is more than the Gate edge is a Gate insulating layer Tail (GI Tail), when a subsequent interlayer dielectric layer (ILD) is formed, two times of climbing (GI slope and Gate slope) need to be continuously completed on the ILD at the GI Tail position, the wrinkling phenomenon is easy to occur, a similar tip phenomenon is formed at the climbing position after a source and drain metal layer is deposited, the ILD thickness at the climbing position is thinner, and in addition, the overetching of the ILD is easy to occur when a data line on the same layer as the source and drain metal layer is formed. If the electrostatic effect occurs, a Data-Gate Short (DGS) is easily generated at the position where the metal wires cross, thereby reducing the yield of the display panel process.
Disclosure of Invention
In view of the above-mentioned defects or shortcomings in the prior art, it is desirable to provide an array substrate, a method for manufacturing the same, and a display device.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
the base plate just keep away from one side of base plate be equipped with in proper order in the direction of base plate: the low-temperature polycrystalline silicon light-emitting diode comprises a low-temperature polycrystalline silicon active layer, a gate insulating layer, a gate structure layer, an interlayer insulating layer, a source drain structure layer, a flat layer, a pixel defining layer and a light-emitting device layer;
the grid structure layer comprises a grid and a grid line which are arranged on the same layer, the source drain structure layer comprises a source electrode, a drain electrode and a data line which are arranged on the same layer, a groove is formed on one side of the grid line, which is back to the substrate, an overlapping area is formed between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is positioned in the orthographic projection area of the groove on the substrate.
Optionally, in the extending direction of the gate line, the width of the groove is at least 1um greater than the width of the overlapping region.
Optionally, the gate line includes a first portion and a second portion other than the first portion, an orthographic projection of the first portion on the substrate coincides with an orthographic projection of the groove on the substrate, wherein,
the thickness of the second part is 0.25 um-0.3 um; and/or the presence of a gas in the gas,
the thickness of the first part is 1/2-2/3 of the thickness of the second part.
In a second aspect, an embodiment of the invention provides a display device, including the array substrate.
In a third aspect, an embodiment of the present invention provides a method for manufacturing an array substrate, including:
sequentially forming a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer on a substrate, wherein the gate structure layer comprises a gate and a gate line which are arranged on the same layer;
sequentially forming a first semiconductor material layer and a light resistance pattern on one side of the interlayer insulating layer, which is far away from the substrate, wherein the light resistance pattern corresponds to a source electrode, a drain electrode and a data line to be formed;
etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line;
forming a flat layer, a pixel defining layer and a light-emitting device layer in sequence on the source electrode, the drain electrode and one side of the data line far away from the substrate; wherein,
a groove is formed in one side, back to the substrate, of the grid line, an overlapping area is formed between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is located in the orthographic projection area of the groove on the substrate.
Optionally, the forming a gate structure layer on a side of the gate insulating layer away from the substrate includes:
forming a second semiconductor material layer on one side of the gate insulating layer, which is far away from the substrate;
coating photoresist on the second semiconductor material layer to form a first photoresist layer;
masking, exposing and developing the first photoresist layer by using a first halftone mask plate or a first gray tone mask plate to form a first fully exposed area, a first partially exposed area and a first unexposed area;
carrying out one-time wet etching to etch away part of the thickness of the second semiconductor material layer in the first fully exposed area;
ashing the photoresist in the first part exposure area, and removing the photoresist in the first part exposure area;
performing secondary wet etching to etch the remaining second semiconductor material layer in the first fully exposed region and the second semiconductor material layer with partial thickness in the first partially exposed region;
stripping the photoresist in the first unexposed area to form the grid and the grid line; wherein,
an orthographic projection of the first partially exposed region on the substrate coincides with an orthographic projection of the groove on the substrate.
Further, in the extending direction of the grid line, the width of the first part exposure area is at least 1um larger than the width of the overlapping area.
Further, before the wet etching is carried out for one time, the thickness of the photoresist in the first part exposure area is 0.4 um-0.6 um.
Further, the gate line includes a first portion facing the groove and a second portion outside the first portion, wherein
The thickness of the second part is 0.25 um-0.3 um; and/or the presence of a gas in the gas,
the thickness of the first part is 1/2-2/3 of the thickness of the second part.
Optionally, forming the photoresist pattern comprises:
coating photoresist on the first semiconductor material layer to form a second photoresist layer;
after a second half-tone mask plate or a second gray-tone mask plate is used for masking, exposing and developing a second photoresist layer, a photoresist pattern with a second completely exposed area, a second partially exposed area and a second unexposed area is formed, the second unexposed area is provided with a middle photoresist area, and the orthographic projection of the middle photoresist area on the substrate is superposed with the orthographic projection of the data line on the substrate;
the number of the second partially exposed areas is two; in the extending direction of the grid line, the two second partial exposure regions are symmetrically and closely distributed on two sides of the middle light resistance region.
Further, the thickness of the photoresist in the second part exposure area is 0.04 um-0.05 um.
Further, the width of the second part exposure area is 1um to 2 um.
In a second aspect, an embodiment of the present invention provides an array substrate, where the array substrate is prepared by using the preparation method described above.
In a third aspect, an embodiment of the present invention provides a display device, including the array substrate as described above.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
according to the array substrate and the preparation method thereof provided by the embodiment of the invention, the grid line with the groove is formed before the interlayer insulating layer is formed, and the orthographic projection of the intersection part between the data line and the grid line on the substrate falls in the orthographic projection of the groove on the substrate, namely, the thickness of the grid line in the overlapping area of the grid line and the data line is reduced, so that the climbing profile of the interlayer insulating layer is smoother; and forming a light resistance pattern corresponding to a source electrode, a drain electrode and a data line to be formed on the first semiconductor material layer, carrying out dry etching on the light resistance pattern and the first semiconductor material layer to form the source electrode, the drain electrode and the data line, and reducing over-etching of the interlayer insulating layer through the light resistance pattern, thereby effectively reducing the DGS risk and improving the yield of the array substrate.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:
fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;
fig. 2 to 14 are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the invention;
fig. 15 to 17 are schematic views illustrating a process of forming a low temperature polysilicon active layer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. It should be noted that, for convenience of description, only the portions related to the present invention are shown in the drawings.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
The embodiment of the invention provides a preparation method of an array substrate, which comprises the following steps:
sequentially forming an LTPS active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer on a substrate, wherein the gate structure layer comprises a gate and a gate line which are arranged on the same layer; sequentially forming a first semiconductor material layer and a light resistance pattern on one side of the interlayer insulating layer, which is far away from the substrate, wherein the light resistance pattern corresponds to a source electrode, a drain electrode and a data line to be formed;
etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line;
forming a flat layer, a pixel defining layer and a light-emitting device layer in sequence on the source electrode, the drain electrode and one side of the data line far away from the substrate; wherein,
a groove is formed in one side, back to the substrate, of the grid line, a superposition area is formed between orthographic projection of the grid line on the substrate and orthographic projection of the data line on the substrate, and the superposition area is located in the orthographic projection area of the groove on the substrate.
In this embodiment, the gate line includes a first portion facing the groove and a second portion other than the first portion, wherein the second portion has the same thickness as the gate electrode, and the first portion has a thickness smaller than that of the second portion.
On one hand, the overlapping area falls in the orthographic projection of the groove (or the first part) on the substrate, so that the thickness of the grid line in the crossing area of the grid line and the data line is effectively reduced, and the climbing profile of the interlayer insulating layer is relatively smooth; on the other hand, a photoresist pattern corresponding to a source electrode, a drain electrode and a data line to be formed is formed on the first semiconductor material layer, the photoresist pattern and the first semiconductor material layer are subjected to dry etching to form the source electrode, the drain electrode and the data line, and overetching of the interlayer insulating layer is reduced through the photoresist pattern. The DGS risk is effectively reduced, and the yield of array substrate manufacturing is improved.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention. As shown in fig. 1, in the array substrate, gate lines 1 and data lines 2 are distributed criss-cross, the gate lines 1 extend along a first direction, the data lines 2 extend along a second direction, an overlap region 3 is formed between an orthographic projection of the gate lines 1 on the substrate and an orthographic projection of the data lines 2 on the substrate, the array substrate is provided with a plurality of overlap regions 3, a plurality of gate lines 1 of the array substrate are provided with a plurality of first portions 171, and the first portions 171 correspond to the overlap regions 3 one to one.
A method for manufacturing an array substrate according to the above embodiment is described below with reference to fig. 2 to 17, and includes the following steps:
(1) as shown in fig. 2, a buffer layer 10 is deposited on a substrate (not shown) to serve as a barrier layer and a planarization layer. The buffer layer 10 may be a SiOx film layer or a SiNx film layer, or may be stacked and deposited by using the two film layers at the same time, which may have better barrier layer and planarization effects.
(2) Referring to fig. 2, 15 to 17, an LTPS active layer 11 is formed on the buffer layer 10.
Depositing an amorphous silicon layer on the buffer layer 10 by using a chemical vapor deposition (PECVD) method, and performing dehydrogenation process treatment on the amorphous silicon layer to prevent hydrogen explosion in the crystallization process;
after the dehydrogenation process is finished, performing an LTPS process to perform polycrystallization treatment on the amorphous silicon layer, and generally adopting a laser annealing process (ELA) to form a polycrystalline silicon layer;
coating a layer of photoresist on the polysilicon layer, exposing and imaging the photoresist by using a single-tone mask plate to form a fully exposed part and an unexposed part, etching the fully exposed part, and stripping the photoresist of the unexposed part to form a polysilicon pattern 12, as shown in fig. 15;
on the substrate on which the polysilicon pattern 12 is formed, the LTPS active layer 11 including the heavily doped region 111, the lightly doped region 112, and the undoped region 113 is formed through a half-tone mask process or a gray-tone mask process. Forming the LTPS active layer 11 includes:
a photoresist is coated on the substrate on which the polysilicon pattern 12 is formed. Exposing and developing the photoresist through a half-tone mask process or a gray-tone mask process to form a third fully exposed region a1, a third partially exposed region a2, and a third unexposed region A3, the third unexposed region A3 having a first thickness of the photoresist and the third partially exposed region a2 having a second thickness of the photoresist, the first thickness being greater than the second thickness, as shown in fig. 16;
performing a first ion implantation process on the third fully exposed region a3 by using an ion implantation method to form heavily doped regions 111 on both sides of the polysilicon pattern 12, as shown in fig. 16, preferably, the first ion implantation is N-type ion implantation, and the N-type ions may be phosphorus ions;
then, through photoresist ashing treatment, the photoresist is entirely removed by a second thickness, that is, the photoresist in the third part exposed region a2 is removed to expose the lightly doped region 112, and the photoresist thickness in the third unexposed region A3 is reduced;
performing a second ion implantation process on the polysilicon pattern 12 in the third fully exposed region A3 and the third partially exposed region a2 by using an ion implantation method to form a lightly doped region 112 between the heavily doped region 111 and an undoped region 113, wherein the ion concentration of the lightly doped region 112 is less than that of the heavily doped region 111, and the undoped region 113 is a channel region of a Thin Film Transistor (TFT), as shown in fig. 17, preferably, the second ion implantation is an N-type ion implantation, and the N-type ion may be a phosphorus ion;
the photoresist remaining in the third unexposed region a3 is stripped off to form the LTPS active layer 11, and the LTPS active layer 11 includes an undoped region 113 located in the middle, heavily doped regions 111 located at both sides, and a lightly doped region 112 located between the undoped region 113 and the heavily doped regions 111.
In order to form good electrical connection between the source and drain electrodes and the LTPS active layer 11, the heavily doped region 111 is formed by heavily doping the source and drain region of the LTPS active layer 11 by using an ion implantation process, and the source and drain electrodes are connected with the heavily doped region 111 of the LTPS active layer 11, so that contact resistance is reduced, and good electrical characteristics of the TFT can be obtained. Meanwhile, considering that the semiconductor region is shorter and shorter, the short channel effect is more obvious, and the short channel effect causes the abnormal characteristics of the TFT, such as larger cutoff voltage Vth, higher leakage current Ioff, and the like, in order to avoid such abnormal characteristics, a lightly doped region 112 is added between the heavily doped region and the undoped region 113, which is equivalent to connecting a resistor in series between the source and drain and the channel, so that the horizontal electric field of the channel is reduced, and the leakage current is suppressed. Moreover, only one patterning process using a halftone mask or a gray tone mask is required to form the heavily doped region 111 and the lightly doped region 112, thereby simplifying the process steps.
(3) A gate insulating layer 14 is formed on the LTPS active layer 11.
Depositing a gate insulating layer 14 on the LTPS active layer 11 by a PECVD method, wherein the gate insulating layer 14 can be a composite SiOx/SiNx film, for example, a SiOx film is deposited first, and the SiOx thickness is 0.03-0.06 um; and depositing a SiNx film layer, wherein the thickness of the SiNx film layer is 0.05-0.09 um.
(4) A gate structure layer is formed on the gate insulating layer 14.
Forming a second semiconductor material layer 15 on the side of the gate insulating layer 14 away from the substrate by using a magnetron sputtering device (sutter), wherein the material of the second semiconductor material layer may be Al, Mo, composite Al/Mo, or the like;
coating photoresist on the second semiconductor material layer 15 to form a first photoresist layer 16, referring to fig. 2;
referring to fig. 3 and 5, after the first photoresist layer 16 is masked, exposed and developed by the first half-tone mask plate 18, a first fully exposed region B1, a first partially exposed region B2 and a first unexposed region B3 are formed;
referring to fig. 6, a wet etching process is performed to etch away a portion of the thickness of the second semiconductor material layer in the first fully exposed regions B1;
referring to fig. 7, the photoresist in the first partially exposed region B2 is ashed to remove the photoresist in the first partially exposed region B2;
performing a second wet etching to etch away the remaining second semiconductor material layer in the first fully exposed region B1 and a portion of the thickness of the second semiconductor material layer in the first partially exposed region B2;
stripping the photoresist in the first unexposed region B3 to form a gate electrode 4 and a gate line 1, see fig. 8; wherein,
the gate line 1 includes a first portion 171 and a second portion 172, an orthogonal projection of the first portion exposed region B2 on the substrate coincides with an orthogonal projection of the first portion 171 on the substrate, the second portion 172 and the gate electrode 4 face the first unexposed region B3, a thickness of the second portion 172 is the same as a thickness of the gate electrode 4, and a thickness of the first portion 171 is smaller than a thickness of the second portion 172, that is, the gate line 1 has a plurality of groove structures.
Further, the width of the first partially exposed region B2 is at least 1um greater than the width of the recombination region 3 in the first direction (i.e., the extending direction of the gate line). The data lines 2 and the gate lines 1 are arranged to cross each other, thus ensuring that the data lines 2 fall within the thinned first portions 171 of the gate lines 1.
Further, before the wet etching is performed, the thickness of the photoresist in the first partially exposed region B2 is 0.4um to 0.6um, so as to ensure that the second semiconductor material layer 15 opposite to the first partially exposed region B2 is not etched when the wet etching is performed.
Further, the thickness of the second portion 172 is 0.25um to 0.3 um; and/or the presence of a gas in the gas,
the thickness of the first portion 171 is 1/2-2/3 of the thickness of the second portion 172.
Generally, it is preferable that the thickness of the first portion 171 is 1/2 the thickness of the second portion 172, and it is more convenient to control the thickness of the first portion 171 by controlling the time of the wet etching.
Compared with the prior art in which a gate line having the same thickness as the gate electrode is disposed, in the embodiment, the thickness of the first portion 171 where the gate line 1 and the data line 2 intersect is smaller than the thickness of the second portion 172, that is, the gate line 1 has the groove structure, so that the thickness of the interlayer insulating layer 21 at the overlapping region of the gate line 1 and the data line 2 can be increased.
Referring to fig. 3, the first half-tone mask plate 18 performs an exposure process on the first photoresist layer 16, and the first half-tone mask plate 18 includes first transparent regions 181, first translucent regions 182, and first opaque regions 183. The photoresist 19 is in the exposed state of the first photoresist layer 16, wherein the region 191 corresponds to the first transparent region 181, the region 192 corresponds to the first translucent region 182, and the region 193 corresponds to the first opaque region 183. The photoresist 20 is in a state where the photoresist 19 is developed, wherein the first fully exposed region B1 corresponds to the first transparent region 181, the first partially exposed region B2 corresponds to the first translucent region 182, and the first unexposed region B3 corresponds to the first opaque region 183.
The first fully exposed region B1, the first partially exposed region B2, and the first unexposed region B3 may also be formed in this embodiment after the first photoresist layer 16 is masked, exposed, and developed using a gray tone masking process. The gray tone mask plate makes the mask have different light intensities in different areas through a grating effect, so that the photoresist is selectively exposed and developed.
Referring to fig. 4, the first photoresist layer 16 is exposed by a first gray-tone mask plate 18 ', and the first gray-tone mask plate 18 ' includes first transparent regions 181 ', first semi-transparent regions 182 ', and first opaque regions 183 '. The photoresist 19 ' is in a state after the first photoresist layer 16 is exposed, wherein the region 191 ' corresponds to the first transparent region 181 ', the region 192 ' corresponds to the first translucent region 182 ', and the region 193 ' corresponds to the first opaque region 183 '. The photoresist 20 ' is in a state where the photoresist 19 ' is developed, in which the first fully exposed region B1 corresponds to the first transparent region 181 ', the first partially exposed region B2 corresponds to the first translucent region 182 ', and the first unexposed region B3 corresponds to the first opaque region 183 '.
In this embodiment, the first fully exposed region B1, the first partially exposed region B2, and the first unexposed region B3 are formed only by a one-step patterning process using a halftone mask or a gray-tone mask, simplifying the process steps.
(5) As shown in fig. 9, an interlayer insulating layer 21 is formed.
An interlayer insulating layer 21 is formed on one side, far away from the substrate, of the grid structure layer through PECVD (plasma enhanced chemical vapor deposition) to prevent short circuit between the grid structure layer and the source drain, the material of the interlayer insulating layer can be a composite SiOx/SiNx film layer, the SiOx/thickness is 0.2-0.5 um, and the SiNx thickness is 0.2-0.3 um.
Two via holes are formed on the interlayer insulating layer 21 and the gate insulating layer 14 through a patterning process (masking, exposing, developing) and a dry etching process, wherein the two via holes correspond to the heavily doped regions of the LTPS active layer 11, and the two via holes correspond to the source electrode 221 and the drain electrode 222 to be formed.
(6) As shown in fig. 10 to 12, the source electrode 221, the drain electrode 222, and the data line 2 are formed.
A first semiconductor material layer 22 is formed on one side of the interlayer insulating layer 21, which is far away from the substrate, the material can be titanium-aluminum-titanium (Ti-Al-Ti), and the film thickness is (300 um-600 um)/(4000 um-5000 um)/(300 um-600 um);
coating photoresist on the first semiconductor material layer 22 to form a second photoresist layer 23, referring to fig. 10;
as shown in fig. 11 and 12, after the second photoresist layer 23 is masked, exposed and developed by the second half-tone mask plate 24, a photoresist pattern 25 having a second fully exposed region C1, a second partially exposed region C2 and a second unexposed region C3 is formed, the second unexposed region C3 has an intermediate photoresist region C4, and the orthographic projection of the intermediate photoresist region C4 on the substrate coincides with the orthographic projection of the data line 2 on the substrate;
the number of second partially exposed areas C2 is two; in the first direction, two second partially exposed regions C2 are symmetrically disposed next to each other on both sides of the middle photoresist region C4.
The photoresist pattern 25 and the first semiconductor material layer 22 are dry-etched, for example, by plasma treatment using boron trichloride and chlorine gas, to form the source electrode 221, the drain electrode 222, and the data line 2.
In this embodiment, the second photoresist layer may be masked, exposed and developed by a second gray-tone mask (not shown) to form a photoresist pattern 25 having a second fully exposed region C1, a second partially exposed region C2 and a second unexposed region C3.
In this embodiment, the second fully exposed region C1, the second partially exposed region C2, and the second unexposed region C3 are formed only by a one-step patterning process using a halftone mask or a gray-tone mask, which simplifies the process steps.
Furthermore, the thickness of the photoresist in the second part exposure area is 0.04 um-0.05 um, and the width of the second part exposure area is 1 um-2 um. At grid line 1 and 2 overlap regions of data line, through the thin layer photoresistor that thickness is 0.04um ~ 0.05um, width are 1um ~ 2um in the second part exposure area, can effectively reduce the overetch to first semiconductor material layer 22, increase the thickness of overlap region department interlayer insulating layer 21 between grid line 1 and the data line 2, reduce the DGS risk.
(7) A planarization layer 26 is formed.
A planarization layer 26, which may be SiNx or an organic coating, is formed on the source electrode 221, the drain electrode 222, and the data line 2 at a side away from the substrate, and a planarization layer via hole exposing the source electrode 221 is formed on the planarization layer 26.
(8) An anode 27, a pixel defining layer 28, a light emitting device layer, and a cathode are formed.
Forming an anode 27 on the side of the planarization layer 25 away from the substrate, wherein the anode 27 is connected to the source 221 through the planarization layer via;
forming a pixel defining layer 28 on the side of the anode 27 away from the substrate, and forming an opening 29 exposing the anode 28 through dry etching;
forming a light emitting device layer (not shown) within the opening;
a cathode (not shown) is formed on the side of the light emitting device layer remote from the substrate and on the side of the pixel defining layer 28 remote from the substrate.
The embodiment of the invention also provides an array substrate, which is prepared by adopting the preparation method, so that an interlayer insulating layer between the grid line and the data line is not over-etched, the risk of DGS is reduced, and the yield of products is improved.
Referring to fig. 14, an embodiment of the present invention provides an array substrate, which includes a substrate, and on one side of the substrate and in a direction away from the substrate, in order: the structure comprises a low-temperature polysilicon active layer 11, a gate insulating layer 14, a gate structure layer, an interlayer insulating layer 21, a source-drain structure layer, a flat layer 26, a pixel defining layer 28 and a light-emitting device layer;
the grid structure layer comprises a grid 4 and a grid line 1 which are arranged on the same layer, the source-drain structure layer comprises a source electrode 221, a drain electrode 222 and a data line 2 which are arranged on the same layer, a groove is formed on one side of the grid line 1, which is back to the substrate, an overlapping area is formed between the orthographic projection of the grid line 1 on the substrate and the orthographic projection of the data line 2 on the substrate, and the overlapping area is positioned in the orthographic projection area of the groove on the substrate.
Because the cross part between the grid line and the data line falls in the groove of the grid line, when the interlayer insulating layer is formed, the thickness of the part of the interlayer insulating layer, which is opposite to the groove, is correspondingly increased, namely the thickness of the interlayer insulating layer between the part of the grid line, which is opposite to the data line, and the data line is increased, so that the interlayer insulating layer can be prevented from being over-etched in the forming process of the source drain structure layer, and the risk of DGS is avoided.
Further, in the extending direction of the gate line 1, the width of the groove is at least 1um larger than the width of the overlapping region. Thus, the data line is ensured to fall in the groove structure of the grid line.
Further, the gate line includes a first portion and a second portion other than the first portion, an orthogonal projection of the first portion on the substrate coincides with an orthogonal projection of the groove on the substrate, wherein,
the thickness of the second part is 0.25 um-0.3 um; and/or the presence of a gas in the gas,
the thickness of the first part is 1/2-2/3 of the thickness of the second part.
The thickness of the first part is preferably 1/2 of the thickness of the second part, and the thickness of the first part can be conveniently controlled by controlling the time of the wet etching.
In this embodiment, the thickness of the first portion where the gate line 1 and the data line 2 intersect is smaller than that of the second portion, that is, the groove structure of the gate line 1 can increase the thickness of the interlayer insulating layer 21 at the overlapping region of the gate line 1 and the data line 2.
The embodiment of the invention also provides a display device which comprises the array substrate. The display device may be: the display device comprises any product or component with a display function, such as a liquid crystal panel, electronic paper, an OLED panel, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
The present invention employs the terms first, second, etc. to describe various information, but the information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
The foregoing description is only exemplary of the preferred embodiments of the invention and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the inventive concept. For example, the above features and (but not limited to) features having similar functions disclosed in the present invention are mutually replaced to form the technical solution.
Claims (12)
1. An array substrate, comprising:
the base plate just keep away from one side of base plate be equipped with in proper order in the direction of base plate: the low-temperature polycrystalline silicon light-emitting diode comprises a low-temperature polycrystalline silicon active layer, a gate insulating layer, a gate structure layer, an interlayer insulating layer, a source drain structure layer, a flat layer, a pixel defining layer and a light-emitting device layer;
the grid structure layer comprises a grid and a grid line which are arranged on the same layer, the source drain structure layer comprises a source electrode, a drain electrode and a data line which are arranged on the same layer, a groove is formed on one side of the grid line, which is back to the substrate, an overlapping area is formed between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is positioned in the orthographic projection area of the groove on the substrate.
2. The array substrate of claim 1, wherein the width of the groove is at least 1um larger than the width of the overlapping region in the extending direction of the gate line.
3. The array substrate of claim 1 or 2, wherein the gate line comprises a first portion and a second portion other than the first portion, an orthographic projection of the first portion on the substrate is coincident with an orthographic projection of the groove on the substrate, wherein,
the thickness of the second part is 0.25 um-0.3 um; and/or the presence of a gas in the gas,
the thickness of the first part is 1/2-2/3 of the thickness of the second part.
4. A display device comprising the array substrate according to any one of claims 1 to 3.
5. A preparation method of an array substrate is characterized by comprising the following steps:
sequentially forming a low-temperature polysilicon active layer, a gate insulating layer, a gate structure layer and an interlayer insulating layer on a substrate, wherein the gate structure layer comprises a gate and a gate line which are arranged on the same layer;
sequentially forming a first semiconductor material layer and a light resistance pattern on one side of the interlayer insulating layer, which is far away from the substrate, wherein the light resistance pattern corresponds to a source electrode, a drain electrode and a data line to be formed;
etching the photoresist pattern and the first semiconductor material layer to form a source electrode, a drain electrode and a data line;
forming a flat layer, a pixel defining layer and a light-emitting device layer in sequence on the source electrode, the drain electrode and one side of the data line far away from the substrate; wherein,
a groove is formed in one side, back to the substrate, of the grid line, an overlapping area is formed between the orthographic projection of the grid line on the substrate and the orthographic projection of the data line on the substrate, and the overlapping area is located in the orthographic projection area of the groove on the substrate.
6. The method for manufacturing the array substrate according to claim 5, wherein the forming of the gate structure layer on the side of the gate insulating layer away from the substrate comprises:
forming a second semiconductor material layer on one side of the gate insulating layer, which is far away from the substrate;
coating photoresist on the second semiconductor material layer to form a first photoresist layer;
masking, exposing and developing the first photoresist layer by using a first halftone mask plate or a first gray tone mask plate to form a first fully exposed area, a first partially exposed area and a first unexposed area;
carrying out one-time wet etching to etch away part of the thickness of the second semiconductor material layer in the first fully exposed area;
ashing the photoresist in the first part exposure area, and removing the photoresist in the first part exposure area;
performing secondary wet etching to etch the remaining second semiconductor material layer in the first fully exposed region and the second semiconductor material layer with partial thickness in the first partially exposed region;
stripping the photoresist in the first unexposed area to form the grid and the grid line; wherein,
an orthographic projection of the first partially exposed region on the substrate coincides with an orthographic projection of the groove on the substrate.
7. The method of claim 6, wherein the width of the first partially exposed region is at least 1um greater than the width of the overlapping region in the extending direction of the gate line.
8. The method for preparing the array substrate of claim 6, wherein the photoresist in the first partially exposed region has a thickness of 0.4um to 0.6um before the wet etching is performed.
9. The method for preparing the array substrate of any one of claims 5 to 8, wherein the gate line comprises a first portion and a second portion outside the first portion, and an orthographic projection of the first portion on the substrate is coincident with an orthographic projection of the groove on the substrate, wherein
The thickness of the second part is 0.25 um-0.3 um; and/or the presence of a gas in the gas,
the thickness of the first part is 1/2-2/3 of the thickness of the second part.
10. The method for preparing the array substrate according to claim 5, wherein the forming the photoresist pattern comprises:
coating photoresist on the first semiconductor material layer to form a second photoresist layer;
after a second half-tone mask plate or a second gray-tone mask plate is used for masking, exposing and developing a second photoresist layer, a photoresist pattern with a second completely exposed area, a second partially exposed area and a second unexposed area is formed, the second unexposed area is provided with a middle photoresist area, and the orthographic projection of the middle photoresist area on the substrate is superposed with the orthographic projection of the data line on the substrate;
the number of the second partially exposed areas is two; in the extending direction of the grid line, the two second partial exposure regions are symmetrically and closely distributed on two sides of the middle light resistance region.
11. The method of claim 10, wherein the photoresist in the second partially exposed region has a thickness of 0.04um to 0.05 um.
12. The method of claim 10, wherein the width of the second partially exposed region is 1um to 2 um.
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