JP2002057316A5 - - Google Patents

Description

Patent application title: Solid-state imaging device

[0001]
Field of the Invention
The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device using a threshold voltage modulation type MOS type image sensor used for a video camera, an electronic camera, an image input camera, a scanner or a facsimile.

[0005]
[Problems to be solved by the invention]
However, in the structure of the solid-state imaging device, the structure of the element separation region and the structure of the field effect transistor for detecting an optical signal are not suitable for miniaturization, and are required as the definition of the image in the future becomes high. There is a problem that it is difficult to cope with the growing demand for miniaturization of unit pixels.

[0006]
The present invention has been made in view of the above-described conventional problems, and provides a solid-state imaging device having a structure suitable for miniaturization of a unit pixel.

[0009]
In the light receiving diode, an impurity region of the opposite conductivity type is formed on the surface of the first well region of one conductivity type, the impurity region is connected to the drain region of the opposite conductivity type, and an element isolation region of the opposite conductivity type. It is characterized by being connected.
In addition, the first and second well regions of one conductivity type are formed in the semiconductor layer of the opposite conductivity type, and the semiconductor layer of the opposite conductivity type is connected to the element isolation region of the opposite conductivity type. There is.
In addition, an impurity layer of the opposite conductivity type is formed in the surface layer of the second well region under the gate electrode to form a channel region.
Also, a plurality of unit pixels are arranged in rows and columns. For example, in the planar arrangement of unit pixels in a solid-state imaging device, the direction from the gate electrode to the light receiving diode in the unit pixel is the row direction or It can be made to match in the diagonal direction or parallel direction to the column direction. Furthermore, the gate electrodes of the insulated gate field effect transistors in the same row can be connected to each other, and the source regions of the insulated gate field effect transistors in the same column can be connected to each other.

[0010]
Below, the effect | action exhibited by the said structure is demonstrated.
By the way, according to the formation of the insulating film by the selective oxidation method (LOCOS method), the formation region of the isolation insulating film spreads over the mask width by the formation of bird's beak, which is disadvantageous for miniaturization.
In the present invention, the isolation region separating adjacent unit pixels 101 has the same conductivity type as the drain region 57a and is formed deeper than the well regions 54a and 54b, so that the isolation region is the drain region 57a. And are connected to the regions 52a and 52b of the same conductivity type as the drain regions under the well regions 54a and 54b. That is, since the element isolation is performed only in the diffusion isolation region 53 without using the isolation insulating film by the LOCOS method, no bird's beak is generated and the element isolation region does not expand beyond the mask width. Thereby, the unit pixel 101 can be miniaturized. In this case, the drain region 57a is connected to the regions 52a and 52b of the same conductivity type as the drain region under the well regions 54a and 54b, and between adjacent unit pixels 101, but no problem occurs in the operation of the solid-state imaging device . In the unit pixel 101, since the source region 56 and the drain region 57a are separated by the ring-shaped gate electrode 59, no problem occurs.

[0013]
As shown in FIG. 1, in the unit pixel 101, the light receiving diode 111 and the light signal detecting MOS transistor 112 are provided adjacent to each other. As the MOS transistor 112, an n-channel MOS (nMOS) is used. The unit pixel 101 has a rectangular shape, and the unit pixel 101 is surrounded by an element isolation region in which the diffusion isolation region 53 is a series. That is, between the well regions where adjacent pixels are formed, the drain region is connected, and the diffusion separation region 53 of the same conductivity type as the drain region and the region 52a of the same conductivity type as the drain region under the well regions 54a and 54b. , 52b are configured and connected.

[0018]
The above components are covered with an insulating film 64 such as a silicon oxide film, and the region other than the light receiving window 63 of the light receiving diode 111 is a metal layer (light shielding film) 62 formed on the insulating film 64. It is shielded from light.
In the element operation for light signal detection in the MOS type image sensor described above, the accumulation period, the readout period, the initialization period (sweeping period), the noise voltage readout period, the accumulation period,... -Readout period-Initialization period (spouting period)-A series of processes of noise voltage readout period is repeated.

[0022]
The second source potential is stored in the second line memory in a state where the photogenerated charge is swept out from the carrier pocket using the noise voltage read period. Also in this period, a voltage similar to that in the above-described read period is applied to the light receiving diode 111 and the MOS transistor 112.

[0031]
The gate electrode 59 is formed on the second well region 54 b between the drain region 57 a and the source region 56 via the gate insulating film 58. The surface layer of the second well region 54b below the gate electrode 59 is a channel region. Further, in order to keep the channel region in the state of accumulation or depletion of electrons under a normal operating voltage, an n-type impurity of an appropriate concentration is introduced into the channel region to form the channel dope layer 54c.

[0034]
FIG. 2B shows a potential diagram in a state where the photogenerated holes are accumulated in the carrier pocket 55, and the electrons are induced in the channel region on the source side to generate the electron accumulation region. The threshold voltage of the MOS transistor 112 is changed by the accumulated charge. Therefore, detection of the light signal can be performed by detecting this change in threshold voltage.

[0051]
In this case, the present invention is applied to the case where the p-type first and second well regions 54a and 54b are used and the light signal detection MOS transistor 112 is an nMOS.
Next, the light detection operation of a series of continuous solid-state imaging devices will be briefly described according to FIG. As described above, the light detection operation repeats a series of processes consisting of accumulation period-readout period-initialization period (sweeping period) -noise voltage readout period. Here, for convenience, the explanation will start from the accumulation period.

[0056]
In the accumulation period, the voltage of the difference between the source potentials stored in the first and second line memories in the previous period is output to the video signal output terminal 107. Regarding this operation, after the noise voltage read period I will explain.
Next, in the period at the start of the reading period, the output (Vpg) of the VSCAN drive scanning circuit 102 is set to the set potential (becomes the gate potential of the MOS transistor 112). On the other hand, the VDD supply lines 61a, 61b,... Are maintained at about 3.3V.

[0057]
Next, in the period after the end of the period at the start of the read period, the output (Vpg) of the VSCAN drive scanning circuit 102 is approximately 2.2 V (becomes the gate potential of the MOS transistor 112). On the other hand, the VDD supply lines 61a, 61b,... Are maintained at approximately 3.3 V (the drain potential of the MOS transistor 112).
That is, a gate voltage (Vpg) of about 2.2 V at which MOS transistor 112 can operate in saturation is applied to gate electrode 59, and a voltage (Vpd) of about 3.3 V at which MOS transistor 112 can operate in drain region 57a. Apply. As a result, a low electric field electron accumulation region is formed in part of the channel region above the carrier pocket 55, and a high electric field region is formed in the remaining part of the channel region. At this time, the drain voltage-current characteristic of the MOS transistor 112 exhibits a saturation characteristic.

[0059]
At this time, the voltage applied to the gate electrode 59 is applied to the second well region 54b and the n-type layer 52b below the second well region 54b. The high electric field generated at this time allows the carriers to be reliably swept out of the second well region 54b.
After discharging the photogenerated charge stored in the carrier pocket 55, the output (Vpg) of the VSCAN drive scan circuit 102 is set to the ground potential (gate of the MOS transistor 112) in a period at the start of the noise voltage read period before the storage period. At the same time, the output (Vpd) of the VDD drive scan circuit 103 is 3.3 V (becomes the drain potential of the MOS transistor 112).

[0060]
Next, in a period after the end of the period at the start of the noise voltage read period, the output (Vpg) of the VSCAN drive scanning circuit 102 is approximately 2.2 V (becomes the gate potential of the MOS transistor 112). On the other hand, the VDD supply lines 61a, 61b,... Are maintained at about 3.3V.
As a result, a low electric field electron accumulation region is formed in part of the channel region above the carrier pocket 55, and a high electric field region is formed in the remaining part of the channel region. At this time, a drain current flows to the source of the MOS transistor 112, and the drain voltage-current characteristic exhibits a saturation characteristic in accordance with the threshold voltage. As a result, the second line memory is charged, and when the charging is completed, the noise voltage (VoutN) due to the residual charge not due to the photogenerated charge is stored in the second line memory.

[0062]
As described above, according to the third embodiment of the present invention, when a light generation hole moves in a series of processes of accumulation operation-read operation-initialization operation (spouting operation) -noise voltage read operation In addition, it is possible to realize an ideal photoelectric conversion mechanism which does not interact with the noise source in the semiconductor surface or the channel region.
As mentioned above, although this invention was explained in detail by the embodiment, the scope of this invention is not limited to the example concretely shown in the above-mentioned embodiment, and the above-mentioned execution of the range which does not deviate from the gist of this invention Modification of the form is included in the scope of the present invention.

[0063]
For example, in the above embodiment, in order to form an accumulation state of electrons in the channel region in the accumulation period, in particular, the pn junction formed by the drain region 57a, the source region 56, and the second well region 54b is reverse biased. As described above, voltages are applied to the drain region 57a and the source region 56, but in some cases, a ground voltage may be applied to the drain region 57a and the source region 56.

Claims (5)

A light receiving diode formed in a first well region of one conductivity type, and a conductive electrically connected adjacent to the first well region of the light receiving diode so as to be capable of storing photogenerated charges generated by the light receiving diode And a unit pixel having an insulated gate field effect transistor for light signal detection formed in a second well region of the die, and the portion of the insulated gate field effect transistor is a second well of the one conductivity type. A drain region and a source region of the opposite conductivity type provided in the region, a channel region between the drain region and the source region, and a gate electrode formed on the channel region via a gate insulating film. A high concentration buried type of one conductivity type provided in the second well region of the one conductivity type under the channel region, for accumulating the photogenerated charge generated by light irradiation with the light receiving diode Solid-state imaging device having a layer, the photogenerated charge is accumulated in the one conductivity type high concentration buried layer, and the threshold voltage of the channel region in the insulated gate field effect transistor is modulated to detect an optical signal A solid-state imaging device,
The gate electrode of the insulated gate field effect transistor has a ring shape, the source region is provided inside the inner peripheral portion of the gate electrode, and the train region is provided outside the outer periphery of the gate electrode, The solid-state imaging device according to claim 1, wherein the unit pixel is surrounded by an element isolation region in which a series of diffusion isolation regions having the same opposite conductivity type as the drain region is formed. In the light receiving diode, an impurity region of the opposite conductivity type is formed on the surface of the first well region of one conductivity type, the impurity region is connected to the drain region of the opposite conductivity type, and the element separation of the opposite conductivity type The solid-state imaging device according to claim 1, wherein the solid-state imaging device is connected to a region. The first conductivity type first and second well regions are formed in the semiconductor layer of the opposite conductivity type, and the semiconductor layer of the opposite conductivity type is connected to the element isolation region of the opposite conductivity type. The solid-state imaging device according to any one of claims 1 or 2. The solid-state imaging device according to any one of claims 1 to 3, wherein an impurity layer of the opposite conductivity type is formed in the surface layer of the second well region below the gate electrode to form a channel region. The solid-state imaging device according to any one of claims 1 to 4, wherein a plurality of the unit pixels are arranged in a row and a column.

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