JP2001169243A - Recorder and recording method, and reproducing device and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a digital VTR to be compatible with even a different image frame size of a digital video signal. SOLUTION: A frame detection section 300 detects a received head of a frame in compliance with the MPEG ES and a counter 301 is started. An H/V detection section 302 starts counting frames from the head of the frames and extracts horizontal (H) and vertical (V) size information from the MPEG ES frames. A dummy generating section 304 generates dummy data whose first 3-byte synchronous wards are the same as those of a macro block and whose 4th byte data are unique data with a signal INVAL outputted from an H/V detection section 302 that detects the H and V size information. A selector 306 selects the MPEG ES read from a memory 303 on the basis of the inverted signal inverse of INVAL or the dummy data from the dummy generating section 304 on the basis of the signal INVAL selectively and provides an output of the selected signal. Parts corresponding to the difference of the image frame size are filled by the dummy data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to compression encoding of a digital video signal, error correction encoding in units of blocks of a predetermined size, recording on a recording medium, and compression encoding in the recording medium in units of blocks of a predetermined size. The present invention relates to a recording apparatus and method for reproducing a digital video signal recorded by error correction coding, and a reproducing apparatus and method.

[0002]

2. Description of the Related Art Digital VTR (Video Tape Recorder)
As represented by r), there is known a data recording / reproducing apparatus which records a digital image signal and a digital audio signal on a recording medium and reproduces the data from the recording medium. In a recording processing unit of a digital image recording device, video and audio digital data are stored in packets of a predetermined length, ID information indicating data contents and an error correction code are encoded in packet units, and the packetized data is encoded. , A sync pattern is formed by adding a synchronization pattern and an ID to the parity of the error correction code. The sync blocks are grouped according to the type of data to form sectors, and serial data is recorded in units of sectors on a magnetic tape by a rotating head. Recording is performed on the magnetic tape with a helical track.

[0003] The sync blocks in the same sector have the same length, the ID numbers are consecutive, and the ID information has the same value. A product code is used as the error correction code.
That is, the outer code and the inner code are encoded in the vertical and horizontal directions of the two-dimensional array of data symbols, respectively, and each symbol is doubly encoded. One unit of encoding / decoding of the product code is called an ECC block. In the ECC block, for example, one row in the inner code direction in data symbol units corresponds to the above-described sync block.

On the reproducing side, the head position of each sync block is detected by a synchronization signal, and the packets in the block are rearranged according to the ID number and ID information. Since a unique synchronization pattern is added to the head position of the sync block, the bit sequence of the synchronization pattern, the pattern appearance cycle, and the fact that the ID number is continuous and the ID information is the same in the same sector are used. , The phase of the synchronization block can be specified. That is, when the bit sequence of the synchronization pattern matches the unique pattern, the same pattern is detected at a position delayed by the block length, and the content of the block ID is appropriate, the phase of the synchronization block is specified.

When a sync block is recorded on a magnetic tape, shuffling is performed in sync block units. After the outer code is encoded, the data arranged in sync block units in the scanning order is shuffled based on a predetermined pattern. An ID is added to the shuffled sync block for each sync block, the inner code is encoded, and the sync block is recorded on a magnetic tape. By the shuffling, the recording positions of the sync blocks on the tape are dispersed in the scanning order. At the time of reproduction, the sync blocks whose inner codes have been decoded are rearranged in the original order using the ID added to each sync block as address information, and are deshuffled. Shuffling prevents data from being intensively decoded due to bursty errors. Further, by performing shuffling, the image update rate can be improved even when data is reproduced in pieces during variable speed reproduction.

[0006] In order to record / reproduce the amount of image data, compression encoding is performed. For example, MPEG (Moving
In the case of Picture Experts Group), DCT (Discrete Cosine Transform)
Is performed, and the coefficient data generated by the DCT is subjected to variable length coding. A macroblock is composed of a plurality of DCT blocks. If the size of the DCT block is constant, the number of macroblocks is uniquely determined by the size of the picture frame, that is, the number of pixels in the horizontal direction and the number of lines in the vertical direction.

[0007]

Conventionally, the number of sync blocks constituting one screen is fixed, and the sync blocks and the above-mentioned macro blocks are in one-to-one correspondence with each other, and video signals are recorded on a magnetic tape. Was recorded.
This is shown in FIG. FIG. 30 shows recording of an NTSC video signal on a magnetic tape, in which the picture frame size is 720 pixels in the horizontal direction and 512 pixels (lines) in the vertical direction. As shown in FIG.
A macro block is composed of 16 pixels × 16 pixels,
The number of macroblocks on the screen is 144 consisting of 45 macroblocks in the horizontal direction and 32 macroblocks in the vertical direction.
There are zero. Therefore, the image data of one screen is shown in FIG.
As shown in FIG. 0B, it is recorded by 1440 sync blocks on the magnetic tape.

[0008] This is based on the reason that the magnetic tape is run at a higher speed than at the time of recording and reproduced, and the quality of the image is easily managed at the time of shuttle reproduction. At the time of shuttle reproduction, the rotary head traces a plurality of tracks obliquely, so that all data of one track cannot be reproduced. Thus, by fixing the number of sync blocks in one screen and recording the sync blocks and macro blocks in a one-to-one correspondence, the shuffled and dispersed macro blocks are recorded at the time of recording. Can be returned to the original position by deshuffling, and the image update rate during shuttle playback can be improved.

On the other hand, in such a format in which a macro block and a sync block are recorded in a one-to-one correspondence, image data exists in all sync blocks recorded on a magnetic tape. Required.
Therefore, the conventional digital VTR has a problem that it can handle only an image with a fixed image frame.

For example, as shown in FIG.
30 are 352 pixels in the horizontal direction and 256 in the vertical direction, both in the horizontal and vertical directions with respect to the image frame of FIG.
Consider a case where image data of a pixel (line) is recorded.
In this case, the image is composed of a total of 352 macroblocks of 16 × 16 pixels, 22 in the horizontal direction and 16 in the vertical direction. In the case of FIG.
This is smaller than the number of 440 macroblocks. Therefore, for example, there is a portion where no image data exists, such as a hatched portion shown in FIG. 31A. Therefore, FIG.
As shown in FIG. 1B, there is no data to be written on the track on the magnetic tape where the image data for one screen is to be recorded, and the one-to-one relationship between the sync block and the macro block is not satisfied. It will break down.

In this case, since there is no data in the hatched portion in FIG. 31A, there is no ID to be address information. On the other hand, at the time of recording, the image frame size is 720 pixels × 5.
Since shuffling is performed on the assumption that the number of pixels is 12 (line), there is a problem that deshuffling during reproduction cannot be performed correctly.

Conventionally, for example, video equipment for broadcasting has been designed on the basis of a standard set in a closed system, so that it only needs to support a single format, and a fixed image frame size is sufficient. there were. However, in digital broadcasting currently being considered for implementation, a standardized technique called MPEG2 is used, so that it is necessary to handle video signals created by other systems.

According to the MPEG2 standard, a dynamic change of the picture frame size for each frame is permitted.
That is, in the MPEG2 bit stream, FIG.
As shown in FIG. 2A and FIG. 32B, information (horizontal_s in FIG.
size_value and vertical_size
_Value) is stored. Image data of a designated size is stored following the image frame size information. In a conventional digital VTR, the image frame size is 720
32B, which corresponds to the stream of FIG. 32A which is a pixel × 512 pixels, when the stream of FIG. 32B whose image frame size is reduced to 352 pixels × 256 pixels is input, a one-to-one correspondence between a sync block and a macro block is obtained. There was a problem that the response failed.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a recording apparatus and method, and a reproducing apparatus and method capable of coping with different picture frame sizes of digital video signals.

[0015]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is directed to a recording apparatus for recording digital video data on a recording medium in which the number of blocks corresponding to one screen is fixedly set. Detecting an image frame size of the input digital video data, and corresponding to the difference between the detected image frame size and the set image frame size, inputting data indicating invalidity to the input digital video data. A recording apparatus characterized in that it is added to data and recorded.

According to another aspect of the present invention, there is provided a recording method for recording digital video data on a recording medium in block units, wherein the number of blocks corresponding to one screen is fixedly set.
The image frame size of the input digital video data is detected, and data indicating invalidity is input to the input digital video data in accordance with the difference between the detected image frame size and the set image frame size. This is a recording method characterized by adding and recording.

According to the present invention, in a reproducing apparatus in which the number of blocks corresponding to one screen is fixedly set and digital video data recorded on a recording medium is reproduced in units of blocks, data is reproduced from the recording medium in units of blocks. A block to which data indicating invalidity is added is detected from a reproducing unit for reproducing and data reproduced by the reproducing unit, and control is performed so as not to output a block to which data indicating invalid is added. A playback device comprising output control means.

According to the present invention, in a reproducing method in which the number of blocks corresponding to one screen is fixedly set and digital video data recorded on a recording medium is reproduced in units of blocks, data is reproduced from the recording medium in units of blocks. A block to which data indicating invalidity is added is detected from the data reproduced in the reproducing step and the data reproduced in the reproducing step, and a block to which data indicating invalidity is added is not output. And a step of controlling output.

As mentioned above, claim 1 or claim 4
The invention described in (1) detects an image frame size of input digital video data, and inputs data indicating invalidity according to a difference between the detected image frame size and the set image frame size. Because the digital video data is recorded in addition to the input digital video data, even if the frame size of the input digital video data is different from the set frame size, the input digital video signal is set. The data can be recorded on the recording medium in the same manner as the data of the image frame size is recorded.

According to another aspect of the present invention, data is reproduced from a recording medium in block units, and a block to which data indicating invalid is added is detected from the reproduced data. Is controlled so as not to output the block to which the data indicating invalid is added, so that data of an image frame size different from the set image frame size is set in the same manner as the set image frame size. Even if the digital video data is recorded on the recording medium, the digital video data reproduced from the recording medium can be output with the same image frame size as at the time of recording.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment.

In this embodiment, the compression method is as follows.
For example, the MPEG2 system is adopted. MPEG2 is a combination of motion-compensated predictive coding and DCT-based compression coding. The data structure of MPEG2 has a hierarchical structure. FIG. 1 schematically shows a hierarchical structure of a general MPEG2 data stream. As shown in FIG. 1, the data structure includes a macroblock layer (FIG. 1E), a slice layer (FIG. 1D), and a picture layer (FIG.
C), GOP layer (FIG. 1B) and sequence layer (FIG. 1)
A).

As shown in FIG. 1E, the macroblock layer is composed of DCT blocks which are units for performing DCT. The macro block layer includes a macro block header and a plurality of DCT blocks. Fig. 1
As shown in D, it is composed of a slice header section and one or more macroblocks. As shown in FIG. 1C, the picture layer includes a picture header section and one or more slices. A picture corresponds to one screen.
As shown in FIG. 1B, the GOP layer includes a GOP header, I pictures that are pictures based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblocks, predicting the future from the past (Forward) Interframe predicting macroblocks, and predicting the future from the future (Backward)
There are an inter-frame prediction macro block and a bi-directional macro block predicted from both forward and backward directions. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. As shown in FIG. 1A, the uppermost sequence layer includes a sequence header section and a plurality of GOPs.

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence from which a data boundary cannot be detected unless the variable-length code is correctly decoded.

At the head of the sequence layer, GOP layer, picture layer and slice layer, a start code having a predetermined bit pattern arranged in byte units is arranged. The start code arranged at the head of each layer is called a sequence header code in the sequence layer and a start code in other layers, and the bit pattern is [00 00 01 xx] (hexadecimal notation). Two digits are shown, and [xx] indicates that a different bit pattern is arranged in each of the layers.

That is, the start code and the sequence header code are composed of 4 bytes (= 32 bits), and can identify the type of subsequent information based on the value of the 4th byte. Since these start codes and sequence header codes are arranged in byte units, they can be captured only by performing 4-byte pattern matching.

Further, the upper 4 bits of 1 byte following the start code are identifiers of the contents of the extended data area described later. The content of the extension data can be determined from the value of the identifier.

It is to be noted that such an identification code having a predetermined bit pattern arranged in byte units is not allocated to the macro block layer and the DCT block in the macro block.

The header of each layer will be described in more detail. In the sequence layer shown in FIG. 1A, a sequence header 2 is arranged at the head, and a sequence extension 3, an extension and user data 4 are arranged subsequently. Sequence header 2
Is arranged at the head of the sequence header code 1. Although not shown, a predetermined start code is also arranged at the head of each of the sequence extension 3 and the user data 4. From the sequence header 2 to the extension and user data 4 are used as the header part of the sequence layer.

As shown in FIG. 2, the sequence header 2 has a sequence header code 1, an encoded image size consisting of the number of horizontal pixels and the number of vertical lines, an aspect ratio, a frame rate, and a bit. Information set in units of a sequence, such as a rate, a VBV (Video Buffering Verifier) buffer size, and a quantization matrix, is assigned a predetermined number of bits and stored.

In sequence extension 3 after the extension start code following the sequence header, as shown in FIG.
Additional data such as a profile, a level, a color difference format, and a progressive sequence used in MPEG2 are specified. As shown in FIG. 4, the extension and user data 4 can store the information of the RGB conversion characteristics of the original signal and the display image size by the sequence display (), and the scalability mode and the scalability by the sequence scalable extension (). Layer designation and the like can be performed.

Following the header of the sequence layer, GOP
Is arranged. At the head of the GOP, a GOP header 6 and user data 7 are arranged as shown in FIG. 1B.
The GOP header 6 and the user data 7 are used as a GOP header. As shown in FIG. 5, the GOP header 6 includes a GOP start code 5, a time code, a GOP
Flags indicating the independence and the validity of each are assigned a predetermined number of bits and stored. As shown in FIG. 6, the user data 7 includes extension data and user data. Although not shown, a predetermined start code is arranged at the head of each of the extension data and the user data.

A picture is arranged following the header section of the GOP layer. As shown in FIG. 1C, a picture header 9, a picture coding extension 10, and extension and user data 11 are arranged at the head of the picture. At the head of the picture header 9, a picture start code 8 is arranged. A predetermined start code is provided at the head of the picture coding extension 10 and the extension and user data 11, respectively. The part from the picture header 9 to the extension and user data 11 is the header part of the picture.

As shown in FIG. 7, a picture start code 8 is arranged in the picture header 9, and encoding conditions for the picture are set. In the picture coding extension 10, as shown in FIG. 8, the range of the motion vector in the front-back direction and the horizontal / vertical direction and the picture structure are specified. In the picture coding extension 10, the setting of the DC coefficient accuracy of the intra macroblock,
Selection of an LC type, selection of a linear / non-linear quantization scale, selection of a scanning method in DCT, and the like are performed.

In the extension and user data 11, as shown in FIG. 9, setting of a quantization matrix, setting of a spatial scalable parameter, and the like are performed. These settings can be made for each picture, and encoding can be performed according to the characteristics of each screen. Further, in the extension and user data 11, it is possible to set the display area of the picture. Further, copyright information can be set in the extension and user data 11.

A slice is arranged following the header of the picture layer. At the head of the slice, as shown in FIG. 1D, a slice header 13 is arranged, and the slice head 1
3, a slice start code 12 is provided.
As shown in FIG.
Contains vertical position information of the slice. The slice header 13 further stores extended slice vertical position information, quantization scale information, and the like.

Following the header of the slice layer, a macro block is arranged (FIG. 1E). In the macro block, a plurality of DCT blocks are arranged following the macro block header 14. As described above, the macroblock header 1
4 has no start code. As shown in FIG. 11, the macroblock header 14 stores the relative position information of the macroblock, and instructs the setting of the motion compensation mode, the detailed setting related to the DCT coding, and the like.

Following the macroblock header 14, DC
A T block is provided. As shown in FIG. 12, the DCT block includes a variable-length coded DCT coefficient and D
Data on CT coefficients is stored.

In FIG. 1, a solid line delimiter in each layer indicates that data is aligned in byte units, and a dotted line delimiter indicates that data is not aligned in byte units. That is, up to the picture layer, FIG.
As shown in an example in FIG. 3A, the boundaries of the codes are separated in units of bytes, whereas in the slice layer, only the slice start code 12 is separated in units of bytes, and each macroblock is shown in FIG. 13B. As an example is shown, it can be divided on a bit-by-bit basis. Similarly, in the macroblock layer, each DCT block can be divided in bit units. On the other hand, in order to avoid signal degradation due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 14 shows the MPE in this embodiment.
The header of the G stream is specifically shown. As can be seen from FIG. 1, the respective header portions of the sequence layer, the GOP layer, the picture layer, the slice layer, and the macroblock layer appear continuously from the head of the sequence layer. FIG. 14 shows an example of a data array that is continuous from the sequence header portion.

From the beginning, a sequence header 2 having a length of 12 bytes is arranged, followed by a sequence extension 3 having a length of 10 bytes. Subsequent to the sequence extension 3, extension and user data 4 are arranged.
A 4-byte user data start code is arranged at the head of the extension and user data 4, and information based on the SMPTE standard is stored in the subsequent user data area.

Next to the header part of the sequence layer is the header part of the GOP layer. A GOP header 6 having a length of 8 bytes is arranged, followed by extension and user data 7. At the beginning of the extension and user data 7, a 4-byte user data start code is arranged, and in the subsequent user data area, information for ensuring compatibility with other existing video formats is stored.

The header part of the GOP layer is followed by the header part of the picture layer. A picture header 9 having a length of 9 bytes is arranged, followed by a picture coding extension 10 having a length of 9 bytes. After the picture coding extension 10, the extension and user data 11 are arranged. The extension and user data are stored in the first 133 bytes of the extension and user data 11, followed by a user data start code 15 having a length of 4 bytes. Following the user data start code 15, information for compatibility with another existing video format is stored. Further, a user data start code 16 is provided.
Data based on the TE standard is stored. Next to the header part of the picture layer is a slice.

The macro block will be described in more detail. The macro block included in the slice layer is a set of a plurality of DCT blocks, and the coded sequence of the DCT block is obtained by converting the sequence of quantized DCT coefficients into the number of consecutive 0 coefficients (run) and the non-zero sequence immediately after it. (Level) is variable-length coded as one unit. Macro blocks and DCT blocks within the macro block include:
Identification codes aligned in byte units are not added.

The macro block is composed of one screen (picture).
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

The numbers of macroblocks in the vertical and horizontal directions on the screen are mb_height and m, respectively.
Called b_width. The coordinates of the macroblock on the screen are the vertical position number of the macroblock, mb_row counted from 0 based on the upper end, and the horizontal position number of the macroblock, and mb_col counted from 0 based on the left end.
mn. To represent the position of the macroblock on the screen with one variable, macro
block_address is set to macroblock
_Address = mb_row × mb_width +
mb_column is defined in this way.

It is specified that the order of slices and macroblocks on a stream must be in the order of smaller macroblock_address. That is, the streams are transmitted from top to bottom of the screen and from left to right.

In MPEG, one slice is usually composed of one stripe (16 lines), and variable-length coding starts from the left end of the screen and ends at the right end. Therefore, V
When the MPEG elementary stream is recorded as it is by the TR, at the time of high-speed reproduction, the reproducible portion is concentrated on the left end of the screen and cannot be uniformly updated. Further, since the arrangement of the data on the tape cannot be predicted, if the tape pattern is traced at a constant interval, the screen cannot be uniformly updated. Furthermore, if an error occurs even at one location, it affects the right edge of the screen and cannot return until the next slice header is detected. For this purpose, one slice is composed of one macroblock.

FIG. 15 shows an example of the configuration on the recording side of the recording / reproducing apparatus according to this embodiment. When recording, the terminal 1
The digital signal input from 00 is SDI (Serial Da
ta Interface) is supplied to the receiving unit 101. SDI is
(4: 2: 2) In order to transmit a component video signal, a digital audio signal, and additional data, S
This is an interface defined by MPTE.
The SDI receiver 101 extracts a digital video signal and a digital audio signal from the input digital signal, and converts the digital video signal into an MPEG signal.
The digital audio signal supplied to the encoder 102 is supplied to the ECC encoder 109 via the delay 103.
Supplied to The delay 103 is for eliminating a time difference between the digital audio signal and the digital video signal.

The SDI receiver 101 extracts a synchronization signal from the input digital signal, and supplies the extracted synchronization signal to the timing generator 104. An external synchronization signal can be input to the timing generator 104 from a terminal 105. The timing generator 104 generates a timing pulse based on a specified signal among the input synchronization signal and a synchronization signal supplied from an SDTI receiving unit 108 described later. The generated timing pulse is supplied to each section of the recording / reproducing apparatus.

The input video signal is supplied to the MPEG encoder 1
In 02, the signal undergoes DCT (Discrete Cosine Transform) processing, is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the MPEG encoder 102 is an elementary stream (ES) compliant with MPEG2. This output is supplied to one input terminal of a recording-side multi-format converter (hereinafter, referred to as MFC) 106.

On the other hand, through the input terminal 107, the SDTI
(Serial Data Transport Interface) format data is input. This signal is transmitted to the SDTI receiving unit 10
At 8, synchronization is detected. Then, the elementary stream is temporarily stored in the buffer, and the elementary stream is extracted. The extracted elementary stream is supplied to the other input end of the recording MFC 106. The synchronization signal obtained by the synchronization detection is supplied to the timing generator 104 described above.

In one embodiment, for example, MPEG ES
In order to transmit (MPEG elementary stream), SDTI (Serial Data Transport Interface) -C
P (Content Package) is used. This ES is 4:
2: 2 components, and as described above, all are I-picture streams, and 1 GOP = 1
It has a picture relationship. In the SDTI-CP format, the MPEG ES is separated into access units and is packed in packets in frame units. The SDTI-CP uses a sufficient transmission band (27 MHz or 36 MHz at a clock rate and 270 Mbps or 360 Mbps at a stream bit rate), and can transmit ES in bursts in one frame period.

That is, system data, a video stream, an audio stream, and AUX data are arranged after the SAV of one frame period until the EAV.
There is no data in the entire one frame period, but data exists in a burst form for a predetermined period from the beginning. SDTI-CP streams (video and audio) can be switched in stream states at frame boundaries. The SDTI-CP has a mechanism for establishing synchronization between audio and video for content using SMPTE time code as a clock reference. Further, the format is determined so that SDTI-CP and SDI can coexist.

In the interface using the SDTI-CP, the encoder and the decoder are connected to the VBV (Video B-Video) as in the case of transferring a TS (Transport Stream).
buffer Verifier) Buffers and TBs (Transport Buf
fers), so there is less delay. Further, the fact that the SDTI-CP itself is capable of extremely high-speed transfer further reduces the delay. Therefore, in an environment where synchronization exists to manage the entire broadcast station, SDTI-
It is effective to use CP.

The SDTI receiving unit 108 further extracts a digital audio signal from the input SDTI-CP stream. The extracted digital audio signal is supplied to the ECC encoder 109.

The recording MFC 106 has a built-in selector and stream converter. Recording MFC 106
Are configured in one integrated circuit, for example. Recording side MF
The processing performed in C106 will be described. MPEG encoder 102 and SDTI receiving unit 1 described above
One of the MPEG ESs supplied from 08 is selected by a selector and supplied to a stream converter.

In the stream converter, the DCTs arranged for each DCT block based on the MPEG2 rules
The coefficients are grouped for each frequency component through a plurality of DCT blocks constituting one macroblock, and the grouped frequency components are rearranged. When one slice of the elementary stream is one stripe, the stream converter makes one slice consist of one macroblock. Further, the stream converter limits the maximum length of variable length data generated in one macroblock to a predetermined length. This can be achieved by setting the higher-order DCT coefficient to zero. The rearranged converted elementary stream is E
It is supplied to the CC encoder 109.

The ECC encoder 109 is connected to a large-capacity main memory (not shown), and includes a packing and shuffling unit, an outer code encoder for audio, an outer code encoder for video, an inner code encoder, a shuffling unit for audio, and a video. It has a built-in shuffling unit. The ECC encoder 109 includes a circuit for adding an ID in sync block units and a circuit for adding a synchronization signal. The ECC encoder 109 is composed of, for example, one integrated circuit.

In one embodiment, the error correction code for video data and audio data is
The product code is used. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. Reed-Solomon code (Reed-Solomon code)
de) can be used.

The processing in the ECC encoder 109 will be described. Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling sections, macroblocks are packed in fixed frames. At this time, the overflow portion that protrudes from the fixed frame is sequentially packed into an area that is vacant with respect to the size of the fixed frame.

Further, system data having information such as an image format and a version of a shuffling pattern is supplied from a system controller 121 described later, and is input from an input terminal (not shown). The system data is supplied to a packing and shuffling unit, and undergoes recording processing in the same manner as picture data. System data is video A
Recorded as UX. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

The video data and system data from the packing and shuffling unit (hereinafter, also referred to as video data even when system data is included unless otherwise necessary) are obtained by encoding the video data by outer coding. , And an outer code parity is added. The output of the outer code encoder is shuffled by a video shuffling unit to change the order in sync block units over a plurality of ECC blocks. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling performed by the shuffling unit may be referred to as interleaving. The output of the video shuffling unit is written to the main memory.

On the other hand, as described above, the SDTI receiving unit 1
08 or the digital audio signal output from the delay 103 is supplied to the ECC encoder 109. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is not limited to these, and may be input via an audio interface. An audio AUX is supplied from an input terminal (not shown). Audio AUX
Is auxiliary data, which is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data and is treated equivalently to the audio data.

The audio data to which the audio AUX is added (hereinafter, unless otherwise required, the audio data including the AUX is also simply referred to as audio data) is an audio outer code for encoding the audio data with an outer code. Supplied to the encoder. The output of the audio outer code encoder is supplied to the audio shuffling unit, and undergoes shuffling processing. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the audio shuffling unit is written to the main memory. As described above, the output of the video shuffling unit is also written in the main memory, and the main memory mixes audio data and video data into one-channel data.

Data is read from the main memory, added with an ID having information indicating a sync block number, and supplied to the inner code encoder. The inner code encoder encodes the supplied data with the inner code. A synchronization signal for each sync block is added to the output of the inner code encoder, thereby forming recording data in which the sync blocks are continuous.

The recording data output from the ECC encoder 109 is supplied to an equalizer 110 including a recording amplifier and the like, and is converted into a recording RF signal. The recording RF signal is supplied to a rotating drum 111 provided with a rotating head in a predetermined manner, and is recorded on a magnetic tape 112. Actually, a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotating drum 111.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used. Note that the equalizer 110 includes both a configuration on the recording side and a configuration on the reproduction side.

FIG. 16 shows an example of a track format formed on a magnetic tape by the rotary head described above. In this example, video and audio data per frame are recorded on four tracks. One segment is composed of two tracks having different azimuths. That is, four tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In each of the tracks, video sectors on which video data is recorded are arranged at both ends,
An audio sector in which audio data is recorded is arranged between video sectors. FIG. 16 shows the arrangement of sectors on the tape.

In this example, four channels of audio data can be handled. A1 to A4
Indicates audio data channels 1 to 4 respectively. The audio data is recorded with its arrangement changed in segment units. In this example, in this example, data of four error correction blocks is interleaved for one track, and Upper Side and Low
It is divided into sectors of r Side and recorded.

A system area (SYS) is provided at a predetermined position in the video sector of the lower side.
The system area is provided alternately for each track, for example, at the beginning and end of a lower side video sector.

In FIG. 16, SAT is an area in which a servo lock signal is recorded. A gap having a predetermined size is provided between the recording areas.

FIG. 16 shows that the data per frame is 4
In this example, data is recorded on a track. Depending on the format of data to be recorded / reproduced, data per frame can be recorded on eight tracks, six tracks, or the like.

As shown in FIG. 16B, the data recorded on the tape is composed of a plurality of blocks divided at equal intervals called sync blocks. FIG. 16C schematically shows the configuration of a sync block. The sync block is
It is composed of a SYNC pattern for synchronous detection, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Data is handled as packets in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. Many sync blocks are arranged (Fig. 1
6B) For example, a video sector is formed.

Referring back to FIG. 15, at the time of reproduction, a reproduction signal reproduced from the magnetic tape 112 by the rotary drum 111 is supplied to the reproduction side configuration of the equalizer 110 including a reproduction amplifier and the like. The equalizer 110 performs equalization and waveform shaping on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary.
The output of the equalizer 110 is supplied to the ECC decoder 113.

The ECC decoder 113 performs the above-described ECC
It performs processing reverse to that of the encoder 109, and includes a large-capacity main memory, an inner code decoder, a deshuffling unit for audio and video, and an outer code decoder. Further, the ECC decoder 113 includes a deshuffling and depacking unit and a data interpolation unit for video. Similarly, an audio AUX separation unit and a data interpolation unit are included for audio. The ECC decoder 113 is composed of, for example, one integrated circuit.

The processing in the ECC decoder 113 will be described. The ECC decoder 113 first detects synchronization and detects a synchronization signal added to the beginning of a sync block, and cuts out the sync block. As for the data, the reproduced data is supplied to the inner code encoder for each sync block, and error correction of the inner code is performed. The ID interpolation processing is performed on the output of the inner code encoder, and the ID of the sync block in which the error occurred due to the inner code, for example, the sync block number, is interpolated. The playback data with the interpolated ID is separated into video data and audio data.

As described above, the video data is the MPE
G means DCT coefficient data and system data generated in intra coding of G, and audio data is PCM
(Pulse Code Modulation) Data and audio AU
Means X.

The separated audio data is supplied to an audio deshuffling unit, and performs a process reverse to the shuffling performed by the recording-side shuffling unit. The output of the deshuffling unit is supplied to an outer code decoder for audio, and error correction by the outer code is performed. The audio outer code decoder outputs error-corrected audio data. An error flag is set for data having an uncorrectable error.

The audio AUX is separated from the output of the audio outer code decoder by the audio AUX separation unit, and the separated audio AUX is output from the ECC decoder 1.
13 (the path is omitted). Audio A
The UX is supplied to, for example, a system controller 121 described later.
The audio data is supplied to a data interpolation unit. In the data interpolating unit, an erroneous sample is interpolated. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like.

The output of the data interpolation unit is the ECC decoder 11
The audio data output from the ECC decoder 113 is output to the delay 117 and the SDTI output unit 115. The delay 117 is provided to absorb a delay caused by processing of video data in the MPEG decoder 116 described later. The audio data supplied to the delay 117 is supplied with a predetermined delay to the SDI output unit 118.

The separated video data is supplied to a deshuffling unit, and the reverse processing of the shuffling on the recording side is performed. The deshuffling unit performs a process of restoring the shuffling in sync block units performed by the shuffling unit on the recording side. The output of the deshuffling unit is supplied to the outer code decoder, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder is supplied to a deshuffling and depacking unit. The deshuffling and depacking unit performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit on the recording side. In the deshuffling and depacking unit, the packing performed at the time of recording is disassembled. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit, the system data is separated, output from the ECC decoder 113, and supplied to the system controller 121 described later.

The output of the deshuffling and depacking unit is supplied to a data interpolation unit, and data for which an error flag is set (that is, an error exists) is corrected.
That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero.
Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, in the data interpolation section, when the header added to the head of the video data is an error, processing for recovering the header (sequence header, GOP header, picture header, user data, etc.) is also performed.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain position onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The video data output from the data interpolator is the output of the ECC decoder 113, and the output of the ECC decoder 113 is supplied to a reproduction-side multi-format converter (hereinafter abbreviated as reproduction-side MFC) 114. . The reproduction-side MFC 114 is the recording-side MFC 1 described above.
It performs the reverse process of 06 and includes a stream converter. The reproduction-side MFC 106 is composed of, for example, one integrated circuit.

[0092] The stream converter performs a process reverse to that of the stream converter on the recording side. That is, D
The DCT coefficients arranged for each frequency component over the CT block are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

The input and output of the stream converter are as follows.
As with the recording side, a sufficient transfer rate (bandwidth) is secured according to the maximum length of the macroblock. If the length of the macroblock (slice) is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter is the reproduction side MF
The output of the reproduction side MFC 114 is output from the SDTI output unit 115 and the MPEG decoder 11.
6.

The MPEG decoder 116 decodes the elementary stream and outputs video data. That is, the MPEG decoder 142 performs the inverse quantization process and the inverse D
CT processing is performed. The decoded video data is supplied to the SDI output unit 118. As described above, audio data separated from video data by the ECC decoder 113 is supplied to the SDI output unit 118 via the delay 117. The SDI output unit 118 maps the supplied video data and audio data into an SDI format, and converts the data into a stream having a data structure in the SDI format. SDI output unit 11
8 is output from the output terminal 120 to the outside.

On the other hand, the SDTI output section 115 is supplied with the audio data separated from the video data by the ECC decoder 113 as described above. The SDTI output unit 115 converts the supplied video data and audio data as elementary streams into SDDT
I format and converted to a stream having a data structure of SDTI format. The converted stream is output from the output terminal 119 to the outside.

In FIG. 15, a system controller 121 is composed of, for example, a microcomputer and controls the entire operation of the storage / reproduction device. Further, the servo 122 performs the running control of the magnetic tape 112 and the drive control of the rotating drum 111 while communicating with the system controller 121.

FIG. 17A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder 102. M output from SDTI receiving section 108
The same applies to PEG ES. In the following, MPE
A description will be given using the output of the G encoder 102 as an example. DC
Starting from the upper left DC component in the T block, DCT coefficients are output in a zigzag scan in a direction in which the horizontal and vertical spatial frequencies increase. As a result, FIG.
As shown in FIG. 1, a total of 64 (8 pixels × 8 lines) DCT coefficients are obtained by being arranged in order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

In the recording-side stream converter built in the recording-side MFC 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 18 schematically shows rearrangement of DCT coefficients in the recording-side stream converter.
In the case of a (4: 2: 2) component signal, one macroblock is composed of four DCT blocks (Y ₁ , Y ₂ , Y ₃ and Y ₄ ) based on a luminance signal Y and chromaticity signals Cb and C.
r, two DCT blocks (C
b ₁ , Cb ₂ , Cr ₁ and Cr ₂ ).

As described above, the MPEG encoder 10
In 2, the zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 18A, the DCT coefficients are arranged in the order of frequency components from DC components and low frequency components to high frequency components for each DCT block. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

In the recording-side stream converter, the variable-length coded and arranged DCT coefficients are once decoded by decoding the variable-length codes to detect the breaks of each coefficient, and are straddled over each DCT block constituting the macro block. Summarize for each frequency component. This is shown in FIG. 18B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are described with reference to FIG.
Each variable length code is assigned to a set consisting of a run and a subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the recording-side stream converter is supplied to a packing and shuffling unit built in the ECC encoder 109. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. MPE
In the G encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. In the packing and shuffling unit, the data of the macroblock is applied to a fixed frame.

FIG. 19 schematically shows a macroblock packing process in the packing and shuffling unit. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time matches the data length of the sync block, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 19, for simplicity,
Assume that one frame contains 8 macroblocks.

As shown in an example in FIG. 19A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of the data area of one sync block, which is a fixed frame, the data of the macro blocks # 1, # 3 and # 6 are longer, respectively.
The data of the macro blocks # 2, # 5, # 7 and # 8 are short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 19B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the portion (overflow portion) that protrudes from the sync block length is packed in an area that is vacant in order from the beginning, that is, after the macroblock whose length is less than the sync block length.

In the example of FIG. 19B, macro block # 1
The portion that protrudes from the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, a portion of the macro block # 6 that protrudes from the sync block length is packed behind the macro block # 7, and a portion that protrudes further from the macro block # 7.
Stuffed behind 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of the variable-length data corresponding to each macroblock can be checked in advance by the recording-side stream converter. This allows the packing unit to know the end of the macroblock data without decoding the VLC data and checking the contents.

FIG. 20 shows the ECC encoder 10 described above.
9 shows a more specific configuration. In FIG. 20, 164
Is an interface of the main memory 160 external to the IC. The main memory 160 is composed of an SDRAM. The interface 164 arbitrates an internal request for the main memory 160, and performs write / read processing on the main memory 160. The packing and shuffling unit 137 is constituted by the packing unit 137a, the video shuffling unit 137b, and the packing unit 137c.

FIG. 21 shows an example of the address configuration of the main memory 160. The main memory 160 is, for example, 64
It is composed of an M-bit SDRAM. Main memory 16
0 has a video area 250, an overflow area 251 and an audio area 252. Video area 250
Are four banks (vbank # 0, vbank # 1,
vbank # 2 and vbank # 3). Each of the four banks can store digital video signals of one equal length unit. One equalization unit is a unit for controlling the amount of generated data to a substantially target value, for example, one unit of a video signal.
This is a picture (I picture). Part A in FIG.
Indicates a data portion of one sync block of the video signal. Data of a different number of bytes is inserted into one sync block depending on the format. In order to cope with a plurality of formats, the data size of one sync block is equal to or larger than the maximum number of bytes and the number of bytes convenient for processing, for example, 256 bytes.

Each bank in the video area is further divided into a packing area 250A and an output area 250B to the inner encoding encoder. Overflow area 251
Consists of four banks corresponding to the above-mentioned video area. Further, the main memory 160 has an area 252 for audio data processing.

In this embodiment, the packing unit 1 is referred to by referring to the data length indicator of each macro block.
Reference numeral 37a stores the fixed frame length data and the overflow data, which is a portion exceeding the fixed frame, in separate areas of the main memory 160 and stores them. The fixed frame length data is data shorter than the length of the data area of the sync block, and is hereinafter referred to as block length data. The area for storing the block length data is the packing processing area 250A of each bank. If the data length is shorter than the block length, an empty area is created in the corresponding area of the main memory 160. The video shuffling unit 137b performs shuffling by controlling the write address. Here, the video shuffling unit 137b shuffles only the block length data, and does not shuffle the overflow portion.
Written to the area allocated for overflow data.

Next, the packing section 137c performs processing of packing and reading the overflow portion into the memory for the outer code encoder 139. That is, 1 is prepared from the main memory 160 to the outer code encoder 139.
The data of the block length is read into the memory of the ECC block, and if there is a free area in the data of the block length, an overflow portion is read there to block the data to the block length. When data for one ECC block is read, the reading process is temporarily suspended, and the outer code encoder 139 generates parity of the outer code. The outer code parity is the outer code encoder 13
9 is stored in the memory. When the processing of the outer code encoder 139 is completed for one ECC block, the outer code encoder 1
From 39, the data and the outer code parity are rearranged in the order of performing the inner code, and are written back to the packing processing area 250A of the main memory 160 and another output area 250B.
The video shuffling unit 140 performs shuffling on a sync block basis by controlling an address at the time of writing back the data on which the encoding of the outer code has been completed to the main memory 160.

As described above, the block length data and the overflow data are separated and the data is written into the first area 250A of the main memory 160 (first packing process), and the overflow data is packed into the memory of the outer code encoder 139. (The second packing process), the generation of the outer code parity, and the data and the outer code parity in the second area 250 of the main memory 160.
The process of writing back to B is performed in units of one ECC block.
Since the outer code encoder 139 includes the memory having the size of the ECC block, the frequency of access to the main memory 160 can be reduced.

A predetermined number of Es contained in one picture
When the processing of the CC block (for example, 32 ECC blocks) is completed, the packing of one picture and the encoding of the outer code are completed. The data read from the area 250B of the main memory 160 via the interface 164 is processed by the ID addition unit 148, the inner code encoder 147, and the synchronization addition unit 150, and the output data of the synchronization addition unit 150 is output by the parallel / serial conversion unit 124. Is converted to bit serial data. The output serial data is processed by the partial response class 4 precoder 125. This output is digitally modulated as required, and is supplied via a recording amplifier 110 to a rotating head provided on a rotating drum 111.

It is to be noted that a sync block called null sync, in which valid data is not arranged, is introduced into the ECC block, and an ECC block is provided for the difference in recording video signal format.
The configuration of the C block is made flexible.
The null sink is generated in the packing unit 137a of the packing and shuffling block 137, and written into the main memory 160. Therefore, since the null sync has a data recording area, it can be used as a recording sync for the overflow portion.

In the case of audio data, even-numbered samples and odd-numbered samples of one-field audio data form separate ECC blocks. Since the ECC outer code sequence is composed of audio samples in the input order, the outer code encoder 136 generates an outer code parity each time an outer code sequence audio sample is input. The address control when writing the output of the outer code encoder 136 to the area 252 of the main memory 160 causes the shuffling unit 137 to perform shuffling (channel units and sync block units).

Further, a CPU interface indicated by 126 is provided, receives data from an external CPU 127 functioning as a system controller, and sets parameters for internal blocks. In order to support a plurality of formats, it is possible to set many parameters including a sync block length and a parity length.

“Packing length data” as one of the parameters is sent to the packing units 137a and 137b, and the packing units 137a and 137b determine the fixed frame (“sync block length” in FIG. 19A) based on the data. ) With VLC data.

"Pack number data" as one of the parameters is sent to the packing unit 137b, and the packing unit 137b determines the number of packs per sync block based on the data, and the data for the determined number of packs is determined. Is supplied to the outer code encoder 139.

[0124] "Video outer code parity number data" as one of the parameters is sent to outer code encoder 139, and outer code encoder 139 outputs the outer code of the video data from which the number of parities is uttered. Perform encoding.

Each of “ID information” and “DID information” as one of the parameters is sent to the ID adding section 148, and the ID adding section 148
The ID information is added to the unit-length data string read from the main memory 160.

Each of “parameter number data for video inner code” and “parity number data for audio inner code” as one of the parameters is an inner code encoder 149.
And the inner code encoder 149 encodes the inner code of the video data and the audio data from which the number of parities are generated based on these. It should be noted that “sink length data”, which is one of the parameters, is also sent to the inner code encoder 149, whereby the unit length (sink length) of the inner-coded data is regulated.

Further, shuffling table data as one of the parameters is stored in a video shuffling table (RAM) 128v and an audio shuffling table (RAM) 128a. The shuffling table 128v performs an address conversion for shuffling the video shuffling units 137b and 140. The shuffling table 128a performs an address conversion for the audio shuffling 137.

Next, an embodiment of the present invention will be described in more detail. ECC encoder 109 described above
Performs an error correction encoding process, expecting that the sync block and the macro block correspond one-to-one. That is, for example, the number of macroblocks for one frame supplied to the ECC encoder 109 needs to be equal to the number of sync blocks for one frame.

Here, MPEG ES can be input, and N
Suppose a digital VTR that supports TSC. This means that the image frame size is 720 pixels x 512 lines,
M in which the number of macroblocks of 16 pixels × 16 pixels (lines) is 1440 (= 45 × 32) per frame
It is expected that PEG ES will be entered.

Consider a case where an MPEG ES having an image frame size different from that described above is supplied to this digital VTR. For example, the SDTI receiving unit 108 has 352 pixels ×
In the 256 lines, that is, in the header information of the MPEG ES, the horizontal size is 352,
MPEGE whose vertical size is 256
S is supplied. In one frame, the number of input MPEG ESs is 22 in the horizontal direction and 16 in the vertical direction, for a total of 35.
It has two macroblocks. This is because the number of 1440 macroblocks per frame expected for the assumed digital VTR ECC encoder 109 is not enough, so that the operation of the ECC encoder 109 breaks down as already described in the conventional example. Become.

According to the present invention, in the recording side MFC 106, horiz in the header information of the input MPEG ES
total size and vertical size
Monitor e. horizontal size va
lue and vertical size value
Is the sequence header 2 as shown in FIG.
Is stored in As in the example above, 22 in the horizontal direction,
When MPEGES having a matrix of 16 macroblocks in the vertical direction is supplied, this is detected, and it is determined that there is no macroblock in a portion other than the matrix (the above-described hatched portion in FIG. 31A). Is done.

Therefore, dummy data is inserted into a portion where no macro block exists so that the image frame size assumed in the digital VTR is obtained. As a result, a data stream having a matrix of 45 macroblocks including dummy data in the horizontal direction and 32 in the vertical direction per frame is transmitted to the ECC encoder 1.
09 and the ECC encoder 109
Can operate as if the number of sync blocks and the number of macro blocks in one frame correspond one to one.

In this embodiment, [00 00 01 AF] (hexadecimal notation), which is a unique code in MPEG, is used as the dummy data.
Is used. Therefore, during reproduction, the ECC decoder 11
3 [00 00 01 A]
F], and by deleting the detected code, the same MPEG ES supplied to the SDTI receiving unit 108 can be supplied to the SDTI output unit 115 and output.

FIG. 22 shows an example of the input MP as described above.
An example configuration for adding dummy data to an EG ES is shown. This configuration is included in the recording-side MFC 106. FIG. 23 is a timing chart showing an example of the operation in the configuration of FIG. The MPEG ES output from the SDTI receiving unit 108 is input to the frame detecting unit 300, the H / V detecting unit 302, and the frame memory 303, respectively. The input of the MPEG ES is performed, for example, one byte per clock. The frame memory 303 is a memory for storing the input MPEG ES.

In the frame detector 300, the input M
The head of the frame is detected from the PEG ES, and a frame start signal indicating the head of the frame is output. The frame start signal is supplied to the counter 301. At the beginning of the frame, for example, the bit pattern is [00 00 01 B
3] A sequence header code defined as (hexadecimal notation) is detected by pattern matching. FIG.
As shown in A, when the last [B3] is detected, it is known that it is a sequence header code, so that a frame start signal is output at that timing (FIG. 23B).

The counter 301 is a counter that counts up by a clock and resets a count value by a frame start signal. When a frame start signal is supplied from the frame detection unit 300, the counter 301 counts up for each clock, and a signal LOCATE shown in FIG. 23C is generated. The signal LOCATE is MP
It is a signal corresponding to the position in byte units in the EG ES.

The signal LOCATE is output from the H / V detector 302
Supplied to As described above, the H / V detection unit 302 is supplied with the MPEG ES together with the frame detection unit 300. In the H / V detection unit 302, the supplied MP
EG ES is counted based on the signal LOCATE, and the horizontal clock of the third clock from the frame start signal is counted.
The ntal size value (FIG. 23D) and the vertical size value at the fourth clock
(FIG. 23E) is extracted and stored in a register (not shown).

As described above, the sequence header 2
Horizontalsize value stored in
e and vertical size value are
Each of them is assigned 12 bits. If the image frame size cannot be represented by each of these 12 bits, horizont stored in sequence extension 3
al size extension and verti
cal size extension (see Fig. 3)
Can be used as the upper two bits of each image frame size. In this case, the number of signals LOCATE to be counted may be increased in H / V detection section 302 so that the position where the above value is stored in sequence extension 3 can be read.

On the other hand, as described above with reference to FIG. 31A, for example, 352 pixels in the horizontal direction and 256 lines in the vertical direction, that is, horizontal size value =
352, vertical size value = 2
The MPEG ES 56 is as shown in FIG. 24 as a whole, and a macroblock MB is continued following a sequence header code and predetermined header information (not shown). In this case, the column of the macroblock MB is the 22nd macroblock MB (2
2) and the 46th macroblock MB (46) are discontinuous. As can be seen from FIG. 32A described above, the picture frame size of the supplied MPEG ES is smaller than the original picture frame size of this digital VTR.
The macro blocks MB (23) to MB (45) are missing as portions where data to be written does not exist. The frame memory 303 stores an MPE as shown in FIG.
G ES is stored.

In the above-described H / V detection section 302, the signal LO
Based on CATE, as shown in FIG. 25A, the timing of the header and the macroblock is managed. Then, the hor extracted in FIG. 23D and FIG.
izonrtal sizevalue and vert
The signal INVAL shown in FIG. 25B is generated from the ical size value. The signal INVAL is
In the supplied MPEGES, since the image frame size is smaller than the specified size, the macro blocks MB (23) to MB (23) to MB
(45) takes a value of "1" in the missing part. That is, the signal INVAL is a signal which becomes "1" in a portion where there is no data to be written, which is indicated by hatching in FIG. 32A.

For example, the signal INVAL is a vertic
At vertical positions equal to or less than the number of macroblocks determined from the al size value, hori
It becomes "1" when the number of macro blocks exceeds the number of macro blocks obtained from the "zonal size value". At the vertical position exceeding the number of macroblocks calculated from the vertical size value (in this case, on the lower side of the screen), all the horizontal positions are "
1 ".

The signal INVAL is inverted by an inverter 305 to become a signal VALID,
3 RE port 310. Also, the signal INV
AL is supplied to the dummy generation unit 304 and the selector 306, respectively.

The frame memory 303 in which the input MPEG ES is stored outputs the stored data when the signal RE (Read Enable) supplied to the RE port 310 is “1”, and outputs the stored data when the signal RE is “0”. Stop the output.
Therefore, as shown in FIG. 25C, the signal INVA
While L is "0", the stored MPEG ES is output. That is, the MPEG ES is output in the above-mentioned area not shown by the diagonal lines in FIG. 31A.

On the other hand, in the dummy generation section 304, the signal IN
While VAL is "1", an example is shown in FIG.
Dummy data is output for each clock. The dummy data has a data length of, for example, 4 bytes in total, and has the same bit pattern [00 00 01] as the start code up to the third byte from the beginning. The fourth byte of the start code uses a value that is not normally used to indicate that this data is invalid data. In this embodiment, [AF] is used as the fourth byte as described above.

By detecting a macro block using [00 00 01] as a synchronization word and detecting that [AF] follows the synchronization word, added dummy data can be detected. . At the time of reproduction, which will be described later, this is used to detect and delete the added dummy data.

The selector 306 sets the signal INVAL to “
When it is 1 ", dummy data is selected and the signal INVA
When L is "0", the output from the frame memory 303 is selected. As a result, as shown in FIG. 25E, the position (inv) of the macroblock where no image data exists because the image frame size is smaller than the specified value.
MPEG ES in which dummy data has been supplemented to the
Is generated.

MPEG output from selector 306
The ES converts the DCT coefficients by a stream converter built in the recording-side MFC 106, and outputs the converted MPE.
GES is supplied to the ECC encoder 109. The ECC encoder 109 performs packing, shuffling, outer code encoding, ID addition, inner code encoding, synchronization signal addition, and the like, as described above.
1 and recorded on the magnetic tape 112.

As shown in FIG. 27, an ordinary macroblock is a horizontal direction following a 4-byte slice start code 12 consisting of a 3-byte synchronization word and 1-byte macroblock position information. , And image data including DCT coefficients and the like. Since the size of the dummy data is much smaller than that of a normal macro block, the ECC encoder 10
9 can be effectively used in the packing process.

Next, the processing at the time of reproduction will be described. An MPEG ES to which dummy data has been added at the time of recording needs to delete the added dummy data and output it at the time of reproduction. FIG. 28 shows an example of a configuration for detecting and deleting dummy data added at the time of recording. This configuration is included in the reproduction-side MFC 114. FIG. 29 shows a timing chart of an example of the operation in the configuration of FIG.

The reproduced signal read from the magnetic tape 112 is transmitted from the rotating drum 111 via the equalizer 110 to E.
It is supplied to the CC decoder 113. ECC decoder 11
In step 3, the supplied reproduced signal is subjected to processes such as synchronization detection, inner code error correction, ID interpolation, deshuffling, outer code error correction, and depacking, as described above. Is output.

The converted MPEG ES output from the ECC decoder 113 is supplied to the reproduction side MFC 114,
The signals are supplied to the NVAL detector 350, the VAL detector 351 and the D flip-flop (D-FF) 352A. The D-FF 352A has three more D-FFs on the output side.
The FFs 352B, 352C, and 352D are connected, and a total of four D-FFs 352 are configured. D-FF352
Provides a predetermined delay to the input converted MPEG ES.

In the converted MPEG ES, if the start code is [00 00 01 AF], the first 3
The byte synchronization word indicates that it is a macro block, and the fourth byte indicates that it is dummy data added during recording. If the first three bytes of the synchronization word are [00 00 01] and the fourth byte is other than [AF], this indicates that it is a valid macro block as image data.

In the configuration shown in FIG. 28, the INVAL detection section 350 is a circuit for detecting the code [00 00 01 AF]. The VAL detector 351 is a circuit that detects that the first three bytes of the synchronization word are [00 00 01] and the fourth byte is a code other than [AF]. The INVAL detector 350 and the VAL detector 351 detect these codes by, for example, pattern matching. For example, in each circuit, first, a synchronization word [00 00 01] is detected, and a code of a subsequent fourth byte is detected. If the fourth byte is [AF], the INVAL detection unit 350 outputs a signal INVAL that is “1” at that clock and “0” at that clock otherwise.
In the VAL detection unit 351, if the fourth byte is other than [AF], it is "1" at that clock and [A
F], the signal V which is “0” at that clock
Output AL.

For example, as shown in FIG. 29A, consider a case where a converted MPEG ES is input. When a sequence header code having a 4-byte pattern of [00 00 01 B3] is supplied, a 3-word synchronization word [0
0 00 01] is INVAL detector 350 and VA
The L byte is detected by the L detector 351 and the next fourth byte is awaited. Since the subsequent fourth byte is [B3], “1” is output from the VAL detector 351 as shown in FIG. 29C, and “0” is output from the INVAL detector 350 (FIG. 29B). .

As described above, the VAL detector 351 detects the synchronization word [00 00 01], and when a pattern other than [AF] is detected in the fourth byte, the VAL detector 351 detects the synchronization word [00 00 01].
"1" is output as in 9C. If the pattern of the fourth byte is [AF], "0" is output.

On the other hand, the INVAL detector 351 detects the synchronization word [00 0001], and when the pattern [AF] is detected in the fourth byte, as shown in FIG.
If the fourth byte is other than [AF], "0" is output.

The signal INVAL and the signal VAL are respectively connected to the RS-flip-flop (RS-FF)
Terminal and the R terminal. RS-FF 353 is
When the signal INVAL input to the S terminal falls,
1 "to generate a signal OFF that is reset at the falling edge of the signal VAL input to the R terminal.
Is "1" during the period when dummy data is inserted as shown in FIG. 29D, and "1" during other periods.
This signal is 0. The signal OFF is supplied as a control signal to a switch circuit 354 that is controlled to be open at “1” and closed at “0”.

The output of the D-FF 352 is
4 is supplied. The D-FF 352, as described above,
Stage D-FFs 352A, 352B, 352C and 35
As shown in FIG. 29E, the input converted MPEG ES is output with a delay of 4 clocks. Therefore, [AF] following [00 00 01]
Is detected and becomes “1”, and the rising of the signal OFF,
Of the converted MPEG ES output from the D-FF 352,
The timing of the inserted dummy data is synchronized with the start of the start code. Therefore, the switch circuit 3
At 54, the dummy data inserted into the converted MPEG ES is gated, and the switch circuit 354 outputs the converted MPEG ES from which the dummy data has been deleted.

A converted MPEG output from the switch circuit 354, in which dummy data inserted at the time of recording has been deleted.
In the ES, the DCT coefficients are rearranged by a stream converter built in the reproduction side MFC 114, and the MPEG E
It is output as S.

As can be seen from the above description, the insertion of dummy data at the time of recording detects a sequence header code and inserts hor appearing after the sequence header code.
zonal size value and vert
Since the process is performed based on the ical size value, it is possible to cope with a case where the image frame size dynamically changes in units of a sequence.

In the above description, the present invention has been described as being applied to a recording / reproducing apparatus for recording and reproducing digital video signals using a magnetic tape as a recording medium. However, the present invention is not limited to this example. That is, the present invention is applicable when it is required that the correspondence between macroblocks and data recording areas such as sectors be one-to-one. For example, even when a disk-shaped recording medium such as a hard disk is used as a recording medium, macroblocks and data such as sectors are used for reasons such as maintaining a constant reproduction image quality during shuttle reproduction and facilitating data management. It is useful to make the correspondence with the recording area one-to-one.

Further, in the above description, the present invention relates to MPEG2
However, the present invention is not limited to this example.
4 can be supported.

[0163]

As described above, according to the present invention, at the time of recording, the image frame size information of the data stream to be recorded is detected, and based on the detected image frame size, the image frame size is sufficient. Dummy data is inserted in the missing part. Therefore, there is an effect that a series of images having a dynamically changing image frame can be recorded.

Furthermore, by using the present invention, macroblocks and recording areas such as sectors on a recording medium are associated one-to-one, so that image data management becomes easy. There are effects such as stabilization.

[Brief description of the drawings]

FIG. 1 is a schematic diagram schematically showing a hierarchical structure of MPEG2 data.

FIG. 2 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 3 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 4 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 5 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 6 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 7 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 8 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 9 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 10 is a schematic diagram illustrating the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 11 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 12 is a schematic diagram showing the contents and bit allocation of data arranged in an MPEG2 stream.

FIG. 13 is a diagram illustrating alignment of data in byte units.

FIG. 14 is a schematic diagram specifically illustrating an MPEG stream header according to an embodiment.

FIG. 15 is a block diagram illustrating an example of a configuration on a recording side of the recording / reproducing apparatus according to the embodiment.

FIG. 16 is a schematic diagram illustrating an example of a track format formed on a magnetic tape.

FIG. 17 is a schematic diagram illustrating an output method of a video encoder and variable-length encoding.

FIG. 18 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 19 is a schematic diagram for explaining a process of packing data whose order is rearranged into a sync block.

FIG. 20 is a block diagram showing a more specific configuration of the ECC encoder.

FIG. 21 is a schematic diagram illustrating an example of an address configuration of a main memory.

FIG. 22 is a block diagram illustrating an example of a configuration for adding dummy data to input MPEG ES.

FIG. 23 is a time chart illustrating an example of a process for adding dummy data to an input MPEG ES.

FIG. 24 is a schematic diagram schematically showing MPEG ES.

FIG. 25 is a time chart illustrating an example of a process for adding dummy data to input MPEG ES.

FIG. 26 is a schematic diagram illustrating a structure of an example of dummy data;

FIG. 27 is a schematic diagram illustrating a structure of an example of a macro block.

FIG. 28 is a block diagram showing an example of a configuration for detecting and deleting dummy data added at the time of recording.

FIG. 29 is a timing chart illustrating an example of a process for detecting and deleting dummy data added during recording.

FIG. 30 illustrates recording of a video signal on a magnetic tape by fixing the number of sync blocks forming one screen and making the sync blocks correspond to the macroblocks on a one-to-one basis. FIG.

FIG. 31 is a schematic diagram illustrating recording of a video signal on a magnetic tape when an image frame size smaller than a set image frame size is input.

FIG. 32 is a schematic diagram illustrating positions where image frame size information in an MPEG2 bit stream is stored.

[Explanation of symbols]

1 ... sequence header code, 2 ... sequence header, 3 ... sequence extension, 4 ... extension and user data, 5 ... GOP start code, 6 ...
GOP header, 7: user data, 8: picture start code, 9: picture header, 10
..Picture coding extension, 11 ... extension and user data, 12 ... slice start code, 13 ...
・ Slice header, 14 ... macroblock header,
101: SDI receiver, 102: MPEG encoder, 106: Multi-format converter (MFC) on recording side, 108: SDTI receiver, 109
... ECC encoder, 112 ... Magnetic tape, 1
13: ECC decoder, 114: reproduction side MF
C, 115: SDTI output unit, 116: MPE
G decoder, 118... SDI output unit, 137a, 1
37c: packing part, 137b: video shuffling part, 139: outer code encoder, 140
..Video shuffling, 149... Inner code encoder, 300... Frame detector, 302... H / V
Detector, 304 ... Dummy generator

Continued on the front page (72) Inventor Susumu Todo 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Akira Sugiyama 6-35-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation In-house F-term (reference) 5C053 FA22 GB01 GB06 GB07 GB08 GB11 GB15 GB18 GB22 GB26 GB30 GB38 HA21 JA22 KA01 KA05 5D044 AB05 AB07 BC01 CC03 DE03 DE12 DE83 EF03 FG10 FG24 GK07 HL04 JJ07

Claims (6)

[Claims] 1. A recording apparatus in which the number of blocks corresponding to one screen is fixedly set, and in which a digital video data is recorded on a recording medium in block units, an image frame size of the input digital video data is detected. In response to the difference between the set image frame size and the set image frame size, data indicating invalidity is added to the input digital video data and recorded. Recording device. 2. The recording apparatus according to claim 1, wherein the data indicating the invalidity is a block whose identifier has a value that is not normally used. 3. A recording method in which the number of blocks corresponding to one screen is fixedly set, and in a recording method for recording digital video data on a recording medium in block units, an image frame size of the inputted digital video data is detected and detected. In response to the difference between the set image frame size and the set image frame size, data indicating invalidity is added to the input digital video data and recorded. Recording method. 4. A reproducing apparatus in which the number of blocks corresponding to one screen is fixedly set and which reproduces digital video data recorded on a recording medium in block units, reproducing means for reproducing data in block units from the recording medium. Detecting, from the data reproduced by the reproducing means, a block to which data indicating invalid is added, and controlling not to output the block to which data indicating invalid is added. A playback device comprising output control means. 5. The reproducing apparatus according to claim 4, wherein the data indicating invalidity is a block whose identifier has a value that is not normally used. 6. A reproducing method in which the number of blocks corresponding to one screen is fixedly set, and digital video data recorded on a recording medium is reproduced in block units. Detecting, from the data reproduced in the reproducing step, a block to which data indicating invalid is added, and not outputting the block to which data indicating invalid is added. And a step of controlling output.