JP2000293435A - Device and method for reproducing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid reading and writing which are performed from/to the same address at the same time by performing access efficiently when reading and writing from/to a common bank of a memory is performed simultaneously. SOLUTION: A sink block is written to an SDRAM in an irregular order when a shuttle is reproduced. In the case access collision occurs between the next sink block reading and sink block writing, a normal mode is shifted to an avoiding mode, a read address is stored in a register and also the address is skipped, and reading is performed at the next address. When writing to an access collision address is finished, the skipped address is read from the register and also, the current read address is stored in another register. After the sink block of the skipped address is read, the read address is made the address stored in the other register and the normal mode is returned. Access collision can be avoided with the configuration of only two registers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing method in which the same memory area is not accessed for reading and writing when data reading and writing are simultaneously performed on one memory at different speeds. Apparatus and method.

[0002]

2. Description of the Related Art In recent years, digital video tape recorders, which use a magnetic tape as a recording medium and record and reproduce digital video signals and digital audio signals, are becoming widespread.

In such an apparatus, digital video data and digital audio data are stored in packet units of a predetermined length, and each packet has a synchronization pattern for detecting synchronization, an ID number for identifying each packet, and a data. The sync block is configured by adding ID information indicating the contents of the above and parity for error correction.
The lengths of the sync blocks in the same sector are the same, the ID numbers are consecutive, and the ID information has the same value. The error correction coding is performed by, for example, a product code that performs double coding of an outer code and an inner code.

[0004] The sync blocks are grouped into sectors according to the type of data, and are recorded on the magnetic tape as serial data in sector units. Recording is performed by a helical scan method in which tracks are formed diagonally on a magnetic tape by a rotating head.

At the time of reproduction, a track on a magnetic tape is traced by a rotary head, and a reproduction signal is obtained.
From the reproduced signal, a sync detection circuit detects a synchronization pattern from a reproduction bit string synchronized with the reproduction clock, adjusts the phase of the sync block, and cuts out the sync block.

[0006] The extracted sync block is subjected to inner code correction by the inner code parity added at the time of recording. If an error exists that exceeds the error correction capability of the error correction code, the data is not corrected and an error flag is set. The data that has been subjected to the inner code correction processing includes an ID number and an I
The rearrangement is performed in the outer code direction using a memory based on the D information, and the outer code is corrected.

As described above, in the digital video tape recorder, in the error correction circuit for performing error correction,
Transfers sync blocks via memory. By the way, in general, the data length of a sync block is larger than the data length that can be read and written in a single access to the memory.
Involves multiple accesses.

Here, consider the case where writing and reading are performed on a memory from a plurality of ports, respectively. At this time, if the sync block is written to the same address as the sync block being read from the memory, the content of the sync block may be rewritten during the reading. In order to avoid such a situation, the memory is generally divided into bank units composed of, for example, sync blocks of one frame or one field. The banks can be accessed independently of each other.

FIG. 17 schematically shows an example of memory access using a bank. The memory 200 is divided into two banks, bank A and bank B. For example, one frame of video data is written in each bank. As shown in an example in FIG. 17A, in the case of reproduction at a normal speed, that is, in the case of performing reproduction at the same tape running speed as at the time of recording, reading and writing are performed in different banks. For example, while reading the sync block from the bank B, writing is performed on the bank A. When writing to bank A is completed, the bank for writing is switched to bank B, and the bank for reading is switched to bank A. In this way, the two banks A and B are alternately switched to continuously input and output video data. More banks may be sequentially switched.

[0010] On the other hand, many digital video tape recorders can perform shuttle playback in which playback is performed with the tape running at a higher speed than during recording. In shuttle playback, it is necessary to display a video in which sync blocks of past frames are mixed. Therefore, the reading and writing of the sync block are often performed on a common bank as shown in an example in FIG. 17B.
A sync block is written to bank A, and a sync block is read from bank A. Therefore, at the time of shuttle reproduction, there is a possibility that read and write accesses are made to the same address. Access control is required to avoid read and write access to the same address.

[0011]

Conventionally, the following two methods have been proposed as access control methods for avoiding read and write accesses to the same address. The first method is a method of stopping write access when read and write accesses occur to the same address. Although this method can be realized by simple processing, the write block sync data is discarded, and there is a problem that the update rate of the sync block in the memory is reduced.

The second method detects that the read and write accesses of the sync block have been made to the same address, and temporarily stores the sync block to be written in the buffer memory. Then, at a timing when there is no possibility of rewriting the sync block being read,
This is a method of writing the sync blocks stored in the buffer memory to a predetermined address in the bank.

According to this method, both the writing and reading of the sync block are not stopped,
Reading and writing of the sync block can be performed in the common bank. However, the second method has a problem in that the worst situation must be assumed when estimating the capacity of the buffer memory, so that a relatively large capacity of the buffer memory must be ensured.

In the second method, it is necessary to further write the sync block data once written in the buffer memory to the bank, and there is a problem that unnecessary processing must be performed.

Accordingly, an object of the present invention is to simultaneously read and write data to and from a common bank of a memory with a small-scale configuration and to efficiently perform access to the same address. And a data recording apparatus and method for avoiding writing.

[0016]

According to the present invention, in order to solve the above-mentioned problem, a plurality of modules simultaneously access a data unit having a size that can be read and / or written by accessing a plurality of times. In a data reproducing apparatus having a possible memory system configuration, data can be simultaneously accessed from a plurality of modules, and data is stored in a data unit of a size that completes reading and / or writing by accessing a plurality of times. A memory, an address generating means for generating a read address for accessing the memory next, and detecting a match between the read address generated by the address generating means and a write address for accessing the memory from another module, or Readings generated by the generating means Address comparing means for detecting a change in a write address that is accessing the memory from another module that matches the write address, and the address comparing means matches the write address that is accessing the memory from another module. Address storage means for temporarily storing the read address detected as having been detected, an address generated by the address generation means in accordance with an address comparison result by the address comparison means,
Address selection means for switching and outputting the address stored by the address storage means, and monitoring a collision state between the write address and the read address;
A data reproducing apparatus characterized in that the order of read addresses is changed while a write address and a read address collide.

Further, the present invention relates to a data reproducing method having a memory system configuration in which a plurality of modules may simultaneously access a data unit having a size that can be read and / or written by accessing a plurality of times. , A plurality of modules can be accessed simultaneously, and a read address to be accessed next is generated in a memory that stores data in a memory in a data unit of a size that completes reading and / or writing by accessing a plurality of times. Detecting a match between the read address generated in the address generation step and the write address being accessed from another module to the memory, or determining whether the read address generated in the address generation step matches the read address generated in the address generation step. Please The address comparison step for detecting a change in the write address accessing the memory from another module, and the address comparison step detects that the write address matches the write address accessed to the memory from another module. An address storage step of temporarily storing the read address,
An address selection step of switching between an address generated in the address generation step and an address stored in the address storage step in accordance with an address comparison result in the address comparison step and outputting the address; A data reproducing method characterized in that a collision state between a write address and a read address is monitored, and the order of the read addresses is changed while the write address and the read address collide.

As described above, the present invention provides a memory which can be accessed simultaneously from a plurality of modules and stores data in data units of a size that completes reading and / or writing by accessing a plurality of times. Detecting whether the read address for accessing the memory next generated by the address generating means matches the write address accessing the memory from another module, or detecting a match with the read address generated by the address generating means. The change of the write address accessing the memory from another module is detected by the address comparing means, and the address comparing means detects that the write address matches the write address accessed from the other module to the memory. Read address is Temporarily stored in less storage means,
The address selecting means switches between the address generated by the address generating means and the address stored by the address storing means in accordance with the result of the address comparison by the address comparing means, and outputs the switched address. Monitor the status, and while the write address and read address collide,
Since the order of the read addresses is changed, a plurality of simultaneous accesses of the same data unit to the memory can be prevented without stopping each of the write and read accesses.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. According to the present invention, when data write and read addresses in a memory coincide with each other and an access collision occurs, the address information coincident between the write and the read is saved, and the read address is rearranged to avoid the access collision. . That is, when an access collision occurs in the memory, the address information of the address at which the access collision is determined is stored, and the read address is incremented to skip the address at which the access collision occurs. When the writing to the address where the access collision occurs is completed, the stored address information is read, and the read address information is read from the address.

Since only address information is stored, a large-capacity memory is not required. Further, since the data writing is continued as usual, the data update rate does not decrease.

First, for easy understanding, a recording / reproducing apparatus applicable to this embodiment will be described.
This recording / reproducing apparatus is suitable for use in a broadcasting station environment, and enables recording / reproducing of video signals of a plurality of different formats. For example, NTSC
48 effective lines in interlaced scanning based on
Both zero signals (480i signals) and signals having 576 effective lines (576i signals) in interlaced scanning based on the PAL system can be recorded / reproduced with almost no hardware change. You. Further, a signal of 1080 lines (1080i
Signal), progressive scanning (non-interlace), and recording / reproducing of 480 lines, 720 lines, 1080 signals (480p signal, 720p signal, 1080p signal) and the like, respectively.

In this recording / reproducing apparatus, a video signal signal is compression-encoded based on the MPEG (Moving Picture Experts Group) 2 system, and an audio signal is treated uncompressed. As is well known, MPEG2 is a combination of motion compensated predictive coding and compression coding by DCT (Discrete Cosine Transform). The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer,
It is an OP layer and a sequence layer.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this recording / reproducing apparatus, one GOP is composed of one I picture.

The recording area in which, for example, one frame of recording data is recorded is predetermined. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this recording / reproducing apparatus, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration on the recording side of the recording / reproducing apparatus. At the time of recording, a digital video signal is input from a terminal 101 via a receiving unit of a predetermined interface, for example, SDI (Serial Data Interface). S
DI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals and additional data. The input video signal is subjected to DCT (Discrete Cosine Transform) processing in the video encoder 102, converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling section 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction) are output.
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal 112. This recording / reproducing apparatus handles uncompressed digital audio signals. The digital audio signal is a signal separated by an SDI receiving unit (not shown) or an SDTI receiving unit 105 on the input side, or a signal input via an audio interface.
The input digital audio signal is supplied to the AUX adding unit 114 via the delay unit 113. The delay unit 113 is for time alignment of the audio signal and the video signal. Audio AUX supplied from input terminal 115
Is auxiliary data, which is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is an AUX adding unit 1
At 14, the audio data is added to the audio data and treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX unless otherwise necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be subjected to scramble processing as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side of the recording / reproducing apparatus of the present invention. A reproduction signal reproduced by the rotary head 122 from the magnetic tape 123 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. For the playback signal,
Equalization and waveform shaping are performed. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, where the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to a process reverse to shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As with the recording side, a sufficient transfer rate (bandwidth) is secured for the input and output of the stream converter 141 in accordance with the maximum length of the macroblock. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with the input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this recording / reproducing apparatus, recording of a signal on a magnetic tape is performed by a helical scan method in which a diagonal track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is constituted by two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged at both ends, and an audio sector in which audio data is recorded is interposed between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since data for one field is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data of two ECC blocks (including the outer code parity) is divided into four sectors, and as shown in FIG. 3, the data is dispersedly recorded on four tracks. Two ECCs
A plurality of sync blocks included in the block are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, video data is shuffled (interleaved) for four ECC blocks for one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks, but depending on the format of the data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this recording / reproducing apparatus, data of one or two macroblocks (VLC) for one sync block is adapted to the format of video data to be recorded.
Data) is stored, and the length is changed according to the format of the video signal handled by the size of one sync block. As shown in FIG. 5A, one sync block is a 2-byte SYNC pattern from the beginning, a 2-byte ID, a 1-byte DID, for example, 112 bytes to 20 bytes.
Data area variably defined between 6 bytes and 12
It consists of byte parity (inner code parity). In addition,
The data area is also called a payload.

The first two bytes of the SYNC pattern are used for synchronization detection and have a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

[0065] ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, length information LT indicating the length of the following macroblock is arranged in the first three bytes.
The length information LT may or may not include its own length. 5C shown in FIG.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.
The length information LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT describes the length of the video AUX data. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this recording / reproducing apparatus, the length of the payload, which is the data storage area of each sync block, is
Since the video sync block and the audio sync block are optimally set, the lengths are not equal to each other. In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Accordingly, the variable-length coded output for the coefficient data of the AC component is obtained by converting AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

The stream converter 106 rearranges the DCT coefficients of the supplied signal. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

The stream converter 106 decodes the variable-length coded and arranged DCT coefficients once by decoding the variable-length code to detect a break of each coefficient, and extends the frequency over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows the processing of packing a macroblock in the packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 9A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in this recording / reproducing apparatus. FIG. 10A shows one ECC block of an error correction code for video data.
FIG. 10B shows one ECC block of an error correction code for audio data. In FIG. 10A, VLC
The data is data from the packing and shuffling unit 107. SYNC for each row of VLC data
One SYNC block is formed by adding a pattern, ID, and DID, and further adding an inner code parity.

That is, a 10-byte parity of the outer code is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID, and VLC data (or outer) are aligned in the horizontal direction. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the lengths of VLC data in one SYNC block are different at 59.94 Hz, 25 Hz, 23.
This is because the frame frequency of video data is different, such as 976 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz.
And one sample is quantized to 16 bits. One sample may be converted into another bit number, for example, 24 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of the even-numbered and odd-numbered audio samples and the audio AUX as data.

Next, the access control of the memory according to the present invention will be described. FIG. 11 shows the deshuffling unit 136, the outer code decoder 137, and the de-shuffling unit 136 in FIG. 2 related to the memory access control according to the present invention.
An example of a configuration including a deshuffling and depacking unit 138 is shown. The outer code decoding process of the error correction code by the outer code decoder 137 and the depacking process by the deshuffling and depacking unit 138 are performed by SD
This is performed using the RAM 10.

SDRAM 10 has banks A, B, C, and D which can be accessed independently of each other, and banks 0 and 1. The banks A to D are banks used for outer code correction, in which sync blocks are written. Banks 0 and 1 are used for depacking processing. For example, one frame of video data can be written in each of the banks A and B and the banks 0 and 1.

In each bank of the SDRAM 10, an ID assigned to a sync block and an address correspond to each other. That is, in each frame, the same ID
Are written to the same address. Hereinafter, the address of the SDRAM 10 corresponding to the ID assigned to the sync block is referred to as the address of the sync block.

SDRAM 10 is SDRAM I / O 11
Connected to. SDRAM I / O11 is SDRAM
This is a module that controls all accesses to the server 10. To the SDRAM I / O 11, each module of a SYNC write control unit 12, an outer code decoder 13, a copy unit 14, and depacking units 15A and 15B is connected.

Although details will be described later, the copy unit 14
Includes an access control unit 20, which is a module that controls access to the SDRAM 10 so as to avoid access collisions in the banks A to D of the SDRAM 10.

The operation of the configuration shown in FIG.
This will be described with reference to FIG. FIG. 12 shows a transition of data in each module in FIG.
Shows the timing of an example of the processing in each module in FIG. In FIG. 13, an example of a read bank from the SDRAM 10 is shown above the arrow line indicating the timing, and an example of a write bank for the SDRAM 10 is shown below the arrow line.

The inner code is corrected by the inner code decoder 133.
The sync block whose ID has been interpolated by the ID interpolation unit 134 is supplied to the SYNC write control unit 12. FIG. 12A
Indicates an example of a sync block supplied to the SYNC write control unit 12. Data is supplied in the order of reproduction in sync block units. As shown in FIG. 13A, the reproduced data is continuously supplied for each frame.

In the shuttle reproduction, as described above, the running speed of the tape is higher than during recording, so that the trace angle of the rotary head 122 is different from the angle of the helical track formed on the magnetic tape 123. for that reason,
All data was not read from one track, and FIG.
, The sync blocks are played back step by step.

FIG. 12B shows the operation of the SYNC write control unit 12.
As shown in FIG. 3, the data is deshuffled based on the sync block ID. The write address of the deshuffled data is controlled by the SDRAM I / O 11 and written into one of the banks A to D, for example, the bank A of the SDRAM 10. In this example, FIG.
As shown in C, one frame of video data is composed of four error correction blocks ECC0 to ECC3.

At the time of normal reproduction, writing of a sync block to the SDRAM 10 is performed, for example, by switching banks for each frame. On the other hand, during shuttle playback,
As already described in the related art, each frame is written to the same bank (bank A in this example) because it is necessary to display a video in which past sync blocks are mixed.

Since deshuffling accompanies, as shown in FIG. 12C, an address is specified in the bank A in an irregular order with respect to the order of the reproduced sync blocks, and the sync blocks are written. As described above, in the bank A, each sync block is written to an address corresponding to the ID assigned to each sync block. As shown in FIG. 13B, the writing of data to the SDRAM 10 is performed according to the time series of data supply shown in FIG. 13A.

At the time of normal reproduction, reproduction is performed at the same tape running speed as during recording. Since all sync blocks in the error correction block are reproduced, the outer code decoder 1
3, error correction of the outer code is performed. SDRAM
The data of each error correction block written in the ten banks A is read out in the outer code sequence, that is, in the column direction, supplied to the outer code decoder 13, and subjected to outer code correction. The data to which the outer code error correction has been performed is SDR in the column direction.
The data is written back to bank A of AM10.

At the time of shuttle reproduction, as shown in FIG. 12C, since the sync blocks can be filled only in the error correction blocks ECC0 to ECC3, the error correction of the outer code by the outer code decoder is not performed. . Under the control of the copy unit 14, the sync block written to the bank A of the SDRAM 10 is written to the bank 0 or 1 for the depacking process. Here, it is assumed that a sync block is written from bank A to bank 1 for explanation.

As shown in an example of FIG. 12D, in the copy of the sync block under the control of the copy unit 14, the addresses of the bank A are sequentially specified, and the sync blocks are read out one after another. As shown in FIG. 12E, the read sync blocks are sequentially packed by switching the bank 1 or 0 alternately for each frame. Since the copy process under the control of the copy unit 14 does not need to be synchronized with the frame timing, it is performed at high speed for one frame period as shown in an example in FIG. 13C. At this time, the sync block corresponding to the outer code parity of the bank A is not copied because it is unnecessary.

At the time of normal reproduction, next, the sync block read from the bank 1 of the SDRAM 10 is supplied to the depacking unit 15A, and the first depacking process is performed. Here, the depacking process will be schematically described. At the time of the depacking processing, the processing reverse to the packing processing shown in FIG. 9 described above is performed to restore the macroblock.

In the depacking unit 15A, the SDRAM 1
The sync block is read from 0, and the macro block packed in the sync block is divided based on the length information L recorded at the beginning of the payload, for example. Then, the divided portions of the divided macro blocks packed into the original macro blocks are temporarily stored in a memory (not shown). In the depacking unit 15B, the SD
The sync block read from the RAM 10 is divided on the basis of the above-described length information L, and a divided part of the corresponding macro block stored in the memory by the depacking unit 15A is compared with the divided original macro block. The data is concatenated, and the variable length code data (VLC data) is restored.

At the time of shuttle reproduction, since all the sync blocks are not reproduced as described above, depacking processing cannot be performed. Therefore, at the time of shuttle reproduction, the processing in the depacking unit 15A is omitted.
At the time of shuttle reproduction, sync blocks are sequentially read from the bank to which the copy unit 14 has just copied, and the read sync blocks are supplied to the depacking unit 15B. In the depacking unit 15B, based on the length information L recorded in the payload of the supplied sync block, the macro block of the macro block packed with respect to the sync block storing the macro block whose data length is smaller than the sync block is stored. The divided part is separated from the sync block.

As described above, in the depacking unit 15B,
The sync block read from the bank 1 of the SDRAM 10 is converted into variable-length coded data having the maximum length of the sync block, and a sync signal or the like is added to the data to be output as a variable-length coded stream (VLC stream). As shown in an example in FIG. 13D, the output from the depacking unit 15B is delayed by the timing used for the copy processing in the copy unit 14, and is synchronized with the frame timing.

As described above, in the SDRAM 10,
In the banks 0 and 1, the processing is performed alternately for each frame, so that there is no collision between writing and reading during shuttle reproduction. On the other hand, in the banks A to D, for example, the bank A, there is a high possibility that an address collision occurs between the writing of the sync block by the SYNC writing unit 12 and the reading by the copying unit 14.

Here, the access collision refers to a state in which write access and read access are performed on the same sync block address in the same bank. In the case of a single-port RAM having only one port for data input / output, RA
Such multiple simultaneous accesses to M cannot occur, but multiple simultaneous accesses to the same sync block may occur. Here, also in this case, it is assumed that there is an access collision.

When an access collision occurs, writing to the address of the sync block is started while the sync block is being read, and the contents of the sync block being read may be rewritten. Sex is lost. Therefore, it is necessary to avoid access collision.

FIG. 14 shows an access method of the SDRAM 10 according to the present invention in which the above-mentioned access collision is avoided. FIGS. 14A and 14B show processing of writing and reading of a sync block, for example, in the bank A of the SDRAM 10 during shuttle reproduction. The processing is performed by switching between a normal mode in which no access collision occurs and a avoidance mode in the case where an access collision occurs.

The write processing of the sync block shown in FIG. 14A is performed on the bank A in an irregular address order, as described above. Although the details will be described later, the write address is always monitored by the SDRAM I / O 11 and an access control circuit 20 described later in the copy unit 14.

On the other hand, the read processing of the sync block shown in FIG. 14B is set to the normal mode when there is no access collision, and the read processing of the sync block is performed in the address order of the sync block.
Sync blocks are read one after another. A sync block causing an access collision is shown by hatching in FIG. 14B. The sync block in which the access collision occurs is skipped, and the operation shifts to the avoidance mode. When the mode shifts to the avoidance mode, reading from the sync block next to the sync block in which the access collision is assumed to occur is sequentially performed.

When the writing to the address of the sync block in which the access collision occurs is completed, the address of the sync block that is currently being read is stored, the address is returned to the skipped address, and the newly written sync block is read. Then, the processing mode is returned to the normal mode, and reading is performed sequentially from the sync block next to the sync block read at the time of completion of writing.

Next, the process of avoiding access collision at the time of writing and reading in the SDRAM 10 will be described in more detail. FIG. 15 shows an example of the configuration of the above-described access control circuit 20 that controls access collision avoidance. The access control circuit 20 is included in the copy unit 14 in the configuration of FIG. 11 described above, for example.

The access control circuit 20 is composed of an address generation circuit 21, a jump address register 22, an address status detection circuit 23 and an address selector 24. The access control circuit 20
The address sync_write which is the write address at which the sync block is currently written in the SDRAM 10, for example, in the bank A, by the YNC write control unit 12.
_Add is supplied and the sync block is transferred to the SDRAM 10
An address rsync_add which is a read address to be read from the bank A of the
An address wsync_add, which is a write address to be written to 10, is output.

In the access control circuit 20, the timing of the address generation circuit 21 is controlled by an increment signal supplied from an address selector 24 to be described later.
An seq_add and an address rseq_add, which is an address to be read next, are generated. These generated addresses are stored in the jump address register 2
2 and the address selector 24.

The jump address register 22 is controlled by the load signal supplied from the address selector 24, and controls the address wseq_add and the address rseq_add.
add and save. The address wseq_add and the address rseq_add stored in the jump address register 22 are an address wjmp_add which is a jump address for writing and an address rjm which is a jump address for reading, respectively.
It is supplied to the address selector 24 as p_add.

The address rseq_add is also supplied to the address status detection circuit 23. At the same time, the address sync_write_add described above is supplied to the address status detection circuit 23. The address status detection circuit 23 can switch the detection mode by a mode signal supplied from an address selector 24 described later. The detection result of the address status detection circuit 23 is used as a status signal by the address selector 2.
4 is supplied.

The address selector 24 switches between the normal mode and the avoidance mode based on the status signal supplied from the address status detection circuit 23 according to an algorithm according to a flowchart described later. The mode signal resulting from the switching is the address status detection circuit 2
3 is supplied. The address selector 24 outputs the read address rsync_add as the output address rjmp supplied from the jump address register 22.
_Add and the address rseq_add supplied from the address generation circuit 21 are selected.

FIG. 16 is a flowchart showing the above-described processing of FIG. 14 more specifically performed by the configuration of FIG. In FIG. 16, the left side of the one-dot chain line indicates processing in the normal mode, and the right side indicates processing in the avoidance mode. The processing is assumed to be started from the normal mode. The process shown in FIG. 16 is executed based on the control of the address selector 24 described above.

First, in the first step S10, the bank A
Write address wsync_add accessed to
It is determined whether or not read address rsync_add matches read address rsync_add. That is, first, the address rseq_add generated by the address generation circuit 21 is output as the read address rsync_add,
The sync block is read from the bank A according to the read address rsync_add. In the address status detection circuit 23, the address rsync_a
dd and the address sync_write_add are compared to detect whether they match.

If it is detected that they match, it is determined that an access collision has occurred, and a status signal indicating this is supplied to the address selector 24.
The address selector 24 sets the operation mode to the avoidance mode based on the status signal. A mode signal indicating the avoidance mode is supplied from the address selector 24 to the address status detection circuit 23.

On the other hand, in step S10, the address rsync_add and the address sync_write_
If add does not match, it is determined that no access collision occurs, and processing in the normal mode is continued. In the next step S11, the read address rsyn
A sync block is read from bank A based on c_add.

After the sync block has been read, in the next step S12, the address rsync_add is again set.
And the address sync_write_add are compared to detect whether they match. If it is detected in step S12 that these addresses match, it is determined that an access collision has occurred,
As in step S10 described above, the operation mode shifts to the avoidance mode.

On the other hand, if it is determined in step S12 that these addresses do not match, the process proceeds to step S12.
Then, the process proceeds to step S13, where the sync block read in step S11 is written to a predetermined address of bank 1 or bank 0. Then, in the next step S14, the read address rsync_add is incremented. The process returns to step S10 again, and the process in the normal mode is continued.

The above steps S10 and S1
2, the address rsync_add and the address sync
_Write_add matches,
The processing shifts to the avoidance mode. In the avoidance mode, first,
In step S15, a load signal is supplied from the address selector 24 to the jump address register 22, and the address rsync_add is set to the jump address rjmp_a.
dd is stored in the jump address register 22.

In the next step S16, the address rsy
nc_add is incremented, and step S17 is performed.
Then, in the bank A, the sync block is read from the incremented address rsync_add. As a result, the address where the access collision has occurred is skipped. When the sync block is read in step S17, the address rsync_add is incremented (step S18).

In the next step S19, the address wsy
It is determined whether nc_add has changed. That is, if it is determined in step S19 that the address wsync_add has not changed compared to the time in step S10 or step S12 described above, it is determined that the sync block is still being written to the address. . Therefore, if the address is set as the read address rsync_add, an access collision may occur. In this case, the process proceeds to step S20
Then, the writing of the sync block to the address is continued, and the process returns to step S17.
In step S17, a sync block is read from the address rsync_add incremented in step S18.

On the other hand, in step S19, the address wsyn
If c_add has changed, the process proceeds to step S2
Move to 1. In step S21, the read address rsync_add is stored. For example, a register seq_add (not shown) included in the address generation circuit 21
, The read address rsync_add is stored. The register seq_add stores the above-mentioned addresses rjmp_add and w in the jump address register 22.
You may make it provide as a register different from the register in which jmp_add is preserved.

In the next step S22, the jump address rjm stored in the jump address register 22 in the above-mentioned step S15 by the address selector 24.
p_add is set as the read address rsync_add. As a result, the read address is returned to the address at the time when the access collision occurred in step S10 or step S12 described above. Step S2
In step 3, the sync block is read from the read address rsync_add set as the jump address rjmp_add. The read sync block is SD
The data is written to a predetermined address in the bank 1 of the RAM 10 (step S24).

In the next step S25, the address stored in the register seq_add (not shown) in the above-mentioned step S21 is set as the read address rsync_add by the address selector 24. Then, the process returns to step S11, and the process in the normal mode is performed.

In the above description, the present invention has been described as being applied to the writing and reading of video data to and from a memory, but the present invention is not limited to this example. The present invention is also applicable to writing and reading other general data to and from a memory.

[0133]

As described above, according to the present invention, an access collision at the time of writing to a memory and reading from the memory is avoided by storing address data. Since only data to be stored is address data, there is an effect that access collision can be avoided with a small-scale memory configuration and circuit configuration.

In particular, when the present invention is applied to a digital video tape recorder, the head does not continuously reproduce sync blocks having the same address due to the recording characteristics of the digital video tape recorder. This has the effect of requiring only two pieces of address information.

Further, according to the present invention, the address information at which an access collision occurs is stored, and reading is performed from the next address. Therefore, there is no need to interrupt writing, and it is possible to stop both writing and reading accesses. There is an effect that access collision can be avoided without any problem.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration on a recording side of a recording / reproducing apparatus applicable to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a configuration on a reproducing side of a recording / reproducing apparatus applicable to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a diagram illustrating a deshuffling unit, an outer code decoder, and a memory related to access control of a memory according to the present invention;
It is a block diagram showing an example of composition of a deshuffling and depacking part.

FIG. 12 is a schematic diagram schematically illustrating the operation of an example of a sync block when shuttle reproduction is performed.

FIG. 13 is a time chart showing an example timing of processing in each unit when shuttle reproduction is performed.

FIG. 14 is a schematic diagram showing an access method of the SDRAM according to the present invention in which access collision is avoided.

FIG. 15 is a block diagram illustrating an example of a configuration of an access control circuit that controls access collision avoidance.

FIG. 16 is a flowchart showing an example of access control of the SDRAM according to the present invention.

FIG. 17 is a schematic diagram schematically showing an example of memory access using a bank.

[Explanation of symbols]

10 SDRAM, 11 SDRAM I /
O, 12: SYNC write control unit, 13: outer code decoder, 14: copy unit, 15A: depacking unit A, 15B: depacking unit B, 20
..Access control circuits, 21... Address generation circuits,
22: jump address register, 23: address status detection circuit, 24: address selector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/92 H04N 5/782 Z 5/937 5/92 H // G11B 20/18 544 5/93 C

Claims (2)

[Claims] 1. A data reproducing apparatus having a memory system configuration in which a plurality of modules may simultaneously access a data unit whose read and / or write is completed by accessing a plurality of times. And a memory that stores data in data units of a size that can be read and / or written by accessing the memory a plurality of times, and an address generation that generates a read address to access the memory next. Means for detecting a match between the read address generated by the address generating means and a write address being accessed to the memory from another module, or matching with the read address generated by the address generating means. Have, other An address comparing means for detecting a change in a write address accessing the memory from the module; and the address comparing means detecting that the write address accessing the memory from the other module is matched by the address comparing means. Address storage means for temporarily storing a read address; and switching between an address generated by the address generation means and an address stored by the address storage means in accordance with an address comparison result by the address comparison means. Address selecting means for outputting, monitoring a collision state between the write address and the read address, and interchanging the order of the read addresses while the write address and the read address collide. Data playback Location. 2. A data reproducing method having a memory system configuration in which a plurality of modules may simultaneously access a data unit whose read and / or write is completed by accessing a plurality of times. Can be accessed at the same time, and a memory for storing data in a memory in a data unit of a size that completes reading and / or writing by accessing a plurality of times can be used to generate a read address to be accessed next. Detecting the match between the read address generated in the address generation step and the write address being accessed to the memory from another module, or the read address generated in the address generation step. Match An address comparison step of detecting a change in a write address that is accessing the memory from another module; and a write address that is accessing the memory from the other module by the address comparison step. An address storage step of temporarily storing the read address detected as a match; an address generated by the address generation step in accordance with an address comparison result in the address comparison step; An address selection step of switching and outputting an address stored by a step, monitoring a collision state between the write address and the read address, and colliding the write address and the read address. While reading above Data reproduction method characterized by switching the order of the addresses.