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JP2001148511A - Semiconductor light-emitting diode - Google Patents

Semiconductor light-emitting diode

Info

Publication number
JP2001148511A
JP2001148511A JP32975599A JP32975599A JP2001148511A JP 2001148511 A JP2001148511 A JP 2001148511A JP 32975599 A JP32975599 A JP 32975599A JP 32975599 A JP32975599 A JP 32975599A JP 2001148511 A JP2001148511 A JP 2001148511A
Authority
JP
Japan
Prior art keywords
electrode
emitting diode
light emitting
layer
mesh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32975599A
Other languages
Japanese (ja)
Other versions
JP3989658B2 (en
JP2001148511A5 (en
Inventor
Ryoichi Takeuchi
良一 竹内
Wataru Nabekura
亙 鍋倉
Koji Hoshina
孝治 保科
Takashi Udagawa
隆 宇田川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP32975599A priority Critical patent/JP3989658B2/en
Priority to TW89121680A priority patent/TW477078B/en
Priority to US09/691,057 priority patent/US6512248B1/en
Publication of JP2001148511A publication Critical patent/JP2001148511A/en
Priority to US10/265,148 priority patent/US6677615B2/en
Publication of JP2001148511A5 publication Critical patent/JP2001148511A5/ja
Application granted granted Critical
Publication of JP3989658B2 publication Critical patent/JP3989658B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a high-luminance semiconductor LED, that preferentially and uniformly diffuses element drive current into an open light-emitting region in a semiconductor LED with a pedestal electrode and a window layer. SOLUTION: A conductive electrode is provided between a light-emitting part and a window layer, where the conductive electrode has an extraction hole part in an open light-emitting region, and is machined into a net shape.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体発光ダイオ
ードに関し、さらに詳しくは、結線用台座電極から供給
されるLED駆動電流を、窓層を介した発光部領域に広
範に拡散するための導電性電極の構成に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting diode, and more particularly, to a semiconductor light emitting diode for diffusing an LED driving current supplied from a connection pedestal electrode to a light emitting portion region through a window layer. The present invention relates to a configuration of an electrode.

【0002】[0002]

【従来の技術】酸化インジウム・錫(英略称:ITO)
などの導電性酸化物材料からなる窓層を備えたIII−
V族化合物半導体発光ダイオード(LED)にあって、
LED駆動電流は窓層の上表面に唯一配置された台座
(pad)電極から供給される構造となっている。しか
し、窓層を構成する酸化物層とLEDを構成するIII
−V族化合物半導体層とを直接、接合させる構成とする
と高い接合障壁が形成され、駆動電流を発光部に広範に
拡散できない。従って、徒に高い順方向電圧(所謂、V
f)が帰結される。例えば、窒化ガリウム(化学式:G
aN)に透明窓層としてITOを接合させた構成を具備
したGaN系LEDのVf(順方向電流=20mA)は
一般値の約2倍の7ボルト(単位:V)を越えるものと
なる(Appl.Phys.Lett.,74(26)
(1999)、3930〜3932頁参照)。これは、
低電圧で駆動できる透明導電性窓層を具備した高輝度の
GaN系LEDを得る際の妨げとなっている。
2. Description of the Related Art Indium tin oxide (abbreviation: ITO)
Having a window layer made of a conductive oxide material such as III-
Group V compound semiconductor light emitting diode (LED)
The LED drive current is supplied from a pedestal (pad) electrode solely disposed on the upper surface of the window layer. However, the oxide layer constituting the window layer and the III constituting the LED
If the structure is directly joined to the -V group compound semiconductor layer, a high junction barrier is formed, and the drive current cannot be widely diffused to the light emitting portion. Therefore, a very high forward voltage (so-called V
f) results. For example, gallium nitride (chemical formula: G
aN) with a structure in which ITO is bonded as a transparent window layer, the Vf (forward current = 20 mA) of a GaN-based LED exceeds 7 volts (unit: V) which is about twice the general value (Appl. Phys.Lett., 74 (26).
(1999), p. 3930-3932). this is,
This hinders obtaining a high-brightness GaN-based LED having a transparent conductive window layer that can be driven at a low voltage.

【0003】砒化ガリウム(化学式:GaAs)と略格
子整合するリン化アルミニウム・ガリウム・インジウム
混晶((AlXGa1-X0.5In0.5P(0≦X≦1))
を発光層とするAlGaInP系LEDでは、ITOか
らなる透明酸化物窓層の上表面上に唯一、備えられた台
座電極から供給される駆動電流を発光部へと効率的に流
通させるために、窓層とLED構成層との間にコンタク
ト(contact)層を配置する構成が知れている
(特開平11−17220号参照)。コンタクト層は窓
層とLEDを構成するIII−V族化合物半導体層との
オーミック(Ohmic)接触性を促進させるために設
けられ、GaAs、砒化リン化ガリウム(組成式:Ga
As1-CC:0≦C≦1)等から構成されるものとなっ
ている(上記の特開平11−17220号公報参照)。
しかし、従来のIII−V族化合物半導体LEDでは、
発光波長に対応するよりも禁止帯幅を小とするIII−
V族化合物半導体からなるコンタクト層が発光領域の表
面を被覆して敷設されているため(上記の特開平11−
17220号公報参照)、この構成ではコンタクト層に
因り発光が吸収され、高輝度のIII−V族化合物半導
体LEDを得るのに支障となっている。
An aluminum-gallium-indium phosphide mixed crystal ((Al x Ga 1 -x ) 0.5 In 0.5 P (0 ≦ X ≦ 1)) which is substantially lattice-matched with gallium arsenide (chemical formula: GaAs)
In the case of an AlGaInP-based LED having a light emitting layer, only a window is provided on the upper surface of a transparent oxide window layer made of ITO in order to efficiently drive a drive current supplied from a pedestal electrode provided to a light emitting portion. A configuration in which a contact layer is disposed between a layer and an LED constituent layer is known (see Japanese Patent Application Laid-Open No. H11-17220). The contact layer is provided to promote ohmic contact between the window layer and the III-V compound semiconductor layer constituting the LED, and is made of GaAs, gallium arsenide phosphide (composition formula: Ga).
As 1-C P C: 0 ≦ C ≦ 1) has a those composed of the like (see JP-A of JP-A 11-17220).
However, in the conventional group III-V compound semiconductor LED,
Making the band gap narrower than corresponding to the emission wavelength III-
Since a contact layer made of a group V compound semiconductor is laid so as to cover the surface of the light emitting region (see Japanese Patent Application Laid-Open No.
In this configuration, light emission is absorbed by the contact layer, which hinders obtaining a high-brightness III-V compound semiconductor LED.

【0004】また、特開平11−4020号公報に記載
される発明には、上表面に唯一、ボンディング用台座電
極が敷設されたITO透明電極層とLED構成層との間
に亜鉛(元素記号:Zn)等の金属膜を具備するAlG
aInPLEDが開示されている。この従来技術に依れ
ば、Zn等の金属膜はITO電極層とIII−V族化合
物半導体構成層との密着性を増強する目的で、発光領域
の全面に一様に万遍なく配置される構成となっている。
この様にITO透明電極層の直下に金属材料からなる連
続膜を配置する手段では、発光層からの発光が金属材料
膜に容赦なく吸収されてしまうため、高輝度のAlGa
InPLEDを得るに妨げとなる。
In the invention described in Japanese Patent Application Laid-Open No. 11-4020, zinc (element symbol: between the ITO transparent electrode layer on which the pedestal electrode for bonding is laid only on the upper surface and the LED constituting layer. AlG having a metal film such as Zn)
An aInPLED is disclosed. According to this conventional technique, a metal film of Zn or the like is uniformly arranged over the entire light emitting region for the purpose of enhancing the adhesion between the ITO electrode layer and the III-V compound semiconductor constituent layer. It has a configuration.
In such a method in which a continuous film made of a metal material is disposed immediately below the ITO transparent electrode layer, light emitted from the light emitting layer is relentlessly absorbed by the metal material film.
It is a hindrance to obtaining InPLED.

【0005】[0005]

【発明が解決しようとする課題】本発明は、発光部から
の発光を効率的に外部に取り出せ、且つ、発光部領域に
広範に駆動電流を拡散することができる素子の構成を提
供することを目的としている。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure of an element which can efficiently extract light emitted from a light emitting portion to the outside and can diffuse a drive current widely in a light emitting portion region. The purpose is.

【0006】[0006]

【課題を解決するための手段】本発明者らは、上記課題
を解決すべく鋭意努力検討した結果、本発明に到達し
た。即ち本発明は、[1]発光層、窓層、および結線用
台座電極を有する半導体発光ダイオードにおいて、素子
平面における台座電極の射影領域以外に網目状の導電性
電極を有することを特徴とする半導体発光ダイオード、
[2]素子の平面形状が、一辺の長さを150〜500
μmとした略正方形であることを特徴とする[1]に記
載の半導体発光ダイオード、[3]網目状の導電性電極
が、素子平面における台座電極の射影領域以外の略全面
に敷設されていることを特徴とする[1]または[2]
に記載の半導体発光ダイオード、[4]網目状の導電性
電極の素子平面における形状が、台座電極の射影領域の
中心点について点対称となっていることを特徴とする
[1]〜[3]の何れか1項に記載の半導体発光ダイオ
ード、[5]網目状の導電性電極の素子平面における形
状が、台座電極の射影領域の中心点を通る線について線
対称となっていることを特徴とする[1]〜[4]の何
れか1項に記載の半導体発光ダイオード、[6]発光層
がIII−V族化合物半導体から形成されていることを
特徴とする[1]〜[5]の何れか1項に記載の半導体
発光ダイオード、[7]窓層が、酸化物から形成された
層を含むことを特徴とする[1]〜[6]の何れか1項
に記載の半導体発光ダイオード、[8]網目状の導電性
電極が、金属から形成された層を含むことを特徴とする
[1]〜[7]の何れか1項に記載の半導体ダイオー
ド、[9]網目状の導電性電極の素子平面上における面
積の合計が、台座電極の底面積の、10〜500%の範
囲内であることを特徴とする[1]〜[8]の何れか1
項に記載の発光ダイオード、[10]素子平面上におい
て、網目状の導電性電極と台座電極の底部とを除く部分
の面積が、素子平面全体に対する面積の比率で30〜9
5%の範囲であることを特徴とする[1]〜[9]の何
れか1項に記載の発光ダイオード、[11]網目状の導
電性電極の素子平面における形状が、直径5〜200μ
mの範囲で円形に搾孔された領域を含むことを特徴とす
る[1]〜[10]の何れか1項に記載の半導体発光ダ
イオード、[12]網目状の導電性電極の素子平面にお
ける形状が、長径5〜200μmの範囲で楕円形に搾孔
された領域を含むことを特徴とする[1]〜[11]の
何れか1項に記載の半導体発光ダイオード、[13]網
目状の導電性電極の素子平面における形状が、一辺の長
さが5〜200μmの範囲で方形に搾孔された領域を含
むことを特徴とする[1]〜[12]の何れか1項に記
載の半導体発光ダイオード、[14]網目状の導電性電
極の素子平面における形状が、一辺の長さが5〜200
μmの範囲で多角形に搾孔された領域を含むことを特徴
とする[1]〜[13]の何れか1項に記載の半導体発
光ダイオード、[15]網目状の導電性電極の素子平面
における形状が、幅が5〜100μmの範囲で帯状に搾
孔された領域を含むことを特徴とする[1]〜[14]
の何れか1項に記載の半導体発光ダイオード、に関す
る。
Means for Solving the Problems The present inventors have made intensive studies to solve the above problems, and as a result, have reached the present invention. That is, the present invention provides [1] a semiconductor light-emitting diode having a light-emitting layer, a window layer, and a pedestal electrode for connection, wherein the semiconductor light-emitting diode has a mesh-shaped conductive electrode other than a projection region of the pedestal electrode on an element plane. Light emitting diode,
[2] The planar shape of the element has a side length of 150 to 500.
The semiconductor light-emitting diode according to [1], which is substantially square in μm, and [3] a mesh-shaped conductive electrode is laid on substantially the entire surface of the element plane other than the projection region of the pedestal electrode. [1] or [2]
[4] wherein the shape of the mesh-shaped conductive electrode in the element plane is point-symmetric with respect to the center point of the projection area of the pedestal electrode [1] to [3]. The semiconductor light-emitting diode according to any one of [1] to [5], wherein the shape of the mesh-shaped conductive electrode in the element plane is line-symmetric with respect to a line passing through the center point of the projection region of the pedestal electrode. The semiconductor light-emitting diode according to any one of [1] to [4], wherein the light-emitting layer is formed from a III-V compound semiconductor. [7] The semiconductor light emitting diode according to any one of [1] to [6], wherein the window layer includes a layer formed from an oxide. [8] the mesh-shaped conductive electrode is made of metal The semiconductor diode according to any one of [1] to [7], wherein [9] the total area of the mesh-shaped conductive electrodes on the element plane is equal to the pedestal electrode. Any one of [1] to [8], which is within a range of 10 to 500% of the bottom area.
Item [10] In the element plane, the area of the portion excluding the mesh-shaped conductive electrode and the bottom of the pedestal electrode is 30 to 9 in terms of the area ratio to the entire element plane.
The light emitting diode according to any one of [1] to [9], wherein the shape of the mesh-shaped conductive electrode in the element plane is 5 to 200 μm in diameter.
The semiconductor light-emitting diode according to any one of [1] to [10], wherein the semiconductor light-emitting diode according to any one of [1] to [10], wherein [12] a mesh-shaped conductive electrode in the element plane is included in a range of m. The semiconductor light-emitting diode according to any one of [1] to [11], wherein the shape includes an elliptical hole formed in a range of 5 to 200 μm in major axis, [13] mesh-like shape. The shape according to any one of [1] to [12], wherein the shape of the conductive electrode in the element plane includes a region which has a rectangular shape with a side length of 5 to 200 μm. The semiconductor light emitting diode, [14] the shape of the mesh-shaped conductive electrode in the element plane is 5 to 200
The semiconductor light-emitting diode according to any one of [1] to [13], including a region pierced into a polygon in a range of μm, [15] an element plane of a mesh-like conductive electrode. Is characterized by including a band-shaped region with a width of 5 to 100 μm [1] to [14].
A semiconductor light-emitting diode according to any one of the above.

【0007】[0007]

【発明の実施の形態】本発明に係わる半導体LEDは、
発光層、窓層、および結線用台座電極を有し、かつ素子
平面における台座電極の射影領域以外に網目状の導電性
電極を有することを特徴としている。特に本発明の構造
の半導体LEDは、砒化アルミニウム・ガリウム(組成
式AlXGa1-XAs:0≦X≦1)、砒化リン化ガリウ
ム(組成式:GaAs1-XX)、(AlXGa1-XY
1-YP、及び窒化アルミニウム・ガリウム・インジウ
ム(組成式AlXGaYIn1-X-YN:0≦X,Y≦1、
X+Y=1)等からなるIII−V族化合物から発光層
(発光部)を構成すると好ましい効果が得られる。発光
部を構成するIII−V族化合物半導体結晶層は、有機
金属熱分解気相成長法(MOCVD法)、分子線エピタ
キシャル成長法(MBE法)、ハロゲン(haloge
n)或いはハイドライド(hydride)気相成長法
等のエピタキシャル成長手段により成膜できる。図1は
本発明の請求項1に係わる第1の実施形態の概念的に説
明するためのIII−V族化合物半導体LED10の平
面模式図である。また、図2は、図1に掲示するLED
10の破線X−Yに沿った断面模式図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor LED according to the present invention comprises:
It has a light-emitting layer, a window layer, and a pedestal electrode for connection, and has a mesh-shaped conductive electrode in a region other than the projection region of the pedestal electrode on the element plane. Particularly, the semiconductor LED having the structure of the present invention includes aluminum gallium arsenide (composition formula: Al X Ga 1 -X As: 0 ≦ X ≦ 1), gallium arsenide phosphide (composition formula: GaAs 1-X P X ), (Al X Ga 1-X ) Y I
n 1-Y P and aluminum gallium indium nitride (composition formula: Al X Ga Y In 1-XY N: 0 ≦ X, Y ≦ 1,
When the light-emitting layer (light-emitting portion) is made of a group III-V compound composed of (X + Y = 1), a preferable effect can be obtained. The group III-V compound semiconductor crystal layer constituting the light emitting portion is formed by a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxial growth method (MBE method), a halogen (halo).
n) or a film can be formed by epitaxial growth means such as hydride vapor phase epitaxy. FIG. 1 is a schematic plan view of a group III-V compound semiconductor LED 10 for conceptually explaining a first embodiment according to claim 1 of the present invention. FIG. 2 shows the LED shown in FIG.
It is sectional schematic along the broken line XY of 10.

【0008】図2を利用して説明すると、本発明に係わ
るLED10は、単結晶からなる基板101の表面上に
エピタキシャル成長法に依り積層されたIII−V族化
合物半導体層からなるn形またはp形クラッド(cla
d)層104、106と発光層105とのヘテロ(he
tero)接合からなる発光部10aと、発光部10a
上に冠された窓層108とを基本的に備えているもので
ある。発光層104と緩衝層102との中間には、ブラ
ッグ反射(DBR)103を挿入した構成としても差し
支えはない。窓層108の上表面の中央部にはLED駆
動電流を供給するための台座電極109が設けられてい
る。本発明のLED10に特徴的なのは、窓層108を
なす透明酸化物層と接合をなすIII−V族化合物半導
体層106の表面上の開放発光領域106aに搾孔され
た開口部を有する網状の導電性電極107が敷設されて
いることにある。開放発光領域面106aとは、発光層
104からの発光が遮蔽されることなく外部に取り出せ
る領域を云う。即ち、窓層108上の台座電極109が
敷設されている領域の外周囲領域、または台座電極10
9の射影領域109a以外の領域が開放発光領域106
aである。なお、台座電極109の射影領域109aに
おいて本発明の網状の導電性電極107が施設されても
本発明の効果が得られる。この場合、Vfをさらに下げ
ることが可能となるが、台座電極により発光が遮蔽され
る部分への拡散電流が増加するため発光効率が若干低下
する。
Referring to FIG. 2, an LED 10 according to the present invention is an n-type or p-type LED made of a group III-V compound semiconductor layer laminated on a surface of a substrate 101 made of a single crystal by an epitaxial growth method. Clad
d) Hetero (he) between the layers 104 and 106 and the light emitting layer 105
tero) a light emitting unit 10a formed of a junction;
It basically has a window layer 108 crowned thereon. A structure in which a Bragg reflection (DBR) 103 is inserted between the light emitting layer 104 and the buffer layer 102 may be used. A pedestal electrode 109 for supplying an LED drive current is provided at the center of the upper surface of the window layer 108. The LED 10 according to the present invention is characterized in that a net-like conductive material having an opening formed in the open light emitting region 106 a on the surface of the group III-V compound semiconductor layer 106 joined to the transparent oxide layer forming the window layer 108. That is, the sex electrode 107 is laid. The open light emitting area surface 106a is an area where light emitted from the light emitting layer 104 can be extracted to the outside without being shielded. That is, the outer peripheral region of the region on the window layer 108 where the pedestal electrode 109 is laid, or the pedestal electrode 10
The area other than the projection area 109a of FIG.
a. Note that the effect of the present invention can be obtained even if the reticulated conductive electrode 107 of the present invention is provided in the projection region 109a of the pedestal electrode 109. In this case, Vf can be further reduced, but the luminous efficiency is slightly reduced because the diffusion current to the portion where light emission is blocked by the pedestal electrode increases.

【0009】また、本発明の更なる特徴は、開放発光領
域106aに設ける導電性電極(オーミック電極)10
7が、搾孔されて開口部を有する網状の膜から構成され
ていることにある。その開口部では、LEDを構成する
半導体層が露呈されることとなっている。例えば、図1
及び図2に例示するLED10にあっては、発光部10
aをなす上部クラッド層106が開口部に露呈してい
る。開放発光領域106aに敷設する導電性電極107
を、開口部を有する網状のオーミック電極107から構
成すれば、開口部を通過して発光は遮蔽されることなく
外部に導出される。従って、開放発光領域106aの平
面積の徒な減少が回避できる利点がある。本発明に用い
られる半導体LEDの好ましいチップ(chip)サイ
ズ(図1に記号Qで示す)は150〜500μm、より
好ましくは180〜300μmの範囲の略正方形であ
り、台座電極の好ましい大きさは底面形状が円形の場合
の直径に換算して80〜160μmの範囲である。略正
方形とは一辺の、他辺に対する比率が好ましくは0.8
〜1.2である長方形または正方形である。また、導電
性電極の開口部にあっては、好ましい開口部の形状は円
形、楕円形、方形、多角形、帯状であり、それぞれの大
きさは、円形の直径、楕円形の長径、方形の一辺の長
さ、多角形の一辺の長さで好ましくは5〜200μm、
より好ましくは5〜50μm、最も好ましくは5〜30
μmであり、開口部が帯状の場合では、幅が好ましくは
5〜100μm、より好ましくは5〜50μm、最も好
ましくは 5〜30μmである。
Further, a further feature of the present invention is that a conductive electrode (ohmic electrode) 10 provided in the open light emitting region 106a is provided.
7 consists of a mesh-like membrane which is squeezed and has an opening. The semiconductor layer constituting the LED is exposed in the opening. For example, FIG.
And the LED 10 illustrated in FIG.
The upper clad layer 106 forming a is exposed at the opening. Conductive electrode 107 laid in open light emitting area 106a
Is constituted by a mesh-like ohmic electrode 107 having an opening, light emitted through the opening is led out without being shielded. Therefore, there is an advantage that a sudden decrease in the plane area of the open light emitting region 106a can be avoided. The preferred chip size (indicated by the symbol Q in FIG. 1) of the semiconductor LED used in the present invention is approximately square in the range of 150 to 500 μm, more preferably 180 to 300 μm, and the preferred size of the pedestal electrode is the bottom surface. It is in the range of 80 to 160 μm in terms of diameter when the shape is circular. A substantially square means that the ratio of one side to the other side is preferably 0.8
It is a rectangle or square that is 〜1.2. In addition, in the opening of the conductive electrode, the preferred shape of the opening is a circle, an ellipse, a square, a polygon, a band, and the size of each is a circular diameter, an elliptical long diameter, and a rectangular shape. The length of one side, preferably the length of one side of the polygon is 5 to 200 μm,
More preferably 5 to 50 μm, most preferably 5 to 30 μm
μm, and in the case where the openings are strip-shaped, the width is preferably 5 to 100 μm, more preferably 5 to 50 μm, and most preferably 5 to 30 μm.

【0010】また、網目状の導電性電極の素子平面上に
おける面積の合計(素子平面上において導電性電極と台
座電極の底部が重なっている部分を含まない)が、台座
電極の底面積に対する比率で、好ましくは10〜500
%、より好ましくは20〜250%、最も好ましくは3
0〜150%の範囲内とし、更に、素子平面上におい
て、網目状の導電性電極と台座電極の底部とを除く部分
の面積が、素子平面全体に対する比率で、好ましくは3
0〜95%、より好ましくは35〜90%、最も好まし
くは40〜80%の範囲とすることでVfの低減と、発
光効率の向上をはかることが可能となる。
The total area of the mesh-shaped conductive electrodes on the element plane (excluding the portion where the bottoms of the conductive electrode and the pedestal electrode overlap on the element plane) is the ratio to the bottom area of the pedestal electrode. And preferably 10 to 500
%, More preferably 20-250%, most preferably 3%
In the range of 0 to 150%, the area of the portion excluding the mesh-shaped conductive electrode and the bottom of the pedestal electrode on the element plane is preferably 3% of the entire element plane.
By setting the range of 0 to 95%, more preferably 35 to 90%, and most preferably 40 to 80%, it becomes possible to reduce Vf and improve luminous efficiency.

【0011】導電性電極107は、アルミニウム(A
i)、ニッケル(元素記号:Ni)等から構成できる
が、特に、金(Au)合金から形成された層を含む構造
とすると、台座電極から供給された電流を発光層に効率
良く拡散でき好ましい。その中でも、n形半導体構成層
については、金(元素記号:Au)−ゲルマニウム(元
素記号:Ge)合金、金−インジウム(元素記号:I
n)合金或いは金−錫(元素記号:Sn)合金等の金合
金類から構成すると、オーミック接触性に優れる電極が
構成できる。またp形の半導体層については、金−亜鉛
(元素記号:Zn)合金または金−ベリリウム(元素記
号:Be)合金などからオーミック接触性に優れる電極
がもたらされる。本発明に係わる網状電極では、開口部
(搾孔部)以外は互いに連結しており、その連結部に於
いて電気的導通が確保されている。従って、発光を透過
させるための開口部を有しつつ、電気的導通を発揮する
オーミック接触性に優れる網状電極を開放発光領域10
6aの略全面に敷設する手段に依れば、台座電極109
より導電性透明酸化物窓層108を介して供給される駆
動電流を発光部10aに効率的に流通させることができ
る。良好なLED駆動電流の通流性を得るには、導電性
電極107をなす網状膜の膜厚を増加させて通流抵抗を
減ずる必要がある。開放発光領域106aの略全域に駆
動電流を拡散できる低抵抗を獲得するに必要な網状電極
膜の膜厚は5ナノメータ(単位:nm)以上である。網
状金属膜を極端に厚くすると、III−V族化合物半導
体構成層と網状金属膜との段差が大となり、後述する窓
層を構成する場合に網状膜の周囲を充分に被覆できない
不都合が発生する。このため、網状電極をなす膜の膜厚
は600nm以下とするのが望ましい。
The conductive electrode 107 is made of aluminum (A
i), nickel (element symbol: Ni) or the like, but a structure including a layer formed of a gold (Au) alloy is preferable because the current supplied from the pedestal electrode can be efficiently diffused into the light emitting layer. . Among them, for the n-type semiconductor constituent layer, a gold (element symbol: Au) -germanium (element symbol: Ge) alloy, gold-indium (element symbol: I)
An electrode having excellent ohmic contact can be formed by using an n) alloy or a gold alloy such as a gold-tin (element symbol: Sn) alloy. For the p-type semiconductor layer, an electrode having excellent ohmic contact is provided from a gold-zinc (element symbol: Zn) alloy or a gold-beryllium (element symbol: Be) alloy. In the mesh electrode according to the present invention, the portions other than the opening (the squeezed portion) are connected to each other, and electrical continuity is secured at the connection. Therefore, a mesh electrode having an ohmic contact and exhibiting electrical continuity and having excellent ohmic contact is provided in the open light emitting region 10 while having an opening for transmitting light emission.
According to the means for laying almost on the entire surface of the pedestal electrode 109,
The drive current supplied via the conductive transparent oxide window layer 108 can be more efficiently circulated to the light emitting unit 10a. In order to obtain good LED drive current flow, it is necessary to reduce the flow resistance by increasing the thickness of the reticulated film forming the conductive electrode 107. The thickness of the mesh electrode film required to obtain a low resistance capable of diffusing the drive current over substantially the entire open light emitting region 106a is 5 nanometers (unit: nm) or more. When the reticulated metal film is extremely thick, the step between the III-V compound semiconductor constituent layer and the reticulated metal film becomes large, and in the case of forming a window layer described later, there arises a problem that the periphery of the reticulated film cannot be sufficiently covered. . For this reason, it is desirable that the thickness of the film forming the mesh electrode be 600 nm or less.

【0012】開放発光領域106aでの電界分布をより
均等とするために、導電性電極107をなす網状膜に於
ける開口部(搾孔部)の素子平面における形状は、台座
電極109(台座電極109の射影領域109a)の中
心点Mについて点対称、または中心点Mを通る何れかの
中心線C1、C2に線対称の関係に配置されているのが
望ましい。さらに上記の開口部は、複数個設置するのが
望ましい。また、開口部は開放発光領域106aに於い
て、互いに等間隔(=d)に位置させるのが、開放発光
領域106aで均一な電界強度分布を形成する上で好都
合である。更には、台座電極109(台座電極の射影領
域109a)の平面形状の中心点Mから等距離(=R)
を保ちつつ、相互に等しい間隔(=d)に配置するのが
更に好都合である。均一な電界強度分布は開放発光領域
106aでの均一な強度の発光をもたらすのに貢献でき
る。また、搾孔部を設ける間隔を極端に短縮すると、即
ち、隣接する搾孔部間の間隔を極端に小として、金属膜
の連結部の幅を減ずることとすると、動作電流の通流に
対し抵抗が増加し、開放発光領域106aの全域に充分
に動作電流を拡散できない不都合が発生する。また、例
えば、間隔が5μm或いはそれ以下の小ささであると微
細加工時に搾孔部間の金属連結部が断裂する確率が増
し、動作電流の広範囲に亘る拡散が定常的に達成されな
い場合が発生する。
In order to make the electric field distribution in the open light emitting region 106a more uniform, the shape of the opening (hole) in the reticulated film forming the conductive electrode 107 in the element plane is the pedestal electrode 109 (the pedestal electrode). It is desirable that the projection areas 109a) are arranged point-symmetrically with respect to the center point M of the projection area 109a, or line-symmetrically with any of the center lines C1 and C2 passing through the center point M. Further, it is desirable to provide a plurality of the above-mentioned openings. In addition, it is convenient to arrange the openings at equal intervals (= d) in the open light emitting region 106a in order to form a uniform electric field intensity distribution in the open light emitting region 106a. Furthermore, equidistant (= R) from the center point M of the planar shape of the pedestal electrode 109 (projection region 109a of the pedestal electrode).
It is more convenient to arrange them at equal intervals (= d) while maintaining the following. A uniform electric field intensity distribution can contribute to providing uniform intensity light emission in the open light emitting region 106a. Further, when the interval between the holes is extremely reduced, that is, when the interval between the adjacent holes is extremely small and the width of the connecting portion of the metal film is reduced, the flow of the operating current is reduced. The resistance increases, and there arises a problem that the operating current cannot be sufficiently diffused over the entire open light emitting region 106a. In addition, for example, if the interval is as small as 5 μm or less, the probability that the metal connection portion between the squeezed portions breaks during micromachining increases, and a case where diffusion of the operating current over a wide range may not be achieved constantly occurs. I do.

【0013】導電性電極107を覆う窓層108はGa
P、AlGaAs、金属酸化物等から構成することがで
きるが、特に酸化物から形成された層を含む構成とする
ことが好ましく、この中では、酸化インジウム(In2
3)、酸化錫(SnO2)、酸化インジウム・錫(IT
O)等の導電性の透明酸化物材料から構成することが特
に好ましい。また、アルミニウム(元素記号:Al)、
ガリウム(元素記号:Ga)、またはインジウム(元素
記号:In)をドーピングして低抵抗率とした酸化亜鉛
(化学式:ZnO)も好適に利用できる。上表面に設け
る台座電極109より供給されるLED駆動電流を網状
の導電性電極107に流通させるために、窓層108は
約1×10-3オーム・センチメートル(Ω・cm)以
下、望ましくは約5×10-4Ω・cm程度の低抵抗率の
材料から構成する。また、III−V族化合物半導体発
光層から放射される近紫外帯光、青色帯光或いは緑色帯
光などの短波長発光を外部に充分に取り出すために作用
を発揮させるには、窓層108は禁止帯幅を大凡、3エ
レクトロンボルト(単位:eV)以上とする材料から構
成するのが好ましい。ちなみにITOと酸化亜鉛の室温
での禁止帯幅は約3.4〜3.5eVである。窓層10
8を構成する導電性酸化物層の層厚は、発光波長に対し
高い透過率を与える厚さに設定する。
The window layer 108 covering the conductive electrode 107 is Ga
Although it can be composed of P, AlGaAs, metal oxide, or the like, it is particularly preferable to have a constitution including a layer formed of an oxide. In this case, indium oxide (In 2 oxide) is preferable.
O 3 ), tin oxide (SnO 2 ), indium tin oxide (IT
It is particularly preferable to use a conductive transparent oxide material such as O). Aluminum (element symbol: Al),
Zinc oxide (chemical formula: ZnO), which is doped with gallium (element symbol: Ga) or indium (element symbol: In) and has a low resistivity, can also be suitably used. In order to allow the LED driving current supplied from the pedestal electrode 109 provided on the upper surface to flow through the mesh-like conductive electrode 107, the window layer 108 is about 1 × 10 −3 ohm-cm (Ω · cm) or less, preferably It is made of a material having a low resistivity of about 5 × 10 −4 Ω · cm. The window layer 108 needs to have an effect to sufficiently take out short-wavelength light such as near-ultraviolet light, blue light, or green light emitted from the III-V compound semiconductor light-emitting layer to the outside. It is preferable to use a material having a band gap of approximately 3 electron volts (unit: eV) or more. Incidentally, the band gap of ITO and zinc oxide at room temperature is about 3.4 to 3.5 eV. Window layer 10
The thickness of the conductive oxide layer constituting 8 is set to a thickness that gives a high transmittance to the emission wavelength.

【0014】窓層108の上表面に設ける台座電極10
9の平面形状は一般的な円形、楕円形或いは、正方形ま
たは長方形などの方形に加え、正六角形や正八角形等の
多角形とすることができる。何れの平面形状を選択する
にしても、左右対称となる開放発光領域106aをもた
らす様に、台座電極109の平面形状は左右対称形であ
るのが望ましい。また、何れの平面形状の台座電極10
9にあっても、容易に結線が達成でき、且つ開放発光領
域106aの表面積の徒な減少を招くことのない様に、
円形台座電極では直径、楕円形台座電極では長径、正方
形の台座電極では一辺の長さ、長方形の台座電極では短
辺の長さ、多角形の台座電極では対角線の長さを少なく
とも約80〜160μmの範囲とすることが望ましい。
The pedestal electrode 10 provided on the upper surface of the window layer 108
The plane shape of 9 can be a polygon such as a regular hexagon or a regular octagon in addition to a general circle, an ellipse, or a square such as a square or a rectangle. Whichever planar shape is selected, the planar shape of the pedestal electrode 109 is desirably bilaterally symmetric so as to provide an open light-emitting region 106a that is bilaterally symmetric. In addition, the pedestal electrode 10 of any planar shape
9 so that the connection can be easily achieved and the surface area of the open light emitting region 106a is not reduced unnecessarily.
The diameter of a circular pedestal electrode, the major axis of an elliptical pedestal electrode, the length of one side of a square pedestal electrode, the length of a short side of a rectangular pedestal electrode, and the length of a diagonal line of a polygonal pedestal electrode are at least about 80 to 160 μm. It is desirable to be within the range.

【0015】一方、網状膜からなる上記の導電性電極1
07とは極性を反対とする他の導電性電極110は、用
いる基板101がn形またはp形の導電性結晶である場
合、基板101の裏面に設けられる。基板101の裏面
に敷設される導電性電極110は、基板裏面の表面の略
全面に亘り設けられるのが一般的である。不導体或いは
絶縁性の基板101である場合、導電性電極110は基
板101上に積層されたn形或いはp形の、導電性のI
II−V族化合物半導体構成層の一部領域上に敷設され
るのが一般的である。
On the other hand, the above-mentioned conductive electrode 1 made of a reticulated film
Another conductive electrode 110 whose polarity is opposite to that of 07 is provided on the back surface of the substrate 101 when the substrate 101 to be used is an n-type or p-type conductive crystal. The conductive electrode 110 laid on the back surface of the substrate 101 is generally provided over substantially the entire surface of the back surface of the substrate. In the case of a non-conductive or insulating substrate 101, the conductive electrode 110 is an n-type or p-type conductive I
It is generally laid on a part of the II-V compound semiconductor constituent layer.

【0016】本発明の請求項11に係わる第11の実施
形態は、円形に搾孔された領域を含む網状の電極から導
電性電極を構成することを特徴としている。図3に本実
施形態に係わる導電性電極107を備えたIII−V族
化合物半導体LED20の平面模式図を例示する。円形
の搾孔部111が円形の台座電極109(台座電極10
9の射影領域109a)の、平面形状の中心点Mを通過
する中心線C1、C2(対角線L1、L2)に対して線
対称の関係となる位置に設けられている。円形の搾孔部
111は即ち、開口部であり、直下のIII−V族化合
物半導体構成層が露呈している領域となっている。従っ
て、発光部から出射される発光を遮蔽することのない構
成となっている。図3に例示した網状電極では、搾孔部
は全て同一の直径を有する円形としているが、必ずしも
全ての搾孔部の平面形状を同一とする必要はない。例え
ば、台座電極の周囲の、LEDの中央付近の搾孔部を円
形とし、LEDの周縁部辺の搾孔部を楕円形とした網状
電極からも導電性電極は構成できる。搾孔部の平面形状
或いは搾孔面積(開口面積)を開放発光領域内で領域に
依って変化させるにしても、帰結される網状電極は中心
線(C1、C2)或いは対角線(L1、L2)に対して
左右対称とするのが最適である。開放発光領域106a
に於ける電位分布を均等となすためである。
An eleventh embodiment according to the eleventh aspect of the present invention is characterized in that the conductive electrode is constituted by a mesh-like electrode including a circular hole. FIG. 3 illustrates a schematic plan view of a III-V compound semiconductor LED 20 including the conductive electrode 107 according to the present embodiment. The circular hole 111 has a circular pedestal electrode 109 (the pedestal electrode 10).
Nine projection areas 109a) are provided at positions that are line-symmetric with respect to the center lines C1 and C2 (diagonal lines L1 and L2) passing through the center point M of the planar shape. In other words, the circular hole 111 is an opening, and is a region where the group III-V compound semiconductor constituent layer immediately below is exposed. Therefore, the configuration does not block light emitted from the light emitting unit. In the reticulated electrode illustrated in FIG. 3, all the holes have circular shapes having the same diameter, but it is not necessary that all the holes have the same planar shape. For example, the conductive electrode can also be formed from a mesh electrode in which the hole near the center of the LED around the pedestal electrode is circular and the hole near the periphery of the LED is elliptical. Even if the plane shape or the hole area (opening area) of the hole portion is changed depending on the region in the open light emitting region, the resulting reticulated electrode is the center line (C1, C2) or the diagonal line (L1, L2). Is optimally symmetric with respect to. Open light emitting area 106a
This is to make the potential distribution in the first embodiment uniform.

【0017】本発明の請求項12に係わる第12の実施
形態では、楕円形に搾孔された領域を含む網状の電極か
ら導電性電極を構成することとする。搾孔部の平面形状
を上記の第10の実施形態に記す如く円形とする、或い
は本実施形態の様に楕円形となすことにより、左右対称
の形状を有する網状の電極が容易にもたらされるからで
ある。図4に本実施形態に係わる楕円形の搾孔部112
を有する導電性電極107を備えたIII−V族化合物
半導体LED30の平面構造を模式的に示す。楕円形の
搾孔部112は、その長径112aをLED30の中心
線C1、C2または対角線L1、L2の何れかに平行に
して設けた導電性電極107は、全て正楕円形に搾孔し
たものであるが、円形の搾孔部と楕円形の搾孔部とを備
えた網状電極からも構成できる。
According to a twelfth embodiment of the present invention, the conductive electrode is constituted by a mesh electrode including an elliptical hole. By making the plane shape of the hole portion circular as described in the tenth embodiment or by making it elliptical as in the present embodiment, a net-like electrode having a symmetrical shape can be easily provided. It is. FIG. 4 shows an elliptical hole 112 according to this embodiment.
1 schematically shows a planar structure of a group III-V compound semiconductor LED 30 provided with a conductive electrode 107 having: The elliptical hole 112 has a conductive electrode 107 whose major axis 112a is parallel to any of the center lines C1 and C2 or the diagonal lines L1 and L2 of the LED 30. However, it can also be constituted by a mesh electrode having a circular hole and an elliptical hole.

【0018】本発明の請求項13に係わる第13の実施
形態では、方形に搾孔された領域113を含む網状の電
極から導電性電極を構成する。図5に本実施形態に係わ
る導電性電極107を備えたIII−V族化合物半導体
LED40の平面模式図を示す。図4に例示する導電性
電極107は正方形に搾孔された網状金属膜から構成さ
れているが、搾孔部は長方形としても差し支えない。正
方形と長方形の搾孔部を備えた網状膜からも導電性電極
を構成できる。形状を異にする開口部を設ける場合、開
口部の形状並びに位置は中心線C1、C2、或いは対角
線L1、L2に対して線対称となる様に設ける。開放発
光領域106aでの均等な電位分布を形成するためであ
る。台座電極の射影領域109aに於ける発光は台座電
極109に遮蔽されて外部へ取り出せないため、台座電
極109の直下に動作電流を流通させたところで、発光
強度の向上は殆ど達成できない。本発明の如く、開放発
光領域106aに限定して、且つ優先的に動作電流を流
通できる形状の導電性電極を配置すれば、開放発光領域
106aの略全域に亘り拡散でき高発光強度のIII−
V族化合物半導体LEDを得るのに有利となる。
According to a thirteenth embodiment of the present invention, the conductive electrode is constituted by a mesh-like electrode including a region 113 which has been squarely bored. FIG. 5 is a schematic plan view of a group III-V compound semiconductor LED 40 including the conductive electrode 107 according to the present embodiment. Although the conductive electrode 107 illustrated in FIG. 4 is formed of a reticulated metal film formed into a square, the hole may be rectangular. The conductive electrode can also be formed from a reticulated membrane having square and rectangular holes. When an opening having a different shape is provided, the shape and position of the opening are provided so as to be line-symmetric with respect to the center lines C1, C2 or the diagonal lines L1, L2. This is for forming a uniform potential distribution in the open light emitting region 106a. Since the light emission in the projection region 109a of the pedestal electrode is shielded by the pedestal electrode 109 and cannot be extracted to the outside, the improvement of the luminescence intensity can hardly be achieved when the operating current is passed immediately below the pedestal electrode 109. As in the present invention, by disposing a conductive electrode limited to the open light emitting region 106a and having a shape through which an operation current can flow preferentially, it can diffuse over substantially the entire open light emitting region 106a and have a high light emission intensity.
This is advantageous for obtaining a group V compound semiconductor LED.

【0019】本発明の請求項14に係わる第14の実施
形態では、多角形に搾孔された領域を含む網状の電極か
ら導電性電極を構成する。特に、搾孔部の形状は、正六
角形、正八角形等の左右対称形の多角形とするのが左右
対称の平面形状の網状電極を得る上で好適である。図6
に本実施例に係わる正六角形の搾孔部114を有する導
電性電極107を備えたLED50を例示する。多角形
状に搾孔された領域以外の領域は連結部であるため、動
作電流を、この部位を導路として開放発光領域106a
の略全域に均等に一様に拡散させることができる。ま
た、図7に台座電極109の射影領域109a以外の開
放発光領域106aにあって、射影領域109aの周辺
領域に正六角形状の搾孔部114を有し、開放発光領域
106aの周縁領域に円形の111を設けてなる網状膜
からなる導電性電極107を備えたLED60の平面構
成を模式的に例示する。台座電極109の直下に在る射
影領域109aでは、窓層108と半導体構成層とが直
接、接触をなし、高い接合障壁を構成している。このた
め、台座電極109より供給されるLED動作電流は台
座電極の射影領域109aよりも開放発光領域106a
に優先的に流通され得る。従って、発光の外部取り出し
効率の向上が果たせ、高発光強度の半導体LEDが得ら
れる。
According to a fourteenth embodiment of the present invention, the conductive electrode is constituted by a mesh-like electrode including a polygonally punched region. In particular, it is preferable that the shape of the hole is a bilaterally symmetric polygon such as a regular hexagon or regular octagon in order to obtain a net-like electrode having a symmetrical planar shape. FIG.
An LED 50 having a conductive electrode 107 having a regular hexagonal hole 114 according to the present embodiment will be exemplified. Since the region other than the region pierced in the polygonal shape is a connecting portion, the operating current is supplied to the open light emitting region 106 a
Can be evenly and uniformly diffused over substantially the entire area. FIG. 7 shows an open light emitting area 106a other than the projection area 109a of the pedestal electrode 109, a regular hexagonal hole 114 in a peripheral area of the projection area 109a, and a circular area around the open light emitting area 106a. 2 schematically illustrates a planar configuration of the LED 60 provided with the conductive electrode 107 formed of a reticulated film provided with 111. In the projection region 109a located immediately below the pedestal electrode 109, the window layer 108 and the semiconductor constituent layer are in direct contact with each other, forming a high junction barrier. For this reason, the LED operating current supplied from the pedestal electrode 109 is larger than the projection area 109a of the pedestal electrode in the open light emitting area 106a.
Can be distributed preferentially. Therefore, the efficiency of external emission of light can be improved, and a semiconductor LED with high light emission intensity can be obtained.

【0020】本発明の請求項15に係わる第15の実施
形態では、帯状に搾孔された領域を含む網状の電極から
導電性電極を構成する。帯状の搾孔部115はLEDの
中心線C1、C2または対角線L1、L2に平行に配置
するのが好適である。図8に一中心線C1に平行な方向
に沿って帯状に搾孔された網状電極を備えたLED70
を例示する。また、図9の平面模式図に示すLED80
は、両中心線C1、C2に平行に設けた帯状の搾孔部1
15を有する導電性電極107を備えたものである。ま
た、図10に中心線C1、C2に平行な帯状の搾孔部1
15を縦横に組み合わせてなる開口部を有する導電性電
極107を備えたLED90を例示する。何れの平面形
状とするにしても搾孔部以外は連結した金属膜から構成
する必要がある。開放発光領域106aの全域に亘り広
範にLED駆動電流の拡散を果たすためである。
According to a fifteenth embodiment of the present invention, the conductive electrode is constituted by a mesh electrode including a band-shaped hole. It is preferable that the strip-shaped hole 115 is disposed in parallel with the center lines C1, C2 or the diagonal lines L1, L2 of the LED. FIG. 8 shows an LED 70 having a reticulated electrode formed in a strip along a direction parallel to the center line C1.
Is exemplified. The LED 80 shown in the schematic plan view of FIG.
Is a band-shaped hole 1 provided in parallel with both center lines C1 and C2.
15 is provided. FIG. 10 shows a band-shaped hole 1 parallel to the center lines C1 and C2.
15 illustrates an LED 90 including a conductive electrode 107 having an opening formed by combining the vertical and horizontal lines 15. Regardless of the plane shape, it is necessary to form a connected metal film except for the hole. This is to diffuse the LED driving current widely over the entire open light emitting region 106a.

【0021】[0021]

【実施例】(実施例1)以下、本発明を、実施例を基に
詳細に説明する。図11に本実施例に係わるAlGaI
nP系LED100の平面模式図を示す。また、図12
は図11に示すLED100の破線A−A’に沿った断
面模式図である。
EXAMPLES (Example 1) Hereinafter, the present invention will be described in detail based on examples. FIG. 11 shows the AlGaI according to this embodiment.
1 shows a schematic plan view of an nP LED 100. FIG. FIG.
FIG. 12 is a schematic cross-sectional view of the LED 100 shown in FIG. 11 taken along a broken line AA ′.

【0022】LED100は、直径約50mmの亜鉛
(Zn)ドープp形(001)−GaAs単結晶円形基
板201上に順次、積層されたZnドープp形GaAs
緩衝層202、何れもZnをドーピングしたp形Al
0.40Ga0.60As層とp形Al0. 95Ga0.05As層とを
交互に12層積層した周期構造からなるブラッグ反射
(DBR)層203、Znドープp形(Al0.7
0.30.5In0.5Pから成る下部クラッド層204、
アンドープのn形(Al0.2Ga0.80.5In0.5P混晶
から成る発光層205、及びSiドープn形(Al0.7
Ga0.30.5In0.5Pから成る上部クラッド層206
から構成されるエピタキシャル積層構造体(ウェハ)1
Aを母体材料として構成した。
The LED 100 has a Zn (Zn) -doped p-type (001) -GaAs single crystal circular substrate 201 having a diameter of about 50 mm, and is sequentially stacked on a Zn-doped p-type GaAs.
Buffer layer 202, both p-type Al doped with Zn
0.40 Ga 0.60 As layer Bragg reflector consisting of 12 layers stacked periodic structure alternately and p-type Al 0. 95 Ga 0.05 As layer (DBR) layer 203, Zn-doped p-type (Al 0.7 G
a 0.3 ) a lower cladding layer 204 made of 0.5 In 0.5 P;
A light-emitting layer 205 composed of an undoped n-type (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P mixed crystal, and a Si-doped n-type (Al 0.7
An upper cladding layer 206 made of Ga 0.3) 0.5 In 0.5 P
Laminated structure (wafer) 1 composed of
A was configured as a base material.

【0023】積層構造体1Aを構成する各構成層202
〜206はトリメチルアルミニウム((CH33
l)、トリメチルガリウム((CH33Ga)及びトリ
メチルインジウム((CH33In)をIII族構成元
素の原料とする減圧MOCVD法により成膜した。亜鉛
(Zn)のドーピング源にはジエチル亜鉛((C25
2Zn)を利用した。珪素(Si)のドーパント源には
ジシラン(Si26)を使用した。各構成層202〜2
06の成膜温度は730℃に統一した。緩衝層202の
キャリア濃度は約5×1018cm-3に、また、層厚は約
1μmとした。DBR層203をなすn形Al0.40Ga
0.60As層とn形Al0.95Ga0.05As層の層厚は各
々、約40nmとした。キャリア濃度は各々、約1×1
18cm-3とした。下部クラッド層204のキャリア濃
度は約3×1018cm-3に、また、層厚は約1.5μm
とした。発光層205の層厚は約15nmとし、キャリ
ア濃度は約5×1016cm-3とした。n形上部クラッド
層206のキャリア濃度は約2×1018cm-3とし、ま
た、層厚は約5μmとした。
Each constituent layer 202 constituting the laminated structure 1A
To 206 are trimethyl aluminum ((CH 3 ) 3 A)
l), trimethylgallium ((CH 3 ) 3 Ga) and trimethyl indium ((CH 3 ) 3 In) were formed by a low-pressure MOCVD method using a group III constituent element as a raw material. Diethyl zinc ((C 2 H 5 )) is used as a zinc (Zn) doping source.
2 Zn) was used. Disilane (Si 2 H 6 ) was used as a silicon (Si) dopant source. Each constituent layer 202-2
The film forming temperature of No. 06 was unified to 730 ° C. The carrier concentration of the buffer layer 202 was about 5 × 10 18 cm −3 , and the layer thickness was about 1 μm. N-type Al 0.40 Ga forming the DBR layer 203
The thickness of each of the 0.60 As layer and the n-type Al 0.95 Ga 0.05 As layer was about 40 nm. Each carrier concentration is about 1 × 1
0 18 cm −3 . The lower cladding layer 204 has a carrier concentration of about 3 × 10 18 cm −3 and a thickness of about 1.5 μm.
And The thickness of the light emitting layer 205 was about 15 nm, and the carrier concentration was about 5 × 10 16 cm −3 . The carrier concentration of the n-type upper cladding layer 206 was about 2 × 10 18 cm −3, and the layer thickness was about 5 μm.

【0024】n形上部クラッド層206の表面の全面
に、一般的な真空蒸着法により膜厚を約50nmとする
金・ゲルマニウム合金(Au95重量%−Ge5重量%
合金)膜を被着させた。続けて、膜厚を約50nmとす
る金(Au)被膜を上記のAu−Ge合金膜の表面上に
被着させた。次に、一般的なフォトリソグラフィー手段
を利用してAu−Ge/Au重層膜にパターニングを施
し、第1及び第2の円弧状の搾孔部207a、207b
と円形の搾孔部207cとを併在させた導電性電極20
7を形成した。第1の円弧状搾孔部207aは台座電極
209の射影領域209aの、平面形状の中心Mを中心
とする直径180μmの円周上に設けた。第1の円弧状
搾孔部207aはLED100の両中心線C1、C2に
対し左右対称となる様に配置した。第1の円弧状搾孔部
207aの幅は約50μmとし、第1の円弧207aの
円周に沿った円弧の長さは約95μmとした。第2の円
弧状の搾孔部207bは台座電極の射影領域209aの
中心Mを中心とする直径220μmの円周上の計4箇所
に設けた。第2の円弧状の搾孔部207bはLED10
0の両対角線C1、C2に対し左右対称となる様に配置
した。第2の円弧状の、搾孔部207bの幅は約60μ
mとし、円弧の長さは約115μmとした。第2の円弧
状の搾孔部207bとLED100の外縁部100bと
の中間には、直径を30μmとする円形の搾孔部207
cを設けた。円形の搾孔部207cはLED100の両
対角線C1,C2上に中心を置いて設けた。
A gold-germanium alloy (Au 95% by weight-Ge 5% by weight) having a thickness of about 50 nm is formed on the entire surface of the n-type upper cladding layer 206 by a general vacuum deposition method.
Alloy) film was deposited. Subsequently, a gold (Au) film having a thickness of about 50 nm was applied on the surface of the Au-Ge alloy film. Next, the Au—Ge / Au multilayer film is patterned by using general photolithography means, and the first and second arc-shaped holes 207a and 207b are formed.
And a conductive electrode 20 in which a circular hole 207c coexists
7 was formed. The first arc-shaped hole 207a was provided on the circumference of the projection area 209a of the pedestal electrode 209 having a diameter of 180 μm centered on the center M of the planar shape. The first arc-shaped holes 207a are arranged symmetrically with respect to both center lines C1 and C2 of the LED 100. The width of the first arc-shaped hole 207a was about 50 μm, and the length of the arc along the circumference of the first arc 207a was about 95 μm. The second arc-shaped holes 207b were provided at a total of four places on a circumference of 220 μm in diameter centered on the center M of the projection region 209a of the pedestal electrode. The second arc-shaped hole 207b is the LED 10
They are arranged so as to be bilaterally symmetrical with respect to both diagonal lines C1 and C2 of 0. The width of the second arc-shaped hole 207b is about 60 μm.
m, and the length of the circular arc was about 115 μm. A circular hole 207 having a diameter of 30 μm is provided between the second arc-shaped hole 207b and the outer edge 100b of the LED 100.
c was provided. The circular hole 207c is provided at the center on both diagonal lines C1 and C2 of the LED 100.

【0025】LED100の一辺の長さ(=Q)は26
0μmとし、また、台座電極209の直径は110μm
としたため、台座電極の射影領域209aを除いた開放
発光領域206aの表面積は約5.8×10-4cm2
なった。また、上記の第1及び第2の円弧状搾孔部20
7a、207bと円形の搾孔部207cとの合計の面積
は約2.4×10-4cm2である。従って、開放発光領
域206aの表面積に占める搾孔部の平面積の割合は約
41.3%となった。また素子平面上における導電性電
極207と台座電極209の底部とを除く部分の、素子
平面全体に対する比率は約50%となった。
The length of one side of the LED 100 (= Q) is 26
0 μm, and the diameter of the pedestal electrode 209 is 110 μm
Therefore, the surface area of the open light emitting area 206a excluding the projection area 209a of the pedestal electrode was about 5.8 × 10 −4 cm 2 . In addition, the first and second arc-shaped holes 20
The total area of 7a, 207b and circular hole 207c is about 2.4 × 10 −4 cm 2 . Therefore, the ratio of the plane area of the squeezed portion to the surface area of the open light emitting region 206a was about 41.3%. In addition, the ratio of the portion excluding the conductive electrode 207 and the bottom of the pedestal electrode 209 on the element plane to the entire element plane was about 50%.

【0026】次に、導電性電極207を配置した上部ク
ラッド層206の表面上に、一般のマグネトロンスパッ
タリング法により透明窓層208とする酸化インジウム
・錫(ITO)膜を被着させた。ITO層の比抵抗は約
5×10-4Ω・cmであり、層厚は約600nmとし
た。次に、窓層208上の全面に一般的な有機フォトレ
ジスト材料を塗布した後、台座電極209を設けるべき
領域を、公知のフォトリソグラフィー技術を利用してパ
ターニングした。然る後、パターニングされたレジスト
材料を残置させたままで、全面に金(Au)膜を真空蒸
着法により被着させた。金(Au)膜の厚さは約700
nmとした。その後、周知のリフト−オフ(lift−
off)手段に依り、レジスト材料を剥離するに併せて
台座電極209の形成予定領域に限定してAu膜を残留
させた。これより、直径を約110μmとする円形の台
座電極209を形成した。台座電極209の底面積は約
0.95×10-4cm2となった。また導電性電極20
7の合計面積の、台座電極の底面積に対する比率は約3
58%となった。
Next, an indium tin oxide (ITO) film serving as a transparent window layer 208 was applied on the surface of the upper cladding layer 206 on which the conductive electrode 207 was disposed by a general magnetron sputtering method. The specific resistance of the ITO layer was about 5 × 10 −4 Ω · cm, and the layer thickness was about 600 nm. Next, after a general organic photoresist material was applied to the entire surface of the window layer 208, a region where the pedestal electrode 209 was to be provided was patterned using a known photolithography technique. Thereafter, a gold (Au) film was deposited on the entire surface by a vacuum deposition method while the patterned resist material was left. The thickness of the gold (Au) film is about 700
nm. Thereafter, the well-known lift-off (lift-off) is performed.
By means of off) means, the Au film was left only in the area where the pedestal electrode 209 was to be formed, while the resist material was peeled off. Thus, a circular pedestal electrode 209 having a diameter of about 110 μm was formed. The base area of the pedestal electrode 209 was about 0.95 × 10 −4 cm 2 . Also, the conductive electrode 20
The ratio of the total area of No. 7 to the bottom area of the pedestal electrode is about 3
It was 58%.

【0027】p形GaAs単結晶基板201の裏面に金
・亜鉛(Au・Zn)合金からなるp形導電性電極21
0を形成した後、通常のスクライブ法により積層構造体
(ウェハ)1Aを裁断して個別に細分化し、LEDチッ
プ100となした。チップ(個別素子)100は一辺の
長さ(=Q)を260μmとする正方形とした。p形導
電性電極210と台座電極209を介してn形の導電性
電極207間に順方向に電流を通流して、開放発光領域
206aを通して波長を約620nmとする赤橙色の発
光を得た。発光スペクトルの半値幅は約20nmであ
り、単色性に優れる発光であった。20ミリアンペア
(mA)の電流を通流した際の順方向電圧(Vf:@2
0mA)は、網状金属膜からなる導電性電極207の良
好なオーミック特性を反映して約2.1ボルト(V)と
なった。また、導電性電極207を搾孔部を有する網状
の金属膜から構成したことに依り、チップ100の周縁
100bの領域に於いても発光が認められ、視感度補正
をした状態で簡易的に測定される発光の強度は約74ミ
リカンデラ(mcd)であった。更に、本実施例のAl
GaInP系LED100では、近視野発光パターンの
観点からしても開放発光面206aに於ける発光強度の
分布は、網状導電性電極207に依る動作電流の均一な
分配の効果により均等となった。
On the back surface of the p-type GaAs single crystal substrate 201, a p-type conductive electrode 21 made of a gold-zinc (Au-Zn) alloy
After forming 0, the laminated structure (wafer) 1A was cut and divided into individual pieces by a normal scribing method to obtain LED chips 100. The chip (individual element) 100 was a square having a side length (= Q) of 260 μm. A current was passed in the forward direction between the n-type conductive electrode 207 via the p-type conductive electrode 210 and the pedestal electrode 209, and red-orange light having a wavelength of about 620 nm was obtained through the open light-emitting region 206a. The half width of the light emission spectrum was about 20 nm, and the light emission was excellent in monochromaticity. Forward voltage (Vf: @ 2) when a current of 20 mA (mA) flows
0 mA) was about 2.1 volts (V), reflecting good ohmic characteristics of the conductive electrode 207 made of a reticulated metal film. In addition, since the conductive electrode 207 is formed of a net-like metal film having a hole, light emission is also observed in the area of the peripheral edge 100b of the chip 100, and the measurement is easily performed with the visibility corrected. The intensity of the emitted light was about 74 millicandela (mcd). Further, in the present embodiment, Al
In the GaInP-based LED 100, even from the viewpoint of the near-field light-emitting pattern, the distribution of the light-emitting intensity on the open light-emitting surface 206a became uniform due to the effect of uniform distribution of the operating current by the reticulated conductive electrode 207.

【0028】(実施例2)本実施例では、菱形に搾孔さ
れたメッシュ(mesh)状の導電性電極を備えた窒化
ガリウム(GaN)系LEDを構成する場合を例にして
本発明を具体的に説明する。図13にGaN系LED2
00の平面模式図を示す。また、図14に、図13のL
ED200の破線B−B’に沿った断面模式図を示す。
(Embodiment 2) In this embodiment, the present invention will be described in detail by taking as an example a case in which a gallium nitride (GaN) LED having a mesh-shaped conductive electrode formed in a diamond shape is formed. Will be explained. FIG. 13 shows a GaN-based LED 2
00 shows a schematic plan view. FIG. 14 shows L in FIG.
FIG. 3 shows a schematic cross-sectional view of the ED 200 along a broken line BB ′.

【0029】硼素(元素記号:B)ドープp形(00
1)珪素(Si)単結晶円形基板301上に、亜鉛(Z
n)ドープp形リン化硼素(BP)低温緩衝層302、
Znドープp形BP高温緩衝層303、マグネシウム
(Mg)をドーピングしたp形GaNからなる下部クラ
ッド層304、平均的なインジウム(In)組成比を
0.10とし、インジウム組成を互いに相違する複数の
相(phase)からなる多相構造のn形Ga0.90In
0.10N発光層305、アルミニウム(Al)組成比を
0.15とした、珪素(Si)ドープn形Al0.15Ga
0.85からなる上部クラッド層306、及びSiドープn
形GaNからなるコンタクト層307を順次、積層して
GaN系LED200用途の積層構造体3Aを形成し
た。
Boron (element symbol: B) doped p-type (00
1) On a silicon (Si) single crystal circular substrate 301, zinc (Z
n) doped p-type boron phosphide (BP) low temperature buffer layer 302;
A Zn-doped p-type BP high-temperature buffer layer 303, a lower cladding layer 304 made of p-type GaN doped with magnesium (Mg), an average indium (In) composition ratio of 0.10, and a plurality of indium compositions different from each other. N-type Ga 0.90 In having a multi-phase structure composed of phases
0.10 N light emitting layer 305, silicon (Si) doped n-type Al 0.15 Ga with an aluminum (Al) composition ratio of 0.15
An upper cladding layer 306 of 0.85 and Si-doped n
The contact layer 307 made of shaped GaN was sequentially laminated to form a laminated structure 3A for the GaN-based LED 200.

【0030】BP緩衝層302、303はトリエチル硼
素(化学式:(C253B)及びフォスフィン(P
3)を原料とする減圧MOCVD法により成膜した。
BP低温緩衝層302は400℃で成膜し、層厚は約1
0nmとした。BP高温緩衝層303は1030℃で成
膜し、層厚は約1μmとした。キャリア濃度は約2×1
18cm-3とした。亜鉛のドーピング源にはジエチル亜
鉛(化学式:(C25 2Zn)を使用した。
The BP buffer layers 302 and 303 are made of triethyl boron.
Element (chemical formula: (CTwoHFive)ThreeB) and phosphine (P
HThree) Was formed as a raw material by a reduced pressure MOCVD method.
The BP low-temperature buffer layer 302 is formed at 400 ° C. and has a thickness of about 1
It was set to 0 nm. The BP high temperature buffer layer 303 is formed at 1030 ° C.
The film was formed, and the layer thickness was about 1 μm. Carrier concentration is about 2 × 1
018cm-3And The zinc doping source is diethyl
Lead (chemical formula: (CTwoHFive) TwoZn) was used.

【0031】積層構造体3Aを構成するその他の各構成
層304〜307はトリメチルアルミニウム((C
33Al)、トリメチルガリウム((CH33Ga)
及びトリメチルインジウム((CH33In)をIII
族構成元素の原料とし、アンモニア(NH3)をV族原
料とする常圧MOCVD法により成膜した。マグネシウ
ム(Mg)のドーピング源にはビスシクロペンタジエニ
ルマグネシウム(bis−(C552Mg)を利用し
た。Siのドーパント源にはジシラン(Si26)を使
用した。各構成層304〜307の成膜温度は1030
℃に統一した。下部クラッド層304のキャリア濃度は
約3×1018cm-3に、また、層厚は約2μmとした。
発光層305の層厚は約100nmとし、キャリア濃度
は約1×10 17cm-3とした。n形Al0.10Ga0.90
層からなる上部クラッド層306のキャリア濃度は3×
1017cm-3とし、また、層厚は約10nmとした。n
形GaNコンタクト層307のキャリア濃度は約2×1
18cm-3とし、その層厚は約100nmとした。
Other components constituting the laminated structure 3A
Layers 304-307 are made of trimethyl aluminum ((C
HThree)ThreeAl), trimethylgallium ((CHThree)ThreeGa)
And trimethylindium ((CHThree)ThreeIn) III
Ammonia (NHThree) For the V-group
The film was formed by a normal pressure MOCVD method as a raw material. Magnesium
(Mg) doping source is biscyclopentadiene
Rumagnesium (bis- (CFiveHFive)TwoMg)
Was. The source of Si dopant is disilane (SiTwoH6)use
Used. The film forming temperature of each of the constituent layers 304 to 307 is 1030
° C. The carrier concentration of the lower cladding layer 304 is
About 3 × 1018cm-3The layer thickness was about 2 μm.
The thickness of the light emitting layer 305 is about 100 nm, and the carrier concentration
Is about 1 × 10 17cm-3And n-type Al0.10Ga0.90N
The carrier concentration of the upper cladding layer 306 is 3 ×
1017cm-3And the layer thickness was about 10 nm. n
Carrier concentration of the GaN contact layer 307 is about 2 × 1
018cm-3And the layer thickness was about 100 nm.

【0032】n形GaNコンタクト層307の表面の全
面に、一般的な真空蒸着法により膜厚を約8nmとする
金(Au)膜を被着させた。次に、一般的なフォトリソ
グラフィー手段を利用して、Au膜に図13に示す如く
の長方形の搾孔部308a、308bを形成した。長方
形の搾孔部308aは、その長辺をLEDチップ200
の中心線C1に平行にして、また、中心線C1と線対称
となる合計2箇所に設けた。搾孔部308aをなす長方
形の大きさは長辺を120μmとし、短辺を50μmと
した。別の長方形の搾孔部308bは長辺を中心線C2
に平行にして、また、中心線C2に対して線対称となる
位置に合計2箇所に設けた。長方形の搾孔部308bは
長辺を260μmとし、短辺の長さを50μmとした。
台座電極の射影領域310aの外縁と長方形の搾孔部3
08a、308bとの最短の間隔は20μmとした。ま
た、長方形の搾孔部308a、308bとLEDの外縁
200bとの距離は20μmとした。
A gold (Au) film having a thickness of about 8 nm was applied to the entire surface of the n-type GaN contact layer 307 by a general vacuum deposition method. Next, rectangular holes 308a and 308b as shown in FIG. 13 were formed in the Au film by using general photolithography means. The rectangular hole 308a has a long side formed by the LED chip 200.
Are provided in parallel with the center line C1, and at a total of two locations that are line-symmetric with the center line C1. The size of the rectangle forming the hole portion 308a was such that the long side was 120 μm and the short side was 50 μm. Another rectangular hole 308b has a long side at the center line C2.
, And at two positions symmetrical with respect to the center line C2. The rectangular hole 308b had a long side of 260 μm and a short side of 50 μm.
Outer edge of projection area 310a of pedestal electrode and rectangular hole 3
The shortest distance between the electrodes 08a and 308b was 20 μm. The distance between the rectangular holes 308a and 308b and the outer edge 200b of the LED was 20 μm.

【0033】次に、n形GaNコンタクト層307上に
長方形の搾孔部308a、308bを有する網状の導電
性電極308を残置させたままで、一般のマグネトロン
スパッタリング法により透明窓層309とする酸化イン
ジウム・錫(ITO)膜を被着させた。ITO層の比抵
抗は約4×10-4Ω・cmであり、層厚は約430nm
とした。窓層309の全面に、一般的な有機フォトレジ
スト材料を塗布した後、台座電極310を設けるべき領
域を、公知のフォトリソグラフィー技術を利用してパタ
ーニングした。然る後、パターニングされたレジスト材
料を残置させたままで、全面にチタン(Ti)膜を電子
ビーム真空蒸着法により被着させた。Ti膜の厚さは約
500nmとした。その後、レジスト材料を剥離するに
併せて、周知のリフト−オフ(lift−off)手段
に依り台座電極310の形成予定領域に限定してTi膜
を残留させた。これより、直径を約120μmとする円
形の台座電極310を形成した。
Next, with the net-shaped conductive electrode 308 having the rectangular holes 308a and 308b remaining on the n-type GaN contact layer 307, indium oxide is formed as the transparent window layer 309 by a general magnetron sputtering method. -A tin (ITO) film was deposited. The specific resistance of the ITO layer is about 4 × 10 −4 Ω · cm, and the layer thickness is about 430 nm.
And After applying a general organic photoresist material to the entire surface of the window layer 309, a region where the pedestal electrode 310 is to be provided was patterned by using a known photolithography technique. Thereafter, a titanium (Ti) film was deposited on the entire surface by an electron beam vacuum evaporation method while leaving the patterned resist material. The thickness of the Ti film was about 500 nm. Thereafter, along with the removal of the resist material, the Ti film was left only in the region where the pedestal electrode 310 was to be formed by well-known lift-off means. Thus, a circular pedestal electrode 310 having a diameter of about 120 μm was formed.

【0034】本実施例では、LED200のチップサイ
ズ(=Q)を300μmとしたことから、台座電極31
0の平面積(約1.1×10-4cm2)を除く開放発光
領域の表面積は約7.9×10-4cm2となった。一
方、長方形の搾孔部308a、308bの合計の平面積
は3.8×10-4cm2であり、従って、開放発光領域
307aの表面積に占める長方形の搾孔部の、合計の平
面積の割合は約48.1%となった。また素子平面上に
おける導電性電極308と台座電極310の底部とを除
く部分の、素子平面全体に対する比率は約42%、素子
平面上における導電性電極308の合計面積の、台座電
極の底面積に対する比率は約373%となった。
In this embodiment, since the chip size (= Q) of the LED 200 is 300 μm, the pedestal electrode 31
The surface area of the open light-emitting region excluding the zero plane area (about 1.1 × 10 −4 cm 2 ) was about 7.9 × 10 −4 cm 2 . On the other hand, the total plane area of the rectangular holes 308a and 308b is 3.8 × 10 −4 cm 2 , and accordingly, the total plane area of the rectangular holes occupying the surface area of the open light-emitting region 307a. The ratio was about 48.1%. The ratio of the portion excluding the conductive electrode 308 on the element plane and the bottom of the pedestal electrode 310 to the entire element plane is about 42%, and the total area of the conductive electrodes 308 on the element plane is smaller than the bottom area of the pedestal electrode. The ratio was about 373%.

【0035】p形Si単結晶基板301の裏面にアルミ
ニウム(Al)からなるp形導電性電極311を形成し
た後、通常のスクライブ法により積層構造体(ウェハ)
3Aを裁断して個別に細分化し、LEDチップ200と
なした。チップ(個別素子)200は一辺を300μm
とする正方形とした。p形導電性電極311及び台座電
極310間に順方向に電流を通流したところ、開放発光
領域307aを通して波長を約440nmとする青色光
が出射された。網状の導電性電極308を配置した効果
に依り、LED200の周縁200bの領域に於いても
略一様な強度発光が認められ、チップ状態で測定した発
光の強度は約1.1カンデラ(cd)であった。20ミ
リアンペア(mA)の電流を通流した際の順方向電圧
(Vf:@20mA)は、導電性電極308の良好なオ
ーミック特性を反映して約3.8ボルト(V)となっ
た。
After a p-type conductive electrode 311 made of aluminum (Al) is formed on the back surface of a p-type Si single crystal substrate 301, a laminated structure (wafer) is formed by a usual scribing method.
3A was cut and individually subdivided into LED chips 200. Chip (individual element) 200 has a side of 300 μm
And a square. When a current was passed between the p-type conductive electrode 311 and the pedestal electrode 310 in the forward direction, blue light having a wavelength of about 440 nm was emitted through the open light emitting region 307a. Due to the effect of arranging the reticulated conductive electrodes 308, substantially uniform intensity light emission is recognized even in the region of the periphery 200b of the LED 200, and the intensity of light emission measured in a chip state is about 1.1 candela (cd). Met. The forward voltage (Vf: @ 20 mA) when a current of 20 mA (mA) was passed was about 3.8 volts (V), reflecting the good ohmic characteristics of the conductive electrode 308.

【0036】[0036]

【発明の効果】本発明に依れば、台座電極と窓層を備え
た半導体LEDにあって、窓層と高い接合障壁を形成す
る半導体層の開放発光領域に搾孔部を有する網状の電極
を設ける構成としたので、開放発光領域の平面積を徒に
減少させることなく、且つ台座電極から供給されるLE
D駆動電流が窓層より導電性電極を介して流通できるた
め、LED駆動電流が開放発光領域に略均等に拡散さ
れ、発光強度の分布が均一で且つ高発光強度の半導体L
EDが提供できる。
According to the present invention, there is provided a semiconductor LED having a pedestal electrode and a window layer, wherein the mesh electrode has a hole in an open light emitting region of the semiconductor layer forming a high junction barrier with the window layer. Is provided, without unnecessarily reducing the plane area of the open light emitting region, and the LE supplied from the pedestal electrode.
Since the D drive current can flow from the window layer through the conductive electrode, the LED drive current is diffused substantially evenly in the open light emitting region, and the semiconductor light emitting device having a uniform light emission intensity distribution and high light emission intensity
ED can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施形態に係わるLEDの平面
構造を示す平面模式図である。
FIG. 1 is a schematic plan view showing a planar structure of an LED according to a first embodiment of the present invention.

【図2】図1に示すLEDの破線X−Yに沿った断面模
式図である。
FIG. 2 is a schematic cross-sectional view of the LED shown in FIG. 1 along a broken line XY.

【図3】本発明の第11の実施形態に係わる導電性電極
を備えたLEDの平面模式図である。
FIG. 3 is a schematic plan view of an LED including a conductive electrode according to an eleventh embodiment of the present invention.

【図4】本発明の第12の実施形態に係わる導電性電極
を備えたLEDの平面模式図である。
FIG. 4 is a schematic plan view of an LED including a conductive electrode according to a twelfth embodiment of the present invention.

【図5】本発明の第13の実施形態に係わる導電性電極
を備えたLEDの平面模式図である。
FIG. 5 is a schematic plan view of an LED including a conductive electrode according to a thirteenth embodiment of the present invention.

【図6】本発明の第14の実施形態に係わる導電性電極
を備えたLEDの平面模式図である。
FIG. 6 is a schematic plan view of an LED including a conductive electrode according to a fourteenth embodiment of the present invention.

【図7】本発明の第14の実施形態に係わる導電性電極
を備えた別のLEDの平面模式図である。
FIG. 7 is a schematic plan view of another LED including a conductive electrode according to a fourteenth embodiment of the present invention.

【図8】本発明の第15の実施形態に係わる導電性電極
を備えたLEDの平面模式図である。
FIG. 8 is a schematic plan view of an LED including a conductive electrode according to a fifteenth embodiment of the present invention.

【図9】本発明の第15の実施形態に係わる導電性電極
を備えた別のLEDの平面模式図である。
FIG. 9 is a schematic plan view of another LED including a conductive electrode according to a fifteenth embodiment of the present invention.

【図10】本発明の第15の実施形態に係わる導電性電
極を備えたまた別のLEDの平面模式図である。
FIG. 10 is a schematic plan view of still another LED provided with a conductive electrode according to a fifteenth embodiment of the present invention.

【図11】本発明の実施例1に記載のLEDの平面模式
図である。
FIG. 11 is a schematic plan view of the LED according to the first embodiment of the present invention.

【図12】図11のLEDの破線A−A’に沿った断面
模式図である。
FIG. 12 is a schematic cross-sectional view of the LED of FIG. 11 taken along a broken line AA ′.

【図13】本発明の実施例2に記載のLEDの平面模式
図である。
FIG. 13 is a schematic plan view of an LED according to a second embodiment of the present invention.

【図14】図13のLEDの破線B−B’に沿った断面
模式図である。
FIG. 14 is a schematic cross-sectional view of the LED of FIG. 13 along the broken line BB ′.

【符号の説明】[Explanation of symbols]

1A 積層構造体 2A 積層構造体 10 III−V族化合物半導体LED 10a pn接合型ダブルヘテロ接合発光部 10b LEDチップの外縁 20 III−V族化合物半導体LED 30 III−V族化合物半導体LED 40 III−V族化合物半導体LED 50 III−V族化合物半導体LED 60 III−V族化合物半導体LED 70 III−V族化合物半導体LED 80 III−V族化合物半導体LED 90 III−V族化合物半導体LED 100 AlGaInP系LED 100b LEDの外縁 101 単結晶基板 102 緩衝層 103 ブラッグ反射層 104 下部クラッド層 105 発光層 106 上部クラッド層 106a 開放発光領域 107 導電性電極 108 窓層 109 台座電極 109a 台座電極の射影領域 110 導電性電極 111 円形の搾孔部 112 楕円形の搾孔部 113 方形の搾孔部 114 六角形の搾孔部 115 帯状の搾孔部 d 隣接する導電性電極間の間隔 C1 LEDチップの中心線 C2 LEDチップの中心線 L1 LEDチップの対角線 L2 LEDチップの対角線 M LEDチップ(台座電極)の中心点 Q LEDチップのサイズ R 台座電極の平面形状の中心点Mより導電性電極の
形状中心に至る距離 200 GaInN系LED 200b LEDの外縁 201 p形GaAs単結晶基板 202 p形GaAs緩衝層 203 ブラッグ反射層 204 AlGaInP系下部クラッド層 205 AlGaInP系発光層 206 AlGaInP系上部クラッド層 206a 開放発光領域 207 導電性電極 207a 第1の円弧状搾孔部 207b 第2の円弧状搾後部 207c 円形の搾孔部 208 導電性透明酸化物窓層 209 台座電極 209a 台座電極の射影領域 210 p形導電性電極 301 p形Si単結晶基板 302 p形BP低温緩衝層 303 p形BP高温緩衝層 304 p形GaN下部クラッド層 305 GaInN発光層 306 n形AlGaN上部クラッド層 307 n形GaNコンタクト層 307a 開放発光領域 308 網状導電性電極 308a 長方形の搾孔部 308b 長方形の搾孔部 309 導電性透明酸化物窓層 310 台座電極 310a 台座電極の射影領域 311 基板裏面側導電性電極
Reference Signs List 1A laminated structure 2A laminated structure 10 III-V compound semiconductor LED 10a pn junction type double hetero junction light emitting section 10b Outer edge of LED chip 20 III-V compound semiconductor LED 30 III-V compound semiconductor LED 40 III-V Group III compound semiconductor LED 50 III-V group compound semiconductor LED 60 III-V group compound semiconductor LED 70 III-V group compound semiconductor LED 80 III-V group compound semiconductor LED 90 III-V group compound semiconductor LED 100 AlGaInP-based LED 100b LED Outer edge 101 Single crystal substrate 102 Buffer layer 103 Bragg reflection layer 104 Lower cladding layer 105 Light emitting layer 106 Upper cladding layer 106a Open light emitting area 107 Conductive electrode 108 Window layer 109 Pedestal electrode 109a Projection area of pedestal electrode 1 Reference Signs List 10 conductive electrode 111 circular hole 112 elliptical hole 113 rectangular hole 114 hexagonal hole 115 band-shaped hole d spacing between adjacent conductive electrodes d1 center of LED chip Line C2 Center line of LED chip L1 Diagonal line of LED chip L2 Diagonal line of LED chip M Center point of LED chip (pedestal electrode) Q Size of LED chip R Center point M of planar shape of pedestal electrode at center of shape of conductive electrode Distance 200 GaInN-based LED 200b Outer edge of LED 201 p-type GaAs single crystal substrate 202 p-type GaAs buffer layer 203 Bragg reflection layer 204 AlGaInP-based lower clad layer 205 AlGaInP-based light-emitting layer 206 AlGaInP-based upper clad layer 206a open light-emitting region 207 conductive Electrode 207a First arc-shaped hole 2 7b Second arc-shaped rear portion 207c Circular hole portion 208 Conductive transparent oxide window layer 209 Pedestal electrode 209a Projection region of pedestal electrode 210 P-type conductive electrode 301 p-type Si single crystal substrate 302 p-type BP low-temperature buffer Layer 303 p-type BP high-temperature buffer layer 304 p-type GaN lower cladding layer 305 GaInN light-emitting layer 306 n-type AlGaN upper cladding layer 307 n-type GaN contact layer 307 a open light-emitting area 308 mesh conductive electrode 308 a rectangular hole 308 b rectangular Hole 309 Conductive transparent oxide window layer 310 Pedestal electrode 310a Projected area of pedestal electrode 311 Conductive electrode on back side of substrate

───────────────────────────────────────────────────── フロントページの続き (72)発明者 保科 孝治 埼玉県秩父市下影森1505番地 昭和電工株 式会社総合研究所秩父研究室内 (72)発明者 宇田川 隆 埼玉県秩父市下影森1505番地 昭和電工株 式会社総合研究所秩父研究室内 Fターム(参考) 5F041 AA03 AA04 CA03 CA34 CA35 CA40 CA85 CA88 CA92 CA93 CA98  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Koji Hoshina 1505 Shimokagemori, Chichibu City, Saitama Prefecture Showa Denko Co., Ltd. F-term 5F041 AA03 AA04 CA03 CA34 CA35 CA40 CA85 CA88 CA92 CA93 CA98

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】発光層、窓層、および結線用台座電極を有
する半導体発光ダイオードにおいて、素子平面における
台座電極の射影領域以外に網目状の導電性電極を有する
ことを特徴とする半導体発光ダイオード。
1. A semiconductor light-emitting diode having a light-emitting layer, a window layer, and a pedestal electrode for connection, comprising a mesh-shaped conductive electrode in an element plane other than a projection area of the pedestal electrode.
【請求項2】素子の平面形状が、一辺の長さを150〜
500μmとした略正方形であることを特徴とする請求
項1に記載の半導体発光ダイオード。
2. The planar shape of the element is such that the length of one side is 150 to 150.
2. The semiconductor light emitting diode according to claim 1, wherein the semiconductor light emitting diode has a substantially square shape of 500 μm.
【請求項3】網目状の導電性電極が、素子平面における
台座電極の射影領域以外の略全面に敷設されていること
を特徴とする請求項1または2に記載の半導体発光ダイ
オード。
3. The semiconductor light emitting diode according to claim 1, wherein the mesh-shaped conductive electrodes are laid on substantially the entire surface of the element plane other than the projection region of the pedestal electrode.
【請求項4】網目状の導電性電極の素子平面における形
状が、台座電極の射影領域の中心点について点対称とな
っていることを特徴とする請求項1〜3の何れか1項に
記載の半導体発光ダイオード。
4. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane is point-symmetric with respect to the center point of the projection area of the pedestal electrode. Semiconductor light emitting diode.
【請求項5】網目状の導電性電極の素子平面における形
状が、台座電極の射影領域の中心点を通る線について線
対称となっていることを特徴とする請求項1〜4の何れ
か1項に記載の半導体発光ダイオード。
5. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane is line-symmetric with respect to a line passing through the center point of the projection area of the pedestal electrode. 13. A semiconductor light emitting diode according to item 9.
【請求項6】発光層がIII−V族化合物半導体から形
成されていることを特徴とする請求項1〜5の何れか1
項に記載の半導体発光ダイオード。
6. The light-emitting layer according to claim 1, wherein the light-emitting layer is formed of a group III-V compound semiconductor.
13. A semiconductor light emitting diode according to item 9.
【請求項7】窓層が、酸化物から形成された層を含むこ
とを特徴とする請求項1〜6の何れか1項に記載の半導
体発光ダイオード。
7. The semiconductor light emitting diode according to claim 1, wherein the window layer includes a layer formed from an oxide.
【請求項8】網目状の導電性電極が、金属から形成され
た層を含むことを特徴とする請求項1〜7の何れか1項
に記載の半導体ダイオード。
8. The semiconductor diode according to claim 1, wherein the mesh-shaped conductive electrode includes a layer formed of a metal.
【請求項9】網目状の導電性電極の素子平面上における
面積の合計が、台座電極の底面積の、10〜500%の
範囲内であることを特徴とする請求項1〜8の何れか1
項に記載の発光ダイオード。
9. The method according to claim 1, wherein the total area of the mesh-shaped conductive electrodes on the element plane is in the range of 10 to 500% of the bottom area of the pedestal electrode. 1
A light-emitting diode according to the item.
【請求項10】素子平面上において、網目状の導電性電
極と台座電極の底部とを除く部分の面積が、素子平面全
体に対する面積の比率で30〜95%の範囲であること
を特徴とする請求項1〜9の何れか1項に記載の発光ダ
イオード。
10. The device according to claim 1, wherein the area of the portion excluding the mesh-shaped conductive electrode and the bottom of the pedestal electrode on the element plane is in the range of 30 to 95% in terms of the area ratio to the entire element plane. The light emitting diode according to claim 1.
【請求項11】網目状の導電性電極の素子平面における
形状が、直径5〜200μmの範囲で円形に搾孔された
領域を含むことを特徴とする請求項1〜10の何れか1
項に記載の半導体発光ダイオード。
11. The method according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane includes a circular hole in a range of 5 to 200 μm in diameter.
13. A semiconductor light emitting diode according to item 9.
【請求項12】網目状の導電性電極の素子平面における
形状が、長径5〜200μmの範囲で楕円形に搾孔され
た領域を含むことを特徴とする請求項1〜11の何れか
1項に記載の半導体発光ダイオード。
12. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane includes a region having a major axis in a range of 5 to 200 μm and formed in an elliptical shape. A semiconductor light-emitting diode according to claim 1.
【請求項13】網目状の導電性電極の素子平面における
形状が、一辺の長さが5〜200μmの範囲で方形に搾
孔された領域を含むことを特徴とする請求項1〜12の
何れか1項に記載の半導体発光ダイオード。
13. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane includes a rectangular hole formed in a range of 5 to 200 μm on one side. The semiconductor light emitting diode according to claim 1.
【請求項14】網目状の導電性電極の素子平面における
形状が、一辺の長さが5〜200μmの範囲で多角形に
搾孔された領域を含むことを特徴とする請求項1〜13
の何れか1項に記載の半導体発光ダイオード。
14. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane includes a polygonal hole having a side length of 5 to 200 μm.
The semiconductor light-emitting diode according to any one of the preceding claims.
【請求項15】網目状の導電性電極の素子平面における
形状が、幅が5〜100μmの範囲で帯状に搾孔された
領域を含むことを特徴とする請求項1〜14の何れか1
項に記載の半導体発光ダイオード。
15. The device according to claim 1, wherein the shape of the mesh-shaped conductive electrode in the element plane includes a band-shaped hole having a width of 5 to 100 μm.
13. A semiconductor light emitting diode according to item 9.
JP32975599A 1999-10-19 1999-11-19 Semiconductor light emitting diode Expired - Fee Related JP3989658B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP32975599A JP3989658B2 (en) 1999-11-19 1999-11-19 Semiconductor light emitting diode
TW89121680A TW477078B (en) 1999-10-19 2000-10-17 Semiconductor light-emitting device, electrode for the device, method for fabricating the electrode, led lamp using the device, and light source using the led lamp
US09/691,057 US6512248B1 (en) 1999-10-19 2000-10-19 Semiconductor light-emitting device, electrode for the device, method for fabricating the electrode, LED lamp using the device, and light source using the LED lamp
US10/265,148 US6677615B2 (en) 1999-10-19 2002-10-07 Semiconductor light-emitting device, electrode for the device, method for fabricating the electrode, LED lamp using the device, and light source using the LED lamp

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32975599A JP3989658B2 (en) 1999-11-19 1999-11-19 Semiconductor light emitting diode

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