JP2000021899A - Field effect transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor for preventing frequency dispersion due to a low resistance region formed in a GaAs layer, at a boundary face part with Si and the deterioration of a gate breakdown voltage to be generated for reducing the parasitic resistance between gate-source, and a method for manufacturing this. SOLUTION: Plural compound semiconductor layers 2-4 are laminated on an Si substrate 1, and a source electrode 16 and a drain electrode 17 are provided on the compound semiconductor layers 2-4 to be separated from each other, and a gate electrode 15 is formed between those source electrode 16 and drain electrode 17 in this field effect transistor. In this case, this device is provided with a conductive region 8 for reaching from the surface part of the compound semiconductor layers 2-4 to the neighborhood of the boundary face with the Si substrate 1, and the drain electrode 17 is formed on this conductive region 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly to a field effect transistor using a compound semiconductor layer provided on a Si substrate as an active layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor devices using a compound semiconductor are known as S
Compared to i-semiconductors, they can operate at higher speeds and higher frequency ranges, and their fields of use are rapidly expanding. Nevertheless, the diameter of a bulk substrate made only of a compound semiconductor is still about 3 to 4 inches, and the mass production of a semiconductor device formed using the same is larger than that of a Si substrate having a larger diameter. Is one of the difficulties.

Therefore, a method of epitaxially growing a compound semiconductor such as GaAs on a Si substrate has attracted attention. MOCVD (Metal Organic Chemical Vapor Dep)
In the so-called two-stage growth method by the osition method, or an improved method thereof, the surface of the Si substrate is heat-treated at 800 ° C. or more, and then a GaAs initialization film is formed at 400 to 450 ° C. for several hundreds.
Then, a compound semiconductor film such as GaAs is epitaxially grown at a normal epitaxial growth temperature (about 700 ° C.).

Due to such a temperature history, during the growth of the compound semiconductor film, the Si element in the Si substrate penetrates and diffuses into the compound semiconductor film, and As, which is a constituent element of the compound semiconductor film, is deposited on the Si substrate. The phenomenon of invasion and diffusion occurs.

[0005] Si becomes an n-type dopant for the III-V group compound semiconductor, and As becomes an n-type dopant for Si. By such interdiffusion, Si substrate and
A low-resistance region is formed at the interface between the III-V compound semiconductor layers.

An MESFET (Metal Semiconductor) is formed using an epitaxial wafer having such a low resistance region formed thereon.
ctor Field Effect Transistor)
An n-GaAs active layer serving as a channel of the MESFET is formed on the buffer layer into which Si has penetrated and diffused, and an n ⁺ -GaAs contact layer is formed thereon as required.

That is, as shown in FIG. 4, a GaAs buffer layer 12, an n-GaAs active layer 13, and an n ⁺ -GaAs contact layer 14 are formed on a high-resistance Si substrate 11 to form an n-GaAs active layer. 13 so as to partially expose the, part of the n ⁺ -GaAs layer 14 and the n-GaAs active layer 13 to form a gate electrode 15 by recess etching, on n ⁺ -GaAs layer 14 on both sides thereof In this case, a source electrode 16 and a drain electrode 17 are formed.

[0008] As shown in FIG. 5, a GaAs buffer layer 12 and an n-GaAs layer 13 are formed on a high-resistance Si substrate 11.
Is formed, a part of the n-GaAs active layer 13 is recess-etched to form a gate electrode 15, and an n + contact region 14 'is formed in the n-GaAs active layer 13 on both sides of the gate electrode 15. N formed by ion implantation
^{+ A} source electrode 16 and a drain electrode 17 are formed on a contact region 14 '.

[0009]

However, the Si substrate 1
Si on the GaAs layer 12 side at the interface between
When an MESFET is formed using an epitaxial wafer on which a low-resistance region 12a is formed by auto-doping,
This slight potential variation in the low resistance region 12a causes a variation in the transistor current, which is observed as a frequency dispersion of the drain conductance Gds and a frequency dispersion of the parasitic capacitance Cdp of the pad portion (not shown) of the drain electrode 17 in a high frequency region. Is done. These phenomena cause a decrease in noise margin, malfunction, and the like, particularly when handling signals of a plurality of frequencies and wide bands.

Further, when an integrated circuit is formed with such an FET device, a characteristic interference phenomenon between elements such as a side gate effect and a back gate effect appears. This is G
This is because a potential change in the low resistance region 12a formed at the interface between the aAs layer 12 and the Si substrate 11 induces a change in the drain current of the transistor.

Therefore, a method of avoiding the above-described fluctuation of the drain current by adopting a driving method of fixing the potential of the low resistance region 12a to a voltage substantially equal to the drain voltage has been proposed (for example, Japanese Patent Application Laid-Open No. Hei 6 (1994) -259). -349858). That is, as shown in FIG.
An electrode 18 is provided on the back side of the device, and the same voltage as the maximum voltage among the fixed voltages applied to the drain electrode 17 is applied to the electrode 18, thereby stabilizing the current flowing through the FET, and the drain due to the back gate effect. This is to suppress the fluctuation of the current.

On the other hand, in order to improve the high frequency characteristics of a GaAs FET, it is necessary to reduce the parasitic resistance between the gate and the source. This is because a large parasitic resistance between the gate and the source causes deterioration of the transconductance (gm). Therefore, as in the conventional example shown in FIG. 5, only the portion immediately below the gate electrode 15 is removed by recess etching, and the thickness of the active layer 13 between the gate and the source and the n ⁺ − between the gate and the source are removed.
A method of keeping the thickness of the GaAs layer 14 large has been adopted. That is, in order to reduce the source resistance, the gate electrode 15 and the recess region are formed at the same time. However, in this method, the distance between the gate electrode 15 and the n ⁺ -GaAs layer 14 on the drain side cannot be secured. This causes a new problem that the gate breakdown voltage deteriorates.

On the other hand, in the conventional example shown in FIG. 6, it is easy to secure the distance between the gate electrode 15 and the n ⁺ -GaAs region 14 'on the drain side, but at the same time, the distance between the gate electrode 15 and the source is increased. Therefore, there is a problem that the parasitic resistance between the gate and the source is increased and the high frequency characteristics are deteriorated.

The present invention has been made in view of such a problem of the conventional device, and GaAs at the interface with Si is provided.
Frequency dispersion due to low resistance region formed in the layer and gate
It is an object of the present invention to provide a field-effect transistor in which deterioration of a gate withstand voltage generated to reduce parasitic resistance between sources is eliminated, and a method of manufacturing the same.

[0015]

In order to achieve the above object, in a field effect transistor according to the present invention, a plurality of compound semiconductor layers are provided on a Si substrate, and a source electrode is provided on the compound semiconductor layer. And a drain electrode provided separately, in a field-effect transistor having a gate electrode provided between the source electrode and the drain electrode, a conductive region is provided from the surface of the compound semiconductor layer to the vicinity of the interface with the Si substrate; The drain electrode was provided on this conductive region.

As described above, when a conductive region extending from the surface of the compound semiconductor layer to the low resistance layer formed near the interface with the Si substrate is provided, and a drain electrode is provided on the conductive region, deep level charge / discharge can be achieved. Fluctuation of the drain current and frequency dispersion caused by this can be reduced.

In the above-described field effect transistor, layers having different energy band gaps may be provided in the compound semiconductor layer.

In the method of manufacturing a field-effect transistor according to claim 4, a buffer layer, an active layer,
After forming a compound semiconductor layer to be a contact layer and performing mesa etching, a part of the contact layer is recess-etched to expose a part of the active layer, and a gate electrode is formed on the exposed part of the active layer. In addition, in the method of manufacturing a field-effect transistor in which a source electrode and a drain electrode are formed on contact layers on both sides of the gate electrode, after forming the compound semiconductor layer on the Si substrate, Impurity ions are implanted into a region reaching the vicinity of the interface with the Si substrate to form a conductive region, and the drain electrode is formed on the conductive region.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a field effect transistor according to the claims and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing one embodiment of the field-effect transistor according to claims 1 and 2, wherein 1 is a high-resistance Si substrate, 2 is a GaAs buffer layer,
Reference numeral 3 denotes an n-GaAs active layer, 4 denotes an n ⁺ -GaAs contact layer, 5 denotes a gate electrode, 6 denotes a source electrode, 7 denotes a drain electrode, and 8 denotes a conductive region.

The Si substrate 1 has a surface orientation of (100) or a specific resistance having an off angle of several degrees and a resistivity of 1 × 10 ² to 10 × 10 ^2.
A high resistance substrate of about ³ Ω · cm is preferably used.

The buffer layer 2 is made of GaAs or the like.
It is formed to a thickness of about 1-3 μm. This buffer layer 2
The low resistance region 2a in which Si is auto-doped from the Si substrate when the buffer layer 2 is formed is formed at the interface portion with the Si substrate 1.

The active layer 3 is made of n-GaAs or the like.
It is formed to a thickness of about 0.1 to 0.2 μm and contains about 1 × 10 ¹⁷ atoms · cm ⁻³ of n-type impurities such as Si.

The contact layer 4 is made of n ⁺ -GaAs or the like, is formed to a thickness of about 0.1 to 0.2 μm,
1 × 10 ¹⁸ to 10 ¹⁹ atoms ·
It contains about cm ^-3 . The contact layer 4 is formed only below the source electrode 6 described later. The n ⁺ -GaAs contact layer 6 may be formed so that a part of the n ⁺ -GaAs contact layer 6 remains on the n-GaAs active layer 3 between the gate electrode 5 and the drain electrode 7 described later. In this case, since the n ⁺ -GaAs layer remaining between the gate and the drain region is isolated from the drain region, the breakdown voltage of the gate and the drain is not reduced.

From the surface of the active layer 3 to the buffer layer 2
The conductive region 8 is formed in the vertical direction over the low resistance region 2a. The conductive region 8 is formed by containing about 1 × 10 ¹⁸ atoms · cm ^{−2 of} an n-type impurity such as Si.

On the active layer 3, a gate electrode 5 made of Ti / Pt / Au, Ti / Al or the like is formed. A source electrode 6 is formed on the n + -GaAs contact layer 4, and a drain electrode 8 is formed on the conductive region 8.

As described above, when the conductive region 8 extending from the surface of the active layer 3 to the low resistance layer 2a near the interface with the Si substrate 1 is provided, and the drain electrode 7 is provided on the conductive region 8,
Since the potential of the low-resistance region 2a is fixed to a potential substantially equal to the potential of the drain electrode, fluctuation and frequency dispersion of the drain current caused by charging and discharging of the deep well level can be reduced. In the above embodiment, the MESFET among the field effect transistors has been described as an example, but the same applies to the HEMT.

Next, an embodiment of a method for manufacturing a field effect transistor according to claim 4 will be described.

First, the high-resistance Si substrate 1 is set to 900 to 950.
After the heat treatment at a temperature of 400 ° C., the temperature is lowered to 400 to 450 ° C., and the GaAs film is formed at a temperature of 100 to 200 ° C. by MOCVD.
After the growth, the temperature was raised to 650 ° C. to grow a high-resistance buffer layer 2 having a thickness of 1 to 3 μm.
N-GaAs active layer 3 of about 10 ¹⁷ atoms · cm ⁻³
Is 0.1 to 0.2 μm and the doping density is 1 × 10 ¹⁸ to
An n ⁺ -GaAs ohmic contact layer 4 of 10 ¹⁹ atoms · cm ⁻³ is formed in a thickness of 0.1 to 0.2 μm (FIG. 2).
(A)).

Next, after mesa etching for element isolation,
Using the resist 9 or the like as a mask, the acceleration energy 100
KeV, Si at a dose of 1 × 10 ¹⁴ atoms · cm ⁻²
Is performed to form a conductive region 8. This ion implantation is performed under a controlled implantation condition until the ion implantation reaches the low resistance region 2a at the interface with the substrate 1 (FIG. 2).
(B)).

Next, the n ⁺ -GaAs layer 4 formed by crystal growth of the drain region was removed by isotropic wet etching using an acid-based etchant using a photoresist (not shown) as an etching mask. Thereafter, the etching mask is removed (FIG. 4C).

Next, a photoresist opening pattern (not shown) for forming a gate electrode is formed on the n ⁺ -GaAs ohmic contact layer 4, and this is used as a mask to form the ohmic contact layer 4 and, if necessary, the active layer 3. Is partially etched, and then Ti / Pt is formed on the active layer 3.
A gate electrode 5 made of / Au or Ti / Al or the like is formed by vapor deposition and lift-off, and source / drain electrodes 6 and 7 made of AuGe / Ni / Au or the like are formed. It is formed so as to be on the conductive region 8. As a result, the distance from the gate electrode to the conductive region 8 is formed smaller than the distance from the gate electrode to the source electrode.

FIG. 3 is a diagram showing an embodiment of the field-effect transistor according to the second aspect. In this field effect transistor, InGaAs, AlGa
Layers 9 having different energy band gaps, such as As and GaAsP, are inserted.

When the layer 9 having a different energy band gap from the material of the buffer layer 2 is inserted into the buffer layer 2 as described above, the leak current to the substrate 1 is reduced, and the withstand voltage of the buffer layer 2 is improved. Further, since the drain region is formed sufficiently away from the gate electrode 5, the gate breakdown voltage is equal to the breakdown voltage of the buffer layer 2. Therefore, a higher gate breakdown voltage can be obtained by inserting these layers 10. Note that the layers 9 having different energy band gaps are not limited to the case where one layer is inserted, but may be several hundred
The superlattice layer may be formed by inserting the layers several times at a time. The layers 9 having different energy band gaps may contain deep-level impurities such as O ₂ , Cr, and Fe.

[0034]

As described above, according to the field-effect transistor of the first aspect, the S from the surface of the compound semiconductor layer.
Since a conductive region reaching the vicinity of the interface with the i-substrate is provided, and the drain electrode is provided on the conductive region, GaAs
The -Si interface is always kept at substantially the same potential as the drain electrode, and it is possible to suppress the fluctuation of the drain current and the frequency dispersion caused by the deep level charge and discharge. Therefore, when an integrated circuit is formed using these transistors, it is possible to suppress a change in drain current with respect to the side gate voltage.

According to the method of manufacturing a field effect transistor according to the fourth aspect, after forming the compound semiconductor layer on the Si substrate, the surface portion of the compound semiconductor layer is used to remove the Si.
Impurity is ion-implanted to a region reaching the vicinity of the interface with the substrate to form a conductive region, a drain electrode is formed on this conductive region, and the distance from the gate electrode to the conductive region is the distance from the gate electrode to the source electrode. And a large gate breakdown voltage substantially equal to the breakdown voltage of the buffer layer can be obtained. Accordingly, the gate breakdown voltage can be further increased by using various high resistance buffer layers. Therefore, high output and high efficiency of the FET can be achieved. Further, since the source region is formed by the epitaxial growth method and is formed simultaneously with the gate electrode, the parasitic resistance between the gate and the source can be reduced. Therefore, the transconductance gm in the high frequency band can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a field-effect transistor according to claim 1;

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a field-effect transistor according to claim 4;

FIG. 3 is a sectional view showing one embodiment of a field-effect transistor according to claim 2;

FIG. 4 is a sectional view showing a conventional field effect transistor.

FIG. 5 is a cross-sectional view showing another conventional field effect transistor.

FIG. 6 is a sectional view showing another conventional field effect transistor.

[Explanation of symbols]

1 ‥‥‥ high-resistance Si substrate, 2 ‥‥‥ GaAs buffer layer, 3 ‥‥‥ n-GaAs active layer, 4 ‥‥‥ n ⁺ -Ga
As contact layer, 2-4 compound semiconductor layer, 5 ‥
{Gate electrode, 6} Source electrode, 7} Drain electrode, 8} Conductive region

Claims (4)

[Claims] 1. A semiconductor device comprising: a plurality of compound semiconductor layers stacked on a Si substrate; a source electrode and a drain electrode provided separately on the compound semiconductor layer; and a gate electrode provided between the source electrode and the drain electrode A field effect transistor, wherein a conductive region extending from the surface of the compound semiconductor layer to the vicinity of the interface with the Si substrate is provided, and the drain electrode is provided on the conductive region. 2. The electric field according to claim 1, wherein at least one layer having a different energy band gap is provided between the compound semiconductor layer serving as a channel in the compound semiconductor layer and the Si substrate. Effect transistor. 3. The field effect transistor according to claim 1, wherein a distance from said gate electrode to said conductive region is longer than a distance from said gate electrode to said source electrode. 4. After forming a buffer layer, an active layer, and a compound semiconductor layer serving as a contact layer on a Si substrate and performing mesa etching, a part of the contact layer is recess-etched to form a part of the active layer. Forming a gate electrode on an exposed portion of the active layer, and forming a source electrode and a drain electrode on contact layers on both sides of the gate electrode. After forming the semiconductor layer, an impurity is ion-implanted from a surface portion of the compound semiconductor layer to a region reaching the vicinity of the interface with the Si substrate to form a conductive region, and the drain electrode is formed on the conductive region. A method for manufacturing a field effect transistor, comprising: