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HK1201983A1 - 半導體器件製造方法和半導體器件 - Google Patents

半導體器件製造方法和半導體器件

Info

Publication number
HK1201983A1
HK1201983A1 HK15102305.9A HK15102305A HK1201983A1 HK 1201983 A1 HK1201983 A1 HK 1201983A1 HK 15102305 A HK15102305 A HK 15102305A HK 1201983 A1 HK1201983 A1 HK 1201983A1
Authority
HK
Hong Kong
Prior art keywords
semiconductor device
manufacturing
device manufacturing
semiconductor
Prior art date
Application number
HK15102305.9A
Other languages
English (en)
Inventor
Motoi Ishida
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of HK1201983A1 publication Critical patent/HK1201983A1/zh

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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
HK15102305.9A 2013-04-02 2015-03-06 半導體器件製造方法和半導體器件 HK1201983A1 (zh)

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US20090096073A1 (en) * 2007-10-16 2009-04-16 Kabushiki Kaisha Toshiba Semiconductor device and lead frame used for the same
US9972557B2 (en) * 2014-12-11 2018-05-15 Stmicroelectronics Pte Ltd Integrated circuit (IC) package with a solder receiving area and associated methods
US10037936B2 (en) * 2015-11-02 2018-07-31 Mediatek Inc. Semiconductor package with coated bonding wires and fabrication method thereof
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
CN110954034B (zh) * 2019-12-12 2021-06-11 深圳赛意法微电子有限公司 一种半导体器件的导线线弧高度测量方法
CN112435979B (zh) * 2020-09-30 2022-07-12 日月光半导体制造股份有限公司 引线单元及引线框架
US11728312B2 (en) * 2021-01-22 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packaging and methods of forming same

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JPH06302638A (ja) * 1993-04-16 1994-10-28 Sony Corp 半導体装置
JPH09266223A (ja) * 1996-03-28 1997-10-07 Nec Kyushu Ltd 半導体装置
JPH10326802A (ja) * 1997-05-26 1998-12-08 Seiko Epson Corp 半導体装置の製造方法
US6545347B2 (en) * 2001-03-06 2003-04-08 Asat, Limited Enhanced leadless chip carrier
US20020153600A1 (en) * 2001-04-19 2002-10-24 Walton Advanced Electronics Ltd Double sided chip package
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US7132735B2 (en) * 2005-03-07 2006-11-07 Agere Systems Inc. Integrated circuit package with lead fingers extending into a slot of a die paddle
JP2007180077A (ja) * 2005-12-27 2007-07-12 Renesas Technology Corp 半導体装置
US7816186B2 (en) * 2006-03-14 2010-10-19 Unisem (Mauritius) Holdings Limited Method for making QFN package with power and ground rings
TW200820402A (en) * 2006-10-26 2008-05-01 Chipmos Technologies Inc Stacked chip packaging with heat sink struct
US8283757B2 (en) * 2007-07-18 2012-10-09 Mediatek Inc. Quad flat package with exposed common electrode bars
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JP5130566B2 (ja) * 2008-07-01 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置
JP5404083B2 (ja) * 2009-02-10 2014-01-29 株式会社東芝 半導体装置
CN102157485B (zh) * 2011-03-23 2012-10-03 南通富士通微电子股份有限公司 一种半导体封装框架

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JP6164895B2 (ja) 2017-07-19

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