EP0397415A2 - Raster scan type printer - Google Patents
Raster scan type printer Download PDFInfo
- Publication number
- EP0397415A2 EP0397415A2 EP90304874A EP90304874A EP0397415A2 EP 0397415 A2 EP0397415 A2 EP 0397415A2 EP 90304874 A EP90304874 A EP 90304874A EP 90304874 A EP90304874 A EP 90304874A EP 0397415 A2 EP0397415 A2 EP 0397415A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- printing
- address
- codes
- data
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J3/00—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed
- B41J3/60—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed for printing on both faces of the printing material
Definitions
- the present invention relates to a raster scan type printer capable of executing printing operations on both surfaces of a printing medium.
- character and graphic images may be horizontally or vertically reversed on one surface of a printing medium, for example, a printing sheet.
- the images to be printed are electrically formed on a so-called page memory by means of software or dedicated hardware.
- the resultant images are written in an image buffer every bit and output to a printing mechanism section in which printing operations are executed.
- the above method causes the software to be complicated, further the printing time to be increased, or the dedicated hardware to increase the production cost.
- a raster scan type printing device capable of executing a printing operation on both surfaces of a printing medium, comprising storing means for storing a plurality of codes corresponding to the character and/or symbol data to be printed, and printing means for printing the data on said printing medium, said printing device further comprising: selecting means for selecting a predetermined surface of said printing medium on which a printing operation is executed; and controlling means for controlling the codes stored in said storing means so as to be rearranged at least in a scan direction when said predetermined surface of said recording medium is selected by said selecting means.
- FIG. 1 shows a block diagram of a raster scan type printer with both surfaces printing function embodying the present invention.
- the printer embodying the present invention is structured by an interface 2 for inputting code corresponding to the character and/or graphic data to be printed from an external host computer 1, a CPU (Central Processing Unit) 3 for controlling the entire printer when the data are inputted into the printer through the interface 2, a receiving buffer 4 for temporarily storing data codes having been inputted, a RAM (Random Access Memory) as a page memory 5 for storing the data every page, a ROM (Read Only Memory) 6 for storing a system control program, a CG (Character Generator) 7 for storing bit data such as characters according to codes, a DPRAM (Display RAM) as an image buffer 8 for storing image information according to the data written and stored in the page memory 5, a parallel-serial conversion circuit 9 for converting parallel output data from the DPRAM 8 into serial output data, a printing mechanism section, i.e., an engine 10 composed of a laser scanner and so forth for inputting bit data for one scan from the parallel-serial conversion circuit 9 and for printing
- the CPU 3 and the DPRAM 8 are electrically connected by a data bus 11, an address bus 12, and a control bus, not shown.
- an address reverse circuit i.e., address conversion circuit, 13 composed of an inverter 13-1 and an address selector 13-2 are disposed therein.
- a front/back surfaces printing selection signal "S" is input from the CPU 3 through an address decoder 14 and an operation is switched.
- the address data transmitted through a line indicated by a letter "F” in the drawing, which is not reversed is output.
- the address data transmitted through a line indicated by a letter "R”, which is reversed via the inverter 13-1 is output.
- the column addresses representing the horizontal addresses in a predetermined data unit are horizontally reversed when the writing operations from the page memory to the DPRAM 8 are executed by every bit.
- the above address decoder 14 as a transfer address change circuit for changing transfer addresses which are output from the CPU 3 and a timing generation circuit 15 for generating timing signals for the DPRAM 8 are respectively provided.
- the address signal and the front/back surface printing selection signal "S" are input from the CPU 3.
- the timing generation circuit 15 receives a transfer signal "T1" which is output from the address decoder 14 and outputs a predetermined DPRAM control timing signal "T2" to the DPRAM 8.
- the DPRAM control timing signals are chiefly classified as four types of signals, i.e., a write signal, a read signal, a transfer signal, and a refresh signal.
- a data reverse circuit 16 for reversing data every bit for back surface printing data is provided on a data line between the DPRAM 8 and the parallel-serial conversion circuit 9, a data reverse circuit 16 for reversing data every bit for back surface printing data is provided.
- the data reverse circuit 16 receives the front/back surface printing selection signal "S" and a printing operation state is switched between the data forward connection and the data reverse connection as hardware.
- the column addresses representing horizontal address data for the back surface are horizontally reversed every word including successive 16 bits (D0 through D15) data in one raster.
- Transfer address sections "a" and "b" for the front surface and the back surface operate in the manner that when some data are written to an address of the transfer address section from the CPU 3, the timing generation circuit 15 reads the address and the printing data for one raster according to the address is transferred from the DPRAM 8 to the parallel-serial conversion circuit 9.
- the data address being output from the CPU 3 is set so that the front surface printing data storage area "A” and the back surface printing data storage area “B” are separately written to the row addresses and the column addresses of the DPRAM 8, respectively.
- the storage locations of the transfer address sections "a” and “b” are set so that they differ in the respective printing data storage areas in the column address direction.
- the transfer address sections "a” and "b” viewed from the CPU 3 differ in the column address direction.
- the CPU 3 writes bit data to predetermined addresses of the DPRAM 8 according to page data, including address data, stored in the page memory 5.
- the DPRAM 8 reads one scan of data, for example, data for 4096 dots, according to the transfer addresses of the image bit data written in the DPRAM 8 according to predetermined address data and transfer signals from the CPU 3 and transfers the resultant data to the engine 10 via the parallel-serial conversion circuit 9, thereby printing the data to a predetermined position on the sheet.
- Image information is transferred from the DPRAM 8 to the engine 10 by assigning a predetermined address by the CPU 3 and by the timing signal "T2" which is output from the timing generation circuit 15 according to the transfer signal "T1" from the address decoder 14 according to the front/back surface printing selection signal "S".
- the address decoder 14 determines whether the data is a transfer command or not in accordance with the address data being read and the transfer address currently set. When the data is the transfer command, the address decoder 14 outputs the transfer signal "T1" to the timing generation circuit 15. After that, the timing generation circuit 15 outputs the signal "T2" to the DPRAM 8 in a predetermined timing.
- the address decoder 14 In this manner, in the case that the selection signal "S" from the CPU 3 represents the front surface, the address decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "a" is assigned. On the other hand, in the case that the selection signal "S" represents the back surface, the address decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "b" is assigned.
- FIGs. 3A and 3B show the condition where transfer addresses are reversed and printing data is reversed in one raster in the CPU 3, the DPRAM 8, and the engine 10.
- the printing data area is set to the left of one raster including 4096 dots, wherein dots 0 through 15: non-image portion; dots 16 through 2415: image portion; and dots 2416 through 4079: non-image portion.
- the transfer address section "a" is set to the right end, dots 4080 through 4095.
- the addresses are reversed between the CPU 3 and the DPRAM 8 by the address reverse circuit 13.
- the printing data storage area "B" and the transfer address section "b" of the back surface are set to the reverse locations of the front surface.
- the addresses of the DPRAM 8 are reversed in the column direction, i.e., horizontal direction in each of 16-bits data by means of the address reverse circuit 13 constituted by a predetermined hardware arrangement.
- the back surface data are horizontally reversed between the DPRAM 8 and the engine 10 by the data reverse circuit 16 every 16 bits.
- FIGs. 4A, 48 and 4C and FIGs. 5A, 5B and 5C show a conception of reversal of address data on the front surface and back surface at the page memory 5, the DPRAM 8, and the engine 10.
- the drawings show an example where each character is composed of 32 x 32 dots.
- characters are actually stored in the form of code data.
- FIGs. 5A through 5C for the data on the back surface, the storage locations of the data transferred from the CPU 3 to the page memory 5 are vertically reversed every character.
- the row addresses are vertically reversed every raster. This operation is performed by program software in the present embodiment.
- the column addresses are horizontally reversed by the address reverse circuit 13 every 16 bits.
- the 16 bit unit is horizontally reversed every bit by the data reverse circuit 16.
- the CPU 3 since the CPU 3 synchronizes with the transfer signal which is output depending on whether the printing surface is the front surface or the back surface and a predetermined address being assigned, it outputs each address of the transfer address section "a" for the data of the front surface to the engine 10 and that of the transfer address section "b" for the data of the back surface to the engine 10 only at a predetermined time, thereby preventing the data being mistakenly transferred.
- the CPU 3 it is not necessary for the CPU 3 to reverse the addresses in the column direction, only necessary to designate addresses of the DPRAM 8 even if a printing operation is executed on the back surface.
- the address conversion operation in the column direction are executed by means of a circuit including the address reverse circuit 13. Therefore, an arrangement of the software controlled by the CPU 3 can be simplified.
- the data from the DPRAM 8 is serially converted every 16 bits by the serial-parallel conversion circuit 9 via a forward connection or a reverse connection structured by hardware of the data reverse circuit 16 and then output to a controller of the engine 10. If such 16 bit data is assigned by software, a shift operation should be executed 16 times, resulting in taking a long process time. Since this operation is executed by hardware, without using complicated software, the operation time can be remarkably reduced.
- the vertical reverse operation is conducted by a program of the CPU and the horizontal reverse operation every bit in the predetermined data unit is conducted by the data reverse circuit 16.
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- Dot-Matrix Printers And Others (AREA)
- Record Information Processing For Printing (AREA)
- Laser Beam Printer (AREA)
Abstract
Description
- The present invention relates to a raster scan type printer capable of executing printing operations on both surfaces of a printing medium.
- When a double side printing operation is performed using a printing apparatus such as a laser printer, character and graphic images may be horizontally or vertically reversed on one surface of a printing medium, for example, a printing sheet. The images to be printed are electrically formed on a so-called page memory by means of software or dedicated hardware. The resultant images are written in an image buffer every bit and output to a printing mechanism section in which printing operations are executed. The above structure has been well known and utilized.
- However, the above method causes the software to be complicated, further the printing time to be increased, or the dedicated hardware to increase the production cost.
- It is therefore an object of the invention to provide an improved raster scan type printer with both surface printing function capable of simply executing a reversing operation of the data to be printed on the back surface.
- For this purpose, according to the present invention, there is provided a raster scan type printing device, capable of executing a printing operation on both surfaces of a printing medium, comprising storing means for storing a plurality of codes corresponding to the character and/or symbol data to be printed, and printing means for printing the data on said printing medium, said printing device further comprising:
selecting means for selecting a predetermined surface of said printing medium on which a printing operation is executed; and
controlling means for controlling the codes stored in said storing means so as to be rearranged at least in a scan direction when said predetermined surface of said recording medium is selected by said selecting means. - The invention will be better understood from the following description which is given by way of example only with reference to the accompanying drawings in which:
- FIG. 1 is a block structural diagram of a raster scan type printer with both surfaces printing function embodying the present invention;
- FIGs. 2A, 2B are diagrams showing the data storage state in an image buffer viewed from a controlling unit of the printer according to the present invention;
- FIGs. 3A, 3B are diagrams showing the reverse state of addresses of data to be printed on the back surface of a printing medium and data for one raster to be printed on both front and back surfaces; and
- FIGs. 4A, 4B, and 4C and FIGs. 5A, 58, and 5C are conceptual diagrams showing the reverse states of an image corresponding to the front and the back surfaces, respectively.
- FIG. 1 shows a block diagram of a raster scan type printer with both surfaces printing function embodying the present invention.
- As illustrated in FIG. 1, the printer embodying the present invention is structured by an interface 2 for inputting code corresponding to the character and/or graphic data to be printed from an external host computer 1, a CPU (Central Processing Unit) 3 for controlling the entire printer when the data are inputted into the printer through the interface 2, a
receiving buffer 4 for temporarily storing data codes having been inputted, a RAM (Random Access Memory) as apage memory 5 for storing the data every page, a ROM (Read Only Memory) 6 for storing a system control program, a CG (Character Generator) 7 for storing bit data such as characters according to codes, a DPRAM (Display RAM) as animage buffer 8 for storing image information according to the data written and stored in thepage memory 5, a parallel-serial conversion circuit 9 for converting parallel output data from theDPRAM 8 into serial output data, a printing mechanism section, i.e., an engine 10 composed of a laser scanner and so forth for inputting bit data for one scan from the parallel-serial conversion circuit 9 and for printing the data on a sheet, and so forth. - The
CPU 3 and the DPRAM 8 are electrically connected by a data bus 11, anaddress bus 12, and a control bus, not shown. Between theCPU 3 and theDPRAM 8, an address reverse circuit, i.e., address conversion circuit, 13 composed of an inverter 13-1 and an address selector 13-2 are disposed therein. To the addressreverse circuit 13, a front/back surfaces printing selection signal "S" is input from theCPU 3 through anaddress decoder 14 and an operation is switched. For the front surface, the address data, transmitted through a line indicated by a letter "F" in the drawing, which is not reversed is output. For the back surface, the address data, transmitted through a line indicated by a letter "R", which is reversed via the inverter 13-1 is output. When the printing operations are executed on the back surface of the sheet, the column addresses representing the horizontal addresses in a predetermined data unit are horizontally reversed when the writing operations from the page memory to theDPRAM 8 are executed by every bit. - In addition, the
above address decoder 14 as a transfer address change circuit for changing transfer addresses which are output from theCPU 3 and atiming generation circuit 15 for generating timing signals for theDPRAM 8 are respectively provided. To theaddress decoder 14, the address signal and the front/back surface printing selection signal "S" are input from theCPU 3. Thetiming generation circuit 15 receives a transfer signal "T1" which is output from theaddress decoder 14 and outputs a predetermined DPRAM control timing signal "T2" to theDPRAM 8. The DPRAM control timing signals are chiefly classified as four types of signals, i.e., a write signal, a read signal, a transfer signal, and a refresh signal. - On a data line between the DPRAM 8 and the parallel-
serial conversion circuit 9, a datareverse circuit 16 for reversing data every bit for back surface printing data is provided. The datareverse circuit 16 receives the front/back surface printing selection signal "S" and a printing operation state is switched between the data forward connection and the data reverse connection as hardware. In the present embodiment, the column addresses representing horizontal address data for the back surface are horizontally reversed every word including successive 16 bits (D0 through D15) data in one raster. - By referring to FIGs. 2A and 2B, an operation of the data storage area of the
DPRAM 8 for the front/back surface data in theCPU 3 is described hereinafter. Transfer address sections "a" and "b" for the front surface and the back surface operate in the manner that when some data are written to an address of the transfer address section from theCPU 3, thetiming generation circuit 15 reads the address and the printing data for one raster according to the address is transferred from theDPRAM 8 to the parallel-serial conversion circuit 9. - As illustrated in FIGs. 2A and 2B, the data address being output from the
CPU 3 is set so that the front surface printing data storage area "A" and the back surface printing data storage area "B" are separately written to the row addresses and the column addresses of theDPRAM 8, respectively. Therefor, the storage locations of the transfer address sections "a" and "b" are set so that they differ in the respective printing data storage areas in the column address direction. Thus, the transfer address sections "a" and "b" viewed from theCPU 3 differ in the column address direction. - In the above structure, the
CPU 3 writes bit data to predetermined addresses of theDPRAM 8 according to page data, including address data, stored in thepage memory 5. In addition, the DPRAM 8 reads one scan of data, for example, data for 4096 dots, according to the transfer addresses of the image bit data written in theDPRAM 8 according to predetermined address data and transfer signals from theCPU 3 and transfers the resultant data to the engine 10 via the parallel-serial conversion circuit 9, thereby printing the data to a predetermined position on the sheet. - Image information is transferred from the
DPRAM 8 to the engine 10 by assigning a predetermined address by theCPU 3 and by the timing signal "T2" which is output from thetiming generation circuit 15 according to the transfer signal "T1" from theaddress decoder 14 according to the front/back surface printing selection signal "S". In other words, depending on whether the printing surface assigned by theCPU 3 is the front surface or the back surface, one of the transfer address sections "a" and "b" is set to theaddress decoder 14. Theaddress decoder 14 determines whether the data is a transfer command or not in accordance with the address data being read and the transfer address currently set. When the data is the transfer command, theaddress decoder 14 outputs the transfer signal "T1" to thetiming generation circuit 15. After that, thetiming generation circuit 15 outputs the signal "T2" to theDPRAM 8 in a predetermined timing. - In this manner, in the case that the selection signal "S" from the
CPU 3 represents the front surface, theaddress decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "a" is assigned. On the other hand, in the case that the selection signal "S" represents the back surface, theaddress decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "b" is assigned. - FIGs. 3A and 3B show the condition where transfer addresses are reversed and printing data is reversed in one raster in the
CPU 3, the DPRAM 8, and the engine 10. In the case of the conventional A4 sheet size, on the front surface viewed from theCPU 3, the printing data area is set to the left of one raster including 4096 dots, wherein dots 0 through 15: non-image portion;dots 16 through 2415: image portion; and dots 2416 through 4079: non-image portion. The transfer address section "a" is set to the right end,dots 4080 through 4095. On the other hand, on the back surface, as described above, the addresses are reversed between theCPU 3 and theDPRAM 8 by the addressreverse circuit 13. Therefore, the printing data storage area "B" and the transfer address section "b" of the back surface are set to the reverse locations of the front surface. In other words, the addresses of theDPRAM 8 are reversed in the column direction, i.e., horizontal direction in each of 16-bits data by means of the addressreverse circuit 13 constituted by a predetermined hardware arrangement. In addition, as shown in FIG. 3B, the back surface data are horizontally reversed between the DPRAM 8 and the engine 10 by the datareverse circuit 16 every 16 bits. - FIGs. 4A, 48 and 4C and FIGs. 5A, 5B and 5C show a conception of reversal of address data on the front surface and back surface at the
page memory 5, the DPRAM 8, and the engine 10. The drawings show an example where each character is composed of 32 x 32 dots. In thepage memory 5, characters are actually stored in the form of code data. As illustrated in FIGs. 5A through 5C, for the data on the back surface, the storage locations of the data transferred from theCPU 3 to thepage memory 5 are vertically reversed every character. When data are transferred from thepage memory 5 to theDPRAM 8 every bit, the row addresses are vertically reversed every raster. This operation is performed by program software in the present embodiment. In addition, the column addresses are horizontally reversed by theaddress reverse circuit 13 every 16 bits. When the data are output from theDPRAM 8 to the engine 10, the 16 bit unit is horizontally reversed every bit by the data reversecircuit 16. - As described above, according to the present embodiment, since the
CPU 3 synchronizes with the transfer signal which is output depending on whether the printing surface is the front surface or the back surface and a predetermined address being assigned, it outputs each address of the transfer address section "a" for the data of the front surface to the engine 10 and that of the transfer address section "b" for the data of the back surface to the engine 10 only at a predetermined time, thereby preventing the data being mistakenly transferred. In other words, it is not necessary for theCPU 3 to reverse the addresses in the column direction, only necessary to designate addresses of theDPRAM 8 even if a printing operation is executed on the back surface. The address conversion operation in the column direction are executed by means of a circuit including theaddress reverse circuit 13. Therefore, an arrangement of the software controlled by theCPU 3 can be simplified. - In addition, the data from the
DPRAM 8 is serially converted every 16 bits by the serial-parallel conversion circuit 9 via a forward connection or a reverse connection structured by hardware of the data reversecircuit 16 and then output to a controller of the engine 10. If such 16 bit data is assigned by software, a shift operation should be executed 16 times, resulting in taking a long process time. Since this operation is executed by hardware, without using complicated software, the operation time can be remarkably reduced. - In the present embodiment, the vertical reverse operation is conducted by a program of the CPU and the horizontal reverse operation every bit in the predetermined data unit is conducted by the data reverse
circuit 16. These means can be also accomplished in different structures according to the present invention.
Claims (12)
selecting means for selecting a predetermined surface of said printing medium on which a printing operation is executed; and
controlling means for controlling the codes stored in said storing means so as to be rearranged at least in a scan direction when said predetermined surface of said recording medium is selected by said selecting means.
bit map memory means for saving the codes having been stored in said storing means as a bit map corresponding to said codes;
selecting means for selecting a predetermined surface of said printing medium on which a printing operation is executed;
address designating means for designating addresses for each of said codes;
address converting means, provided between said bit map memory means and said address designating means, for converting the addresses designated by said address designating means in a predetermined manner in a scan direction when said codes having been stored in said storing means are saved in said bit map memory means, when said predetermined surface of said recording medium is selected by said selecting means; and
another address converting means for converting at least the addresses designated by said address designating means in a row direction perpendicular to said scan direction when said codes having been stored in said storing means are saved in said bit map memory means, when said predetermined surface of said recording medium is selected by said selecting means.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP116693/89 | 1989-05-09 | ||
JP11669389A JPH02295772A (en) | 1989-05-09 | 1989-05-09 | Raster scan type perfecting printer |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0397415A2 true EP0397415A2 (en) | 1990-11-14 |
EP0397415A3 EP0397415A3 (en) | 1991-01-09 |
Family
ID=14693519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19900304874 Withdrawn EP0397415A3 (en) | 1989-05-09 | 1990-05-04 | Raster scan type printer |
Country Status (2)
Country | Link |
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EP (1) | EP0397415A3 (en) |
JP (1) | JPH02295772A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115122766A (en) * | 2021-03-26 | 2022-09-30 | 精工爱普生株式会社 | Liquid ejecting apparatus |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05174135A (en) * | 1991-12-26 | 1993-07-13 | Casio Electron Mfg Co Ltd | Data inverter |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3810223A1 (en) * | 1987-04-02 | 1988-10-20 | Minolta Camera Kk | DUPLEX PRINTING DEVICE |
EP0295612A1 (en) * | 1987-06-16 | 1988-12-21 | Canon Kabushiki Kaisha | Control method for a both-surface/multiplex recording apparatus |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63221044A (en) * | 1987-03-10 | 1988-09-14 | Fuji Xerox Co Ltd | One-sided and two-sided printing character generator |
JP3006764B2 (en) * | 1988-03-08 | 2000-02-07 | キヤノン株式会社 | Double-sided printing control device |
-
1989
- 1989-05-09 JP JP11669389A patent/JPH02295772A/en active Pending
-
1990
- 1990-05-04 EP EP19900304874 patent/EP0397415A3/en not_active Withdrawn
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3810223A1 (en) * | 1987-04-02 | 1988-10-20 | Minolta Camera Kk | DUPLEX PRINTING DEVICE |
EP0295612A1 (en) * | 1987-06-16 | 1988-12-21 | Canon Kabushiki Kaisha | Control method for a both-surface/multiplex recording apparatus |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115122766A (en) * | 2021-03-26 | 2022-09-30 | 精工爱普生株式会社 | Liquid ejecting apparatus |
CN115122766B (en) * | 2021-03-26 | 2023-06-20 | 精工爱普生株式会社 | Liquid ejecting apparatus |
Also Published As
Publication number | Publication date |
---|---|
EP0397415A3 (en) | 1991-01-09 |
JPH02295772A (en) | 1990-12-06 |
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