Nothing Special   »   [go: up one dir, main page]

EP0397415A2 - Drucker mit Abtastraster - Google Patents

Drucker mit Abtastraster Download PDF

Info

Publication number
EP0397415A2
EP0397415A2 EP90304874A EP90304874A EP0397415A2 EP 0397415 A2 EP0397415 A2 EP 0397415A2 EP 90304874 A EP90304874 A EP 90304874A EP 90304874 A EP90304874 A EP 90304874A EP 0397415 A2 EP0397415 A2 EP 0397415A2
Authority
EP
European Patent Office
Prior art keywords
printing
address
codes
data
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP90304874A
Other languages
English (en)
French (fr)
Other versions
EP0397415A3 (de
Inventor
Hajime Usami
Hiroyuki Funahashi
Masahiro Murakami
Kiyoshi Takahashi
Toru Tsuzuki
Ichiro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Brother Industries Ltd
Original Assignee
Brother Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brother Industries Ltd filed Critical Brother Industries Ltd
Publication of EP0397415A2 publication Critical patent/EP0397415A2/de
Publication of EP0397415A3 publication Critical patent/EP0397415A3/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J3/00—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed
    • B41J3/60—Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed for printing on both faces of the printing material

Definitions

  • the present invention relates to a raster scan type printer capable of executing printing operations on both surfaces of a printing medium.
  • character and graphic images may be horizontally or vertically reversed on one surface of a printing medium, for example, a printing sheet.
  • the images to be printed are electrically formed on a so-called page memory by means of software or dedicated hardware.
  • the resultant images are written in an image buffer every bit and output to a printing mechanism section in which printing operations are executed.
  • the above method causes the software to be complicated, further the printing time to be increased, or the dedicated hardware to increase the production cost.
  • a raster scan type printing device capable of executing a printing operation on both surfaces of a printing medium, comprising storing means for storing a plurality of codes corresponding to the character and/or symbol data to be printed, and printing means for printing the data on said printing medium, said printing device further comprising: selecting means for selecting a predetermined surface of said printing medium on which a printing operation is executed; and controlling means for controlling the codes stored in said storing means so as to be rearranged at least in a scan direction when said predetermined surface of said recording medium is selected by said selecting means.
  • FIG. 1 shows a block diagram of a raster scan type printer with both surfaces printing function embodying the present invention.
  • the printer embodying the present invention is structured by an interface 2 for inputting code corresponding to the character and/or graphic data to be printed from an external host computer 1, a CPU (Central Processing Unit) 3 for controlling the entire printer when the data are inputted into the printer through the interface 2, a receiving buffer 4 for temporarily storing data codes having been inputted, a RAM (Random Access Memory) as a page memory 5 for storing the data every page, a ROM (Read Only Memory) 6 for storing a system control program, a CG (Character Generator) 7 for storing bit data such as characters according to codes, a DPRAM (Display RAM) as an image buffer 8 for storing image information according to the data written and stored in the page memory 5, a parallel-serial conversion circuit 9 for converting parallel output data from the DPRAM 8 into serial output data, a printing mechanism section, i.e., an engine 10 composed of a laser scanner and so forth for inputting bit data for one scan from the parallel-serial conversion circuit 9 and for printing
  • the CPU 3 and the DPRAM 8 are electrically connected by a data bus 11, an address bus 12, and a control bus, not shown.
  • an address reverse circuit i.e., address conversion circuit, 13 composed of an inverter 13-1 and an address selector 13-2 are disposed therein.
  • a front/back surfaces printing selection signal "S" is input from the CPU 3 through an address decoder 14 and an operation is switched.
  • the address data transmitted through a line indicated by a letter "F” in the drawing, which is not reversed is output.
  • the address data transmitted through a line indicated by a letter "R”, which is reversed via the inverter 13-1 is output.
  • the column addresses representing the horizontal addresses in a predetermined data unit are horizontally reversed when the writing operations from the page memory to the DPRAM 8 are executed by every bit.
  • the above address decoder 14 as a transfer address change circuit for changing transfer addresses which are output from the CPU 3 and a timing generation circuit 15 for generating timing signals for the DPRAM 8 are respectively provided.
  • the address signal and the front/back surface printing selection signal "S" are input from the CPU 3.
  • the timing generation circuit 15 receives a transfer signal "T1" which is output from the address decoder 14 and outputs a predetermined DPRAM control timing signal "T2" to the DPRAM 8.
  • the DPRAM control timing signals are chiefly classified as four types of signals, i.e., a write signal, a read signal, a transfer signal, and a refresh signal.
  • a data reverse circuit 16 for reversing data every bit for back surface printing data is provided on a data line between the DPRAM 8 and the parallel-serial conversion circuit 9, a data reverse circuit 16 for reversing data every bit for back surface printing data is provided.
  • the data reverse circuit 16 receives the front/back surface printing selection signal "S" and a printing operation state is switched between the data forward connection and the data reverse connection as hardware.
  • the column addresses representing horizontal address data for the back surface are horizontally reversed every word including successive 16 bits (D0 through D15) data in one raster.
  • Transfer address sections "a" and "b" for the front surface and the back surface operate in the manner that when some data are written to an address of the transfer address section from the CPU 3, the timing generation circuit 15 reads the address and the printing data for one raster according to the address is transferred from the DPRAM 8 to the parallel-serial conversion circuit 9.
  • the data address being output from the CPU 3 is set so that the front surface printing data storage area "A” and the back surface printing data storage area “B” are separately written to the row addresses and the column addresses of the DPRAM 8, respectively.
  • the storage locations of the transfer address sections "a” and “b” are set so that they differ in the respective printing data storage areas in the column address direction.
  • the transfer address sections "a” and "b” viewed from the CPU 3 differ in the column address direction.
  • the CPU 3 writes bit data to predetermined addresses of the DPRAM 8 according to page data, including address data, stored in the page memory 5.
  • the DPRAM 8 reads one scan of data, for example, data for 4096 dots, according to the transfer addresses of the image bit data written in the DPRAM 8 according to predetermined address data and transfer signals from the CPU 3 and transfers the resultant data to the engine 10 via the parallel-­serial conversion circuit 9, thereby printing the data to a predetermined position on the sheet.
  • Image information is transferred from the DPRAM 8 to the engine 10 by assigning a predetermined address by the CPU 3 and by the timing signal "T2" which is output from the timing generation circuit 15 according to the transfer signal "T1" from the address decoder 14 according to the front/back surface printing selection signal "S".
  • the address decoder 14 determines whether the data is a transfer command or not in accordance with the address data being read and the transfer address currently set. When the data is the transfer command, the address decoder 14 outputs the transfer signal "T1" to the timing generation circuit 15. After that, the timing generation circuit 15 outputs the signal "T2" to the DPRAM 8 in a predetermined timing.
  • the address decoder 14 In this manner, in the case that the selection signal "S" from the CPU 3 represents the front surface, the address decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "a" is assigned. On the other hand, in the case that the selection signal "S" represents the back surface, the address decoder 14 outputs the transfer signal "T1" only when an address of the transfer address section "b" is assigned.
  • FIGs. 3A and 3B show the condition where transfer addresses are reversed and printing data is reversed in one raster in the CPU 3, the DPRAM 8, and the engine 10.
  • the printing data area is set to the left of one raster including 4096 dots, wherein dots 0 through 15: non-image portion; dots 16 through 2415: image portion; and dots 2416 through 4079: non-image portion.
  • the transfer address section "a" is set to the right end, dots 4080 through 4095.
  • the addresses are reversed between the CPU 3 and the DPRAM 8 by the address reverse circuit 13.
  • the printing data storage area "B" and the transfer address section "b" of the back surface are set to the reverse locations of the front surface.
  • the addresses of the DPRAM 8 are reversed in the column direction, i.e., horizontal direction in each of 16-bits data by means of the address reverse circuit 13 constituted by a predetermined hardware arrangement.
  • the back surface data are horizontally reversed between the DPRAM 8 and the engine 10 by the data reverse circuit 16 every 16 bits.
  • FIGs. 4A, 48 and 4C and FIGs. 5A, 5B and 5C show a conception of reversal of address data on the front surface and back surface at the page memory 5, the DPRAM 8, and the engine 10.
  • the drawings show an example where each character is composed of 32 x 32 dots.
  • characters are actually stored in the form of code data.
  • FIGs. 5A through 5C for the data on the back surface, the storage locations of the data transferred from the CPU 3 to the page memory 5 are vertically reversed every character.
  • the row addresses are vertically reversed every raster. This operation is performed by program software in the present embodiment.
  • the column addresses are horizontally reversed by the address reverse circuit 13 every 16 bits.
  • the 16 bit unit is horizontally reversed every bit by the data reverse circuit 16.
  • the CPU 3 since the CPU 3 synchronizes with the transfer signal which is output depending on whether the printing surface is the front surface or the back surface and a predetermined address being assigned, it outputs each address of the transfer address section "a" for the data of the front surface to the engine 10 and that of the transfer address section "b" for the data of the back surface to the engine 10 only at a predetermined time, thereby preventing the data being mistakenly transferred.
  • the CPU 3 it is not necessary for the CPU 3 to reverse the addresses in the column direction, only necessary to designate addresses of the DPRAM 8 even if a printing operation is executed on the back surface.
  • the address conversion operation in the column direction are executed by means of a circuit including the address reverse circuit 13. Therefore, an arrangement of the software controlled by the CPU 3 can be simplified.
  • the data from the DPRAM 8 is serially converted every 16 bits by the serial-parallel conversion circuit 9 via a forward connection or a reverse connection structured by hardware of the data reverse circuit 16 and then output to a controller of the engine 10. If such 16 bit data is assigned by software, a shift operation should be executed 16 times, resulting in taking a long process time. Since this operation is executed by hardware, without using complicated software, the operation time can be remarkably reduced.
  • the vertical reverse operation is conducted by a program of the CPU and the horizontal reverse operation every bit in the predetermined data unit is conducted by the data reverse circuit 16.

Landscapes

  • Dot-Matrix Printers And Others (AREA)
  • Laser Beam Printer (AREA)
  • Record Information Processing For Printing (AREA)
EP19900304874 1989-05-09 1990-05-04 Drucker mit Abtastraster Withdrawn EP0397415A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP116693/89 1989-05-09
JP11669389A JPH02295772A (ja) 1989-05-09 1989-05-09 ラスタスキャン方式の両面印刷装置

Publications (2)

Publication Number Publication Date
EP0397415A2 true EP0397415A2 (de) 1990-11-14
EP0397415A3 EP0397415A3 (de) 1991-01-09

Family

ID=14693519

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19900304874 Withdrawn EP0397415A3 (de) 1989-05-09 1990-05-04 Drucker mit Abtastraster

Country Status (2)

Country Link
EP (1) EP0397415A3 (de)
JP (1) JPH02295772A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115122766A (zh) * 2021-03-26 2022-09-30 精工爱普生株式会社 液体喷出装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05174135A (ja) * 1991-12-26 1993-07-13 Casio Electron Mfg Co Ltd データ反転装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63221044A (ja) * 1987-03-10 1988-09-14 Fuji Xerox Co Ltd 片面及び両面プリント用文字発生装置
DE3810223C2 (de) * 1987-04-02 1994-05-26 Minolta Camera Kk Duplex-Drucksystem
DE3866600D1 (de) * 1987-06-16 1992-01-16 Canon Kk Verfahren zur steuerung einer vorrichtung zum beidseitigen und mehrfachen kopieren.
JP3006764B2 (ja) * 1988-03-08 2000-02-07 キヤノン株式会社 両面印字制御装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115122766A (zh) * 2021-03-26 2022-09-30 精工爱普生株式会社 液体喷出装置
CN115122766B (zh) * 2021-03-26 2023-06-20 精工爱普生株式会社 液体喷出装置

Also Published As

Publication number Publication date
EP0397415A3 (de) 1991-01-09
JPH02295772A (ja) 1990-12-06

Similar Documents

Publication Publication Date Title
EP0131966B1 (de) Schrittformatüberlagerungs-Druckvorrichtung
US5012434A (en) Apparatus and method for selective rotation of data printed by a matrix printer
US5382968A (en) Raster image serial printer having variable buffer memory and method for operating same
JPH0417459B2 (de)
EP0690410B1 (de) Drucker mit rollierendem Drucker-Pufferspeicher, und Druckverfahren
US4475162A (en) Output device for providing information by scan
US4642622A (en) Video signal generating circuit
US4623978A (en) Print control apparatus having line buffer
EP0397415A2 (de) Drucker mit Abtastraster
JPH01136770A (ja) プリンタ
EP0072708B1 (de) Drucker
EP0284260B1 (de) Drucker vom Rasterabtasttyp
JPH0616764Y2 (ja) ドットマトリクスプリンタ
JP2650416B2 (ja) ラスタスキャン方式の両面印刷装置
JPS5941051A (ja) 文字パタ−ン発生装置
JP3059618B2 (ja) 画像制御装置
JP2748004B2 (ja) 文字パターン群の回転処理方法
JPH024915B2 (de)
JPS6163891A (ja) 書式回転方式
JPH0867034A (ja) プリンタ装置および同装置に使用されるバッファメモリのアドレス制御方法
JPH064344B2 (ja) 印字装置
JPS61106264A (ja) 図形出力制御装置
JPH0644015A (ja) 印刷方法及び装置
JPS61135274A (ja) 文字発生制御装置
JPS6137441A (ja) ドツトプリンタの高速印字処理方式

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

RHK1 Main classification (correction)

Ipc: B41J 3/60

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB

17P Request for examination filed

Effective date: 19910612

17Q First examination report despatched

Effective date: 19930211

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19930622