Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
  • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
  • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains

Definitions

• This invention relates to counting apparatus and, more particularly, to counting apparatus that is composed of a plurality of subcounters each one of which provides at its output at least two states.
• counting apparatus is defined as apparatus that provides an indication at its output that a predetermined number of transitions have been presented to its input.
• the counting apparatus may be comprised of a plurality of subcounters each one of which may in turn be defined as a state machine which passes sequentially through N states advancing always from the i to the i+1 state when clocked
• a faster counting apparatus is provided in accordance with the present invention wherein the counting apparatus is comprised of a plurality of subcounters that are independent from each other in the sense that no subcounter depends on any of the other subcounters for the development of its output state.
• each subcounter is chosen to provide a maximum number of states at its output that belongs to a set of relatively prime factors of the predetermined number, N, which is the number of input transitions that occur before an output indication is given by the apparatus.
• FIG. 1 is a counting apparatus constructed in accordance with the prior art
• FIG. 2 is a counting apparatus constructed in accordance with the present invention
• FIG. 3 is a chart of the output states provided by the counter circuits in FIG. 2.
• FIG. 1 One prior art technique of constructing a counting apparatus that will generate an output indication after a predetermined number of input transitions is illustrated in FIG. 1.
• counting circuits 101 , 102 and 103 are connected such that the input transitions are provided by way of a clock line 104 to the input of a counter circuit 101.
• the transitions referred to in this patent specification are changes in voltage with respect to some reference potential.
• the transition typically forms the leading edge of a voltage pulse, the required duration of which depends on the technology used to implement the counter circuits.
• Counter circuit 101 and two additional counter circuits 102 and 103 are initially cleared to their zero states by a transition on the clear line 105 which sets the counters to some predetermined output.
• FIG. 1 apparatus and the FIG.
• this cleared output is simply a binary zero on each of the output lines provided by the counting circuits.
• each transition on clock line 104 causes counter circuit 101 to change the binary word provided at its output on lines 106 through 108 thereby advancing counter circuit 101 through all of its M-
• a transition is provided on line 109 to the clock input of counter circuit 102. This initial transition on line 109 causes counter circuit 102 for the first time to change from the state provided on its output lines 110 through 112 after the• reset transition on clear line 105.
• the binary output lines of all counter circuits are connected to a word detector 120 which is constructed to recognize some predetermined pattern of binary states provided on these output lines before it generates a transition on its output line 121 to indicate that N transitions have occurred on the clock input line 104.
• the output indication on line 121 from word detector 120 can only be checked after counter circuits 101 through 103 have been permitted to stabilize or settle, that is permitted to respond to transitions that are developed on lines 109 and 113. This required period of stabilization is the primary factor in limiting the speed of the ripple counter shown in FIG. 1.
• each of the counter circuits 102 and 103 respond directly to transitions on a common clock line.
• the counter 102 will remain in the same state at each clock transition unless an enabling signal is present on line 109.
• counter circuit 103 will not advance its count unless an enabling signal is present on line 113 when a transition occurs on the clock input line.
• the output indication on line 121 from word detector 120 can only be checked after the output lines of counts 101-103 have stabilized.
• the amount of time needed for counter circuits 102 and 103 to develop the outputs 110-112 and 114-116 after a clock transition will be longer due to dependence on the enable inputs 109 and 110 than for counters which have no such dependence on enable inputs. This will determine the overall speed at which transitions can occur on the clock line.
• a counting apparatus may be constructed in accordance with the present invention by first factoring the number, N, which designates the number of input transitions that are to occur before an output indication is given, into a set of relatively prime factors.
• N designates the number of input transitions that are to occur before an output indication is given
• integers are said to be relatively prime if the greatest common divisors of the integers is a unit, for example, 8 and 15 are relatively prime even though neither is a prime number.
• Counter circuits are then chosen so that each counter circuit provides a maximum number of output states equal to a different one of the relatively- prime factors in the set of relatively prime factors. These counter circuits are connected as shown in FIG. 2 with the input transitions on clock line 204 being connected to each of the counter circuits 201, 202 and 203. As indicated in FIG. 2, counter circuit 201 provides K- j states at its output, counter circuit 202 provides K 2 states at its output, and counter circuit 203 provides K3 states at its output.
• Each of the counter circuits 201 through 203 are first cleared by a transition on the clear line 205 before the count of input transitions on line 204 begins.
• This transition on the clear line presets each of. the counter circuits to some predetermined state which in the case of the present embodiment is the state during which there is a binary zero on each of the output lines from all of the counter circuits.
• the output lines 206 through 208, 210 through 212, and 214 through 217 are connected to a word detector 220.
• This word detector 220 provides an output indication on line 221 when a predetermined binary pattern is provided on the output lines from counter circuits 201 through 203.
• counter circuits 201 , 202 and 203 are independent of each other in that the output of any one of the counter circuits is in no way dependent on the state achieved by any of the other counter circuits. Each is connected to respond to the input transitions on clock line 204.
• Clock circuit 205 is designed to provide five different binary states on its output lines 206 through 208
• counter circuit 202 is designed to provide eight different output states on its output lines 210 through 212
• clock circuit 203 is designed to provide nine different output states on its output lines 214 through 217.
• the state assignments chosen for the counter circuits 201-203 in the embodiment of FIG. 2 are illustrated in the table set forth in FIG. 3. All of the counter circuits are reset to their S n state by the appearance of a transition on clear line 205.
• counter 201 consists of a state machine with three binary output lines, which machine is caused to recycle after its 5 state S ⁇ .
• Counter circuit 202 is a state machine with three binary output lines, which machine is caused to cycle through all of its eight states.
• Counter circuit 203 is a state machine with four binary output lines, and the machine is caused to recycle after its 9 state, Sg.
• Word detector 220 is constructed to provide an output indication on line 221 when counter 201 has the binary word 1XX at its output, counter 202 has the binary word 110 at its output, and counter 203 has the binary word 1XXX at its output.
• the symbol X indicates that either binary zero or one may be present.
• Each of these .counters 201-203 may be constructed by circuits that are well known to those skilled in the art. Any sequence of binary numbers may be assigned, of course, to the counter states within counters 201-203.
• FIG. 3 represents only one possible choice. See, for example, the synchronous binary counters described in Chapters 4 and 10 of the text "Electronic Counters", R. M. M. Oberman, Copyright 1973, the McMillan Press Ltd. Chapters 4 and 10 of this text provide schematic block diagrams of arrangements that can be used for each of these counter circuits.
• a different number of counting stages may be used to provide counting apparatus to indicate other predetermined numbers of input transitions or even the same number of input transitions.
• a counting apparatus that is designed to give an indication after 900 input transitions may be constructed either with counting circuits that provide 4, 9 and 25 output states, or with counter circuits that provide 36 and 25 output states, or even with counting apparatus that provide 4 and 225 output states.
• the maximum number of output states need only be related to each other by the above-stated principles of being relatively prime.
• the principles of the present invention are equally applicable when the counter circuits provide output words in something other than the binary system.

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• Manipulation Of Pulses (AREA)

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• 1985
  • 1985-02-15 JP JP85500985A patent/JPS61501421A/ja active Pending
  • 1985-02-15 WO PCT/US1985/000265 patent/WO1985004297A1/en not_active Application Discontinuation
  • 1985-02-15 EP EP19850901244 patent/EP0187758A1/de not_active Withdrawn

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