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DE69840889D1 - Chemisch-mechanisches Polieren für die Planarisierung isolierender Dielektrika - Google Patents

Chemisch-mechanisches Polieren für die Planarisierung isolierender Dielektrika

Info

Publication number
DE69840889D1
DE69840889D1 DE69840889T DE69840889T DE69840889D1 DE 69840889 D1 DE69840889 D1 DE 69840889D1 DE 69840889 T DE69840889 T DE 69840889T DE 69840889 T DE69840889 T DE 69840889T DE 69840889 D1 DE69840889 D1 DE 69840889D1
Authority
DE
Germany
Prior art keywords
planarization
chemical
mechanical polishing
insulating dielectrics
dielectrics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69840889T
Other languages
English (en)
Inventor
Leif C Olsen
Leland S Swanson
Henry L Edwards
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69840889D1 publication Critical patent/DE69840889D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69840889T 1997-12-23 1998-12-22 Chemisch-mechanisches Polieren für die Planarisierung isolierender Dielektrika Expired - Lifetime DE69840889D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6866197P 1997-12-23 1997-12-23
US8621598P 1998-05-21 1998-05-21

Publications (1)

Publication Number Publication Date
DE69840889D1 true DE69840889D1 (de) 2009-07-23

Family

ID=26749214

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69840889T Expired - Lifetime DE69840889D1 (de) 1997-12-23 1998-12-22 Chemisch-mechanisches Polieren für die Planarisierung isolierender Dielektrika

Country Status (3)

Country Link
EP (1) EP0926715B1 (de)
JP (1) JPH11251271A (de)
DE (1) DE69840889D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054379A (en) 1998-02-11 2000-04-25 Applied Materials, Inc. Method of depositing a low k dielectric with organo silane
US6303523B2 (en) 1998-02-11 2001-10-16 Applied Materials, Inc. Plasma processes for depositing low dielectric constant films
US6660656B2 (en) 1998-02-11 2003-12-09 Applied Materials Inc. Plasma processes for depositing low dielectric constant films
US6593247B1 (en) 1998-02-11 2003-07-15 Applied Materials, Inc. Method of depositing low k films using an oxidizing plasma
US6287990B1 (en) 1998-02-11 2001-09-11 Applied Materials, Inc. CVD plasma assisted low dielectric constant films
US6667553B2 (en) 1998-05-29 2003-12-23 Dow Corning Corporation H:SiOC coated substrates
US6159871A (en) 1998-05-29 2000-12-12 Dow Corning Corporation Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
CN1422314A (zh) 2000-04-11 2003-06-04 卡伯特微电子公司 用于优先除去氧化硅的系统
US6764958B1 (en) 2000-07-28 2004-07-20 Applied Materials Inc. Method of depositing dielectric films
US6465366B1 (en) * 2000-09-12 2002-10-15 Applied Materials, Inc. Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
US6531398B1 (en) 2000-10-30 2003-03-11 Applied Materials, Inc. Method of depositing organosillicate layers
US6537733B2 (en) 2001-02-23 2003-03-25 Applied Materials, Inc. Method of depositing low dielectric constant silicon carbide layers
US6583053B2 (en) * 2001-03-23 2003-06-24 Texas Instruments Incorporated Use of a sacrificial layer to facilitate metallization for small features
US6709721B2 (en) 2001-03-28 2004-03-23 Applied Materials Inc. Purge heater design and process development for the improvement of low k film properties
US20020177321A1 (en) 2001-03-30 2002-11-28 Li Si Yi Plasma etching of silicon carbide
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing
US6486082B1 (en) 2001-06-18 2002-11-26 Applied Materials, Inc. CVD plasma assisted lower dielectric constant sicoh film
EP1271631A1 (de) 2001-06-29 2003-01-02 Interuniversitair Micro-Elektronica Centrum Vzw Herstellungsverfahren von Halbleiteranordnungen unter Verwendung eines chemisch-mechanischen Polierens
US6936309B2 (en) 2002-04-02 2005-08-30 Applied Materials, Inc. Hardness improvement of silicon carboxy films
US6815373B2 (en) 2002-04-16 2004-11-09 Applied Materials Inc. Use of cyclic siloxanes for hardness improvement of low k dielectric films
US7238393B2 (en) 2003-02-13 2007-07-03 Asm Japan K.K. Method of forming silicon carbide films
US7138332B2 (en) 2003-07-09 2006-11-21 Asm Japan K.K. Method of forming silicon carbide films
US20050056810A1 (en) * 2003-09-17 2005-03-17 Jinru Bian Polishing composition for semiconductor wafers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498565A (en) * 1991-11-29 1996-03-12 Sony Corporation Method of forming trench isolation having polishing step and method of manufacturing semiconductor device
US5362669A (en) * 1993-06-24 1994-11-08 Northern Telecom Limited Method of making integrated circuits

Also Published As

Publication number Publication date
JPH11251271A (ja) 1999-09-17
EP0926715A2 (de) 1999-06-30
EP0926715B1 (de) 2009-06-10
EP0926715A3 (de) 1999-12-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition