DE3226764A1 - Arrangement for converting a measurement voltage to a constant amplitude whilst retaining its frequency - Google Patents

Abstract

In the main application P 3205683.4-35, the measurement voltage is converted into a squarewave voltage and supplied to a switched-capacitor filter (9), the cut-off frequency of which is 1/100 of the clock frequency at the input (92). Extracting the clock frequency from the measurement frequency is done by a PLL circuit, in the control loop of which a stepping-down by a factor of 128 is carried out. The present arrangement replaces closed-loop control by open-loop control. A high-frequency pulse sequence of a generator (4) is used for determining the duration of a period of the measurement voltage (UM) by means of a counter (3). A pulse shaper stage (2) following the limiter circuit (1) supplies the signals for the beginning and end of a period. They also control the transfer of the count into a memory (5), from where a count corresponding to the duration of one period :256 is transferred into a counter (6) and a count corresponding to a duration of the period :128 is transferred into a counter (7). Both counters are counted down by the high-frequency pulse sequence. When the count drops below the stored value, the output (74) of the counter (7) outputs a signal which loads both counters with a new value from the memory (5). The output (64) of the sign stage of the counter (6) is directly used as clock signal source. <IMAGE>

Description

Arrangement for converting a measuring voltage while maintaining it

their frequency to constant amplitude The invention relates to a Arrangement for converting a measuring voltage with changing amplitude and within a certain range of any frequency into a voltage of the same Constant amplitude frequency according to the preamble of claim 1.

Such an arrangement is the subject of the main application P 32 05 683.4-35. To derive a signal that controls the cut-off frequency of the low-pass filter from the Frequency fM of the measuring voltage, a PLL circuit is used in its control loop a reduction stage is inserted.

The phase comparator of the PLL circuit compares each of the Measurement voltage with the voltage reduced in time by the factor m, so that at the input the reduction stage a voltage of the frequency m is obtained by regulation, which is used as a clock signal to control the cut-off frequency of the low-pass filter. Disadvantageous in this solution is the time required for the regulation. During this settling time, which can be several hundred ms occur because of the wandering limit frequency of the low-pass filter on output voltages with different distortion factors. you disturb especially when switching on but also when wobbling, as they falsify the measurement results can, unless you drive slowly enough through the wobble area.

The invention is based on the object in an arrangement of type mentioned at the beginning of the derivation of the clock signal for controlling the cutoff frequency to accelerate the low-pass filter from the measurement voltage and thereby faster sweeps to enable. This task is achieved by the characterizing features of the claim 1 solved.

This solution differs from the older solution in that that the frequency fT of the clock signal from the frequency fM of the measuring voltage directly through Determining the respective period of the measurement voltage is derived so that it there is no settling as with a regulation.

Appropriate refinements of the invention are set out in the subclaims marked.

In the following the invention is based on an embodiment, which is shown in the drawing, explained.

1 shows the block diagram of the exemplary embodiment, FIG. 2 shows a timing diagram for FIG. 1.

The measurement voltage UM to be converted is one in the arrangement of FIG Limiter circuit 1 supplied, which they - as in the main application - in a square wave voltage of the same frequency fM. A signal shaper circuit 2 derives from the positive Flanks of this square-wave voltage positive pulses from and off the negative flanks negative impulses.

A downstream counter 3, at whose counting input 32 a quartz stabilized Generator 4 is connected, is connected to its control input 31 by the positive pulses of the signal shaping circuit 2 set to zero and restarted. This happens after a full period of the square-wave voltage with the frequency has elapsed fM.

The negative pulses from the signal conditioning circuit become the control input 52 of a memory 5 and cause a takeover when they occur the respective count of the counter 3 via p parallel input lines 51 in the memory 5. This happens in each case with an interval of a full period of the Square-wave voltage with frequency fM, but by a half period compared to the start of the counter offset. Thus, the memory 5 always takes one of the duration of a half period the measuring voltage UM proportional count value, and this corresponds to the quotient from the generator frequency and twice the measuring frequency fM.

Instead of the offset transfer of the counter reading into the memory 5 a simultaneous transfer with the start of the counter is also possible. The half-period offset was chosen in the exemplary embodiment because the relevant signals in the overall arrangement, to which the subject of the registration belongs, still control other processes. For the principal However, this is irrelevant to the function of the subject of the application.

In the exemplary embodiment, frequencies fM are between 200 Hz and 3500 Hz to be considered. The generator 4 gives a constant frequency fK of 10 MHz away. Consequently, at == 200 Hz a count of 25000 in the memory 5 transferred, with fM = 3500 a count value of 1428. This sets a counter 3 with at least 15 steps ahead, memory 5 must also have at least 15 steps (p # 15).

Of these p stages of the memory 5, the most significant are over q Output lines connected to q parallel inputs 62 of a +/- counter 6, the same the q output lines and a further output line 53 lead to q + l parallel inputs 72 of another +/- counter 7.

With q = p-7, a count reduction by a factor of 128 is achieved; q + l is then p-6 and results in a reduction by a factor of 64. The +/- counter 6 therefore receives the 128th part of the in memory at the time of takeover 5 contained count value, while the +/- counter 7 the 64th part of this count value gets fed.

Since the count value in memory 5 corresponds to the quotient fK / 2fM the count value fK / 256fM transferred to the +/- counter 6 and that to the +/- counter 7 count value transferred fK / 128fM-The highest count value that got into the + / - counter 7 here is 390, which requires a counter with at least 9 levels. For the +/- counter 6 is the highest count 195; but it contains at least one more level above the 8 levels required for the value 195, so it has at least 9 levels. The additional stage serves as a sign stage. It leads with a positive sign low potential, with a negative sign of the counter reading high potential.

The inputs 61 and 71 of both + / - counters 6 and 7 are on the clock generators 4 and are connected in 10 MHz clock with pulses that they count backwards, applied.

In each case when the + / - counter 7 follows the counter reading 0 Receives a pulse, it emits an overflow signal at output 74, which is sent to the control inputs 63 and 73 of both + / - counters 6 and 7 and their reset as well as the new one Takeover of the 128 resp.

64 divided count from memory 5 in the +/- counters 6 and 7 caused.

The output 64 of the most significant stage of the + / - counter 6 is at the Clock input 92 of the switched capacitor filter 9 is connected. This exit lies after each new count has been accepted, always at low potential until the counter through the downward pulses below 0, i.e. in the negative counting range, is brought.

Then it jumps into the high potential state. This happens when the number of pulses emitted by the generator 4 corresponds to the number originally accepted Count has reached, with the rising edge of the following pulse.

Since the count value accepted is fK / 256fM, the above takes place Theoretically, jump at a point in time given by (l / fK) '(fK / 256fM) = 1 / 256fM after the overflow signal of the + / - counter 6. This is practical because of the digital Processing a slight deviation of 1 / fK = 0.1 As possible. The high potential is now at output 64 until the next overflow signal appears at output 74. This comes through to you (1 / fK). (FK / 128fM) = 1 / 128fM (+ possibly 0.1 µs) specified time. As a result, a square-wave signal appears at the output 64 the period 1 / 128fM and the frequency 128fM.

This signal serves as the clock signal for the switched capacitor filter 9 and causes its cutoff frequency fg, which is always a hundredth of the clock frequency is here. 1.28 sc.

Fig. 2 shows the signal curves described using the example of the measuring frequency 1000 Hz. The count of the counter 3 transferred to the memory 5 after a Half-period is 5000 in this case, which is what is shown in line a of FIG Dual value, assuming a 16-level memory.

The two + / - counters 6 and 7, which are assumed to have 12 levels here, immediately after the transfer of the signals on lines q and 53 show the in the Lines b and c show counter readings which correspond to the decimal values 39 and 78.

The signal from the generator 4 is shown in line d.

Since it has a frequency fK of 10 MHz, those in line i correspond entered intervals of 0.1 µs each. Line e shows the signal curve on the first (least significant) level of the + / - counter 6. It is set in the event of an overflow signal from the Counter 7, shown in line h, is set to 1 because the last bit in line b is 1 is. In the following intervals 1-78 it changes periodically between 0 and 1 back and forth. At the beginning of the 79th interval, an overflow signal occurs again and sets this level to 1.

In line f is the output signal of the most significant stage of the +/- counter 6 can be seen, which is also the signal at the output 64 of FIG. The person in question Level is set to 0 with the first overflow signal in line h and remains until including the 40th interval to 0.

In the 40th interval, all stages of counter 6 have assumed the zero position. With the beginning of the 41st interval they all take on the value 1, including the Highest level in line f. This value would be retained for another 211 intervals but at the beginning of interval 80, the stage is overflowed by the overflow signal reset to 0 again.

Line g shows the signal curve at the first stage of counter 7. Since the last bit in line c is 0, it is always out of phase with that of the first Level of counter 6 in line e. All levels of the +/- counter are in the 79th interval 7 in the O-position. Therefore, the overflow signal occurs at the beginning of the 80th interval Line h and resets the first stage of counter 7 to 0.

In the example under consideration, a square-wave signal occurs at the output 64 of FIG. 1 the period of 7.9 microseconds (line f in Fig. 2). This corresponds to a frequency of 126 582 Hz. The cutoff frequency fg of the switched capacitor filter 9 is derived from this to 1265.82 Hz.

Theoretically it should be 1280 Hz, but this deviation which is based on an uncertainty of 1 interval of 0.1 µs in the period of the clock signal does not matter, especially since the period is only around 0.1 µs elevated which shifts the cut-off frequency down a little. On the measuring voltage, which act as an anti-aliasing filter to the switched capacitor filter 9 Low-pass filter 8 is supplied, this shift has no effect.

The arrangement of a low-pass 8 in front of and a low-pass 10 behind the switched capacitor filter 9 is here as in the arrangement of the main application taken to prevent components of the clock signal frequency from being sent to the signal input 91 and can get to exit 11.

The measurement voltage UM to be converted is converted into square-wave voltages fed directly to the low-pass filter 8 through the limiter circuit 1. After going through of the switched capacitor filter 9, it appears more appropriate as a sinusoidal voltage Frequency, but constant amplitude at its output 93 and can at output 11 of the downstream low-pass filter 10 can be removed.

As with the main application, you can also use the signal conditioning circuit here 2 switch a reduction stage with the reduction factor 2, which has the effect that only full periods of the measuring voltage UM are evaluated, so that inaccuracies No incorrect setting of the switched capacitor filter in the zero crossings 9 bring about. The frequency division in the transition between the memory 5 and the + / - counters 6 and 7 must then by the factors 256 and 128 (instead of 128 and 64) happen. This reduction has the further advantage that it increases the accuracy. with which the cut-off frequency is derived from the measuring frequency, because it increases the Resolution refined by a factor of 2.

The time until the correct setting of the cut-off frequency fg has elapsed with half-period evaluation between 0.15 ms for 3500 Hz and 2.5 ms for 200 Hz It doubles the evaluation of entire periods, i.e. a maximum of 5 ms.

This is fast enough, even when wobbling, especially when there is a change the frequency fM of the measuring voltage no undefined states as in a regulation occur, but the previous cut-off frequency is still a fraction of a millisecond until a few milliseconds is maintained.

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Claims (5)

Claims arrangement for converting a measuring voltage with itself changing amplitude and within a certain range of any frequency into a voltage of the same frequency with constant amplitude, at which the Measurement voltage by means of a limiter circuit (1) into a square-wave voltage of each same frequency fM is converted to a low-pass controllable cutoff frequency fg is supplied, and the cut-off frequency fg by one from the frequency fM of the measuring voltage derived signal according to the relationship: fg = Y is controlled to fM, where 1 < y <2, according to patent application P 32 05 683.4-35, characterized in that the switched capacitor filter used as a low-pass controllable cut-off frequency (9) of known design, the cutoff frequency fg of which is determined by the frequency fT of a clock signal is determined, a clock signal is supplied whose frequency fT by the frequency fM of the measuring voltage is controlled by the period 1 / M of the measuring voltage by counting with a signal emitted by a generator (4) of the constant Frequency fK is determined and the counter value corresponding to fK / fM is reduced by a factor of a which corresponds to twice the desired ratio of fT / fM, and by a counter circuit (6) to which the signal of the frequency fK is applied is, in each case when their counter reading agrees with the corresponding fK / afM Value - the alternating application of low and high potential to the clock signal input (92) of the switched capacitor filter (9) is controlled (Fig. 1). 2. Arrangement according to claim 1, characterized in that as a counter circuit (6) a + / - counter is used, which uses its respective initial value fK / afM the frequency fK counts down, and a second +/- counter (7) is inserted, which is loaded to an initial value of 2fK / afM and then also with the frequency fK is counted backwards, with the second +/- counter (7), the period duration of the clock signal, both +/- counters when it falls below its 0 position (6 and 7) resets and loading with new initial values fK / afM and 2fK / afM controls, while the first +/- counter (6) is both positive and negative Area is operated and the output (64) of its sign stage directly the Supplies clock signal. 3. Arrangement according to one or more of the preceding claims, characterized in that the reduction of the count value fK / fM by the factor a or a / 2 is effected in that of p stages of a memory (5) in which this Counter value is stored, only the outputs of the upper q or q + l stages are continued are, where 2p-q = a resp. 2P-q-1 = a / 2. 4. Arrangement according to one or more of the preceding claims, characterized in that for counting the period l / fM of the measuring voltage a counter (3) with p steps is used, the counting input (32) of which with the generator (4) connected to the constant frequency fK and its control input (31) is connected to the output of a pulse shaper circuit (2), which consists of the measuring voltage converted into a square wave voltage at a certain phase position, preferably 0 ° or 3600, a start signal for the counter (3) derives and at one other phase position, preferably 1800, to the control input 52 of the memory (5) incoming signal to take over what is pending on p outputs of counter (3) Count value generated on corresponding inputs (51) of the memory (5). 5. Arrangement according to one or more of the preceding claims, characterized in that the pulse shaping circuit (2) has a reduction stage is connected upstream by a factor of 2, so that only with full periods of the measuring voltage UM alternating start signals for the counter (3) and acceptance signals for the memory (5) can be derived from the measurement voltage.