DE2232801A1 - DEVICE FOR DATA TRANSFER - Google Patents

Description

Device for data transfer

The invention relates to a device for data transfer between a memory containing at least one central unit of a data processing system and at least one peripheral unit to specify the memory addresses is capable.

E3 devices for inputting and outputting data - hereinafter referred to as EA works for short - are already known, via which the exchange of information between the main memory or the central processor of the central unit on the one hand and the peripheral units on the other hand is carried out (see Anke, Kaltenecker , Oetker "Prozessrechner", R. Oldenbourg-Verlag Munich-Vienna 1970, in particular pages 77 to S3). Although the I / O plant is usually assigned to the central unit, in the following it is to be regarded as a facility between the central unit or its working memory and the peripheral units. EA operations are generally carried out in a program-controlled manner via so-called standard channels or also via high-speed channels, which differ from the standard channels essentially only in the greater width of the transmission channels. An EA transfer from the control server of the central unit to the EA plant

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Command sequence causes the input or output of either a single piece of information or a block of information. In the case of a block transfer, for example, a first I / O command contains information about the Type of operation to be performed (input or output) and the address of the peripheral unit to be called. A second I / O command contains the start address of a work memory area that can be used for the relevant operation. With a third IO command finally the block length or occasionally the end address of the working memory area in question is specified. For this purpose, the EA plant has its own control, a command register and other things, a so-called byte counter and a register for the current (main memory) address, which, starting from the start address, depends on the position of the byte counter is increased or decreased by 1 until the byte counter or the end address is at zero is reached.

The EA plant sometimes still contains input / output buffer memories, to compensate for different • clock phases, different input-output speeds and / or different widths of the transmission channels are used. Often, however, the buffers are assigned to the peripheral units.

Pur the connection of peripheral units where very fast access to the main memory is necessary is, of additional processors with special functions, but also for the coupling of data processing systems the use of EA works of the type described is not particularly expedient. It is already known

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EA plants are to be trained in such a way that the relevant EA interfaces are punctured by "direct working memory interfaces" exhibit. The main memory addresses are within certain processed memory areas not provided by "commands from the central unit, but by the peripheral units themselves, who of course have to be specially trained. Such direct memory interfaces can then not be used for other peripheral units and are therefore often idle.

The invention is now based on the object of a parameterizable using IO commands. EA plant with central To train address provision so that each standard channel has the function of a direct memory interface can take over. According to the invention, this object is achieved in a device for the data transfer between at least one. Central unit containing working memory and at least one peripheral unit that is able to specify memory addresses with a Register for the current working memory address, a channel command register, a control device and input / output buffers (EA-Werk) solved in that means are provided which, when a corresponding Channel command the takeover of a from the peripheral unit together with a first data request signal cause output memory address and their intermediate storage and due to this first or a second data request signal output by the peripheral unit, the data transfer between the addressed working memory cell and the peripheral unit.

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In the following, exemplary embodiments of the invention are explained in more detail with reference to the drawing. The Pig. 1 shows a central unit ZE, which is indicated by the main memory ASP and the control or program unit StV /. The arithmetic unit belonging to the central unit ZE and the auxiliary devices assigned to the main memory such as address registers, control devices, read / write registers and the main memory coordinator, which is important for regulating memory access, are in the Figure not shown because they have no direct significance for the invention.

The one highlighted by a dashed border EA-Werk EAW contains its own control device EASt, a command register BFR, a register for the current memory address ADRR, one. Byte counter BZ and a 1-bit register R. As usually the I / O plant has many connection points that are largely or entirely occupied by peripheral units and therefore several data requests can arrive at the same time, the EA plant has an in. The figure Priority network, not shown, which distributes the available working memory cycles to the individual connection points (channels) according to their ranking. Not immediately taken into account Data requests are temporarily stored in a register (also not shown) (queue).

So if a data request is received from a peripheral unit and has been made by the operating system (organization program) a corresponding channel command or a command group is provided by the controller of the I / O plant the channel command or the command group is activated and the data transfer runs in the

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gangs "manner described from. G _e Mäss of the invention a further channel command is defined which of the associated connection point which punctures a" are direct memory interface ". As has already been mentioned, is carried out here to indicate the memory addresses by the connected peripheral unit, unlike for operation via standard interfaces in which the addresses are determined by program commands.

The following are based on the Pig. 2, 3a and 3b

Described options for the functional sequence. For this purpose it is initially arbitrarily presupposed that the Interface has one signal bundle each for input and output. Just entering addresses and Only one signal bundle is available for data. Otherwise, the interface should be based on what is known per se Work receipt principle. This is indicated in FIGS. 2, 3a and 3b with the aid of the arrows which show should that between the beginning and the end of the exchanged between the peripheral and the central unit Signals, in particular the data request signal PA of the peripheral unit and the acknowledgment signal QP is directly dependent on the central unit. The time interval between the interdependent Changes in status are to a lesser extent due to device-internal Signal transit times, but essentially determined by the signal transit times on the connecting lines. The same time interval must at least elapse before a new one after the termination of an acknowledgment signal Data request is triggered.

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after one in both the peripheral unit and the procedure specified in the EA plant each time in both Directions. By a 1st data request PA the peripheral unit is the associated one, in a register of the I / O plant or in an agreed memory location The stored channel command is activated and the main memory address entered with the 1st data request PA ADR stored by EA-Y / Erk, preferably in the register for the current working memory address. as The 1-bit register is used to identify the deposit R set to "1". (There can also be a special Position in the operation part of the command register BPR). The content of the addressed memory cell is output to the peripheral unit together with an acknowledgment signal QP. The stored address remains unchanged, which means that the otherwise with the block-by-block data output after each individual transfer change of address (increase or decrease by 1) is now suppressed.

With the subsequent 2nd data request PA, which is sent by the peripheral unit is released in any case on the basis of the determination made, the sends peripheral unit a date DE. The EA-Werk recognizes the information received as a date because the identification bit is still set in the 1-bit register R, the receipt of the data DE acknowledges and writes it into the memory cell addressed with the previous data request. Sends the peripheral device the same date DE returned as it was in the immediately preceding edition DA has received, the affected memory cell remains unchanged when the date is written. In which

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expired cycle it concerns the total effect after a data output. However, if the date DE entered with the 2nd data request PA coincides not with the previously output data DA, the content of the addressed memory cell will be with the new data DE Overwritten, d. H. changes. In this case, it is all about data entry. To At the end of the cycle, the identification bit in the 1-bit register R is reset to "0", which results in has that the previously stored memory address loses its meaning and that with the next data request The working memory address offered by the peripheral unit is recognized as such by the EA-7 / Erk and accepted can be.

The data output lines that are free during the second data request in the operating mode described can be issued by the EA plant with an agreed sample, which can be received by the peripheral unit is checked.

In the operating mode described, its chronological sequence in Pig. 2, a signal determining the transfer direction is not required, v / eil the respective direction of transfer of the individual data is determined in advance. This reduces the effort the interface. The disadvantage of the operating mode described is the time required in terms of the time required in the "data output" cycle, inevitably following the data output DA in the narrower sense, which are in themselves superfluous Re-entry of the date just issued before. However, sending the date back can be used for checking purposes will.

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In the case of a second operating mode, the higher expenditure of time can be partially avoided in that at the same time with the! data request PA of the peripheral unit and a signal TR (direction signal) is transmitted with the main memory address, which determines the transfer direction. If the direction signal TR denotes a data output, the I / O plant responds with an acknowledgment signal QP, which is based on the content of the addressed memory cell is accompanied '. After receiving the output data DA, the peripheral unit terminates its data request PA, which in turn results in the termination of the acknowledgment signal QP. After the peripheral unit has found the end of the acknowledgment signal, it can make a new data request. The temporal The sequence of the output process is shown in FIG. 3 &.

If the direction signal TR accompanying the new data request PA requests data input (FIG. 3), then run initially largely the same signal sequences as for the data output. A very important difference is, however, that the content of the addressed memory cell is now not output. Much more the main memory address ADR sent from the central unit is initially only cached in the EA plant, for example again in the register ADRR for the current working memory address. A second request for data of the peripheral unit is then accompanied by the date to be entered. Again that answers EA-Werk with an acknowledgment signal and stores the incoming date under the previously entered address in the main memory as soon as a main memory cycle is available.

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One sees, in particular, by comparing that in the Pig. 2, 3a and 3b shown signal sequences that the Data output in the second operating mode only takes half the time as in the first operating mode, whereas there is no difference in data entry in this respect. But you can also see that the first operating mode (Pig. 2) requires two main memory accesses for each data transfer, while the second operating mode with one access each.

A shortening of the time required for data entry after the second mode of operation would also be due to the Provision of separate trunk groups for entering the memory address and the date possible, which of course would increase the effort considerably. It should also be noted that the additional trunk group for entering addresses when using the interface as the standard interface.

Another way of organizing data input and output is as follows. As in the second mode of operation is that for data output with the data request and the direction signal TR "Output" offered working memory address initially from the EASt control of the I / O plant into the ADRR register for the current working memory address and then the content of the addressed working memory cell is output. The stored address however remains. If another output with a changed address is to take place afterwards, so the effect of the identification bit is determined by the with The direction signal supplied with the new data request is canceled.

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An entry now presupposes that immediately beforehand an output was requested from the same peripheral unit for which the working memory address was deposited. The information offered with the data request and the direction signal "input" is recognized by the EA-V / Erk as input date and written into the working memory cell, the address of which is still in the Register ADR ^ for the current working memory address stands. The address is also not changed during this process. It is therefore the peripheral unit after a previous output it is possible to enter the same memory cell as often as required. If another working memory cell is to be written to, the peripheral unit must be used beforehand an output from the cell concerned can be requested in order to transfer the relevant working memory address to the EA plant.

It is possible that the line bundle available for data input via the standard interface optimized for centrally controlled block transfer is too tight for the transmission of a complete working memory address. Since it is often sufficient if a certain peripheral unit has direct access to only part of the main memory, it only needs ^{to transmit partial addresses to the EA-T} , which determine individual cells within the assigned memory area. The remaining part of the total working memory address can be contained in the channel command as a prefix or base address.

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Another way to bypass the specified difficulty, which is especially important then, if the availability of the main memory for the peripheral unit should not be restricted, exists therein, several, z. B. two or three To carry out transfers. Accordingly, instead of a single identification bit, several or instead of the 1-bit register, a register for several bits or a counting register can be provided.

love the great flexibility that results from it, that for the centrally controlled. Block transfer optimized standard channels also optionally the Being able to take over punctures of a direct memory access is the particular advantage of the applied principle because of the participation of the central control on the main memory access in the Possibility of being able to use the memory protection devices that are usually present here anyway.

3 figures

11 claims

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Claims (11)

-12 claims Facility for data transfer between at least one a central unit containing a main memory and at least one peripheral unit, the Is able to specify working memory addresses with a register for the current working memory address, a channel command register, a control device and input / output buffers (I / O plant), characterized in that means are provided which, when a corresponding Channel command the takeover of a from the peripheral unit together with a first data request signal cause output memory address and their intermediate storage and based on this first or a second data request signal output by the peripheral unit s the data transfer between the addressed working memory cell and the peripheral unit. 2. Device according to claim 1, characterized in that when a working memory address is taken over, an identifier bit in the operation part of the channel command register or in a special register and is only deleted when the relevant memory address is no longer valid. 3. Device according to claim 1 or 2, characterized ge denote that the direction of data transfer from one of the peripheral unit at the same time with the first data request signal VPA 9/210/1035 -13- 309883 / 081S given directional signal depends. 4. Device according to claim 3, characterized in that that when data is entered in the main memory of the central unit peripheral unit simultaneously with the transmission of the second data request signal, the corresponding Data. 5. Device according to claim 4, characterized in that that one through the peripheral unit with data request and direction signal triggered data entry into a memory cell with an unchanged address as often as desired to one with the Input of the relevant address associated data output takes place. 6. Device according to claim 1 or 2, characterized gekennzei without t that the data transfer between the main memory of the central unit and the peripheral unit in the following steps expires: a) Output of the working memory address with the first data request signal by the peripheral unit, b) reading the addressed working memory cell and transferring its content to the peripheral unit, c) Providing a date with the second data request signal by the peripheral unit and entering this date in the previously addressed working memory cell, its address for this purpose was cached. VPA 9/210/1039 - '-14- 309883/0816 -H- 7. Device according to claim 1 or 2 with separate Line bundles for address entry, data entry and Data output, characterized in that the data transfer is independent of its through the Direction signal specific direction is handled during the first data request. 8. Device according to one of the preceding claims, characterized in that t the intermediate storage of the working memory address output by the peripheral unit in the register for the current memory address. 9. Device according to one of the preceding claims, characterized in that the Data to be transferred to adapt the clock phase and / or different input / output speeds be cached in input / output buffers. 10. Device according to one of the preceding claims, characterized in that the Data to be transferred to compensate for different widths of the data or address transmission paths cached in input / output buffers and that for entering a complete working memory address or for inputting or outputting a Several data requests of the same type are made on the full date. VPA 9/210/1039 ■ -15- 309883/0816 ORiGMNAL JNSPECTED 11. Device according to one of claims 1 to 8, d a through characterized in that the peripheral unit only has partial addresses for selection of working memory cells within memory areas available and that the remaining, the memory areas determining part of the main memory address as prefix or base address iia Channel command is included. VPA 9/210/1039 303883/031? ORIGINAL INSPECTED