DE1563626C3 - Control arrangement with frequency and time proportional signals using combined target and actual value conversion - Google Patents

Description

The invention relates to a multiple control arrangement with frequency and time proportional signals, in which the actual values by frequency analog Signals are shown and the nominal values are set and / or entered numerically, and in which only one counter and means are provided for processing actual and target values per control loop proportional to its control and to the signed-weighted formation of the control deviations Time intervals, in particular multiple control arrangements for ratio control.

Such an arrangement is in the book by C. Keßler, "Digitale Signalverarbeitung in der Regelstechnik", VDE book series, Volume 8, 1962, pp. 238 and 239.

Such control arrangements have the disadvantage that the size of the; Control deviations are included in the sampling period, which is the case with multi-channel arrangements (Ratio control) must lead to a discontinuous detection of the measuring frequency. The one with it Occurring loss of information does not allow an error-free integral formation. In addition, switching means must be provided to the time base supplying the measuring time depending on the maximum required in each case Trigger sampling time.

In the earlier patent 12 97,366 is therefore the task made to eliminate these disadvantages inherent in the known arrangements.

The solution in the earlier patent is that the counter is a presettable counter and that the Means for controlling the counter and for the formation of a sign-weighted formation of the system deviations proportional The following time intervals are:

a) a preselection device controlled by the output of the counter for setting the setpoint,

b) one alternately from this and from one the time base signal with that through an inverter stage inverted output signal of the preselection device linking AND gate controlled, first bistable multivibrator,

c) two of the two outputs of this bistable multivibrator and the output of the preselection

3 4

Direction-controlled and the two preparation pulse numbers are linked, which in turn create one

control inputs of a second bistable trigger stage second input of the summation stage, and

controlling AND gate, further that the output signals of the last

d) two more of the output of the first bistable flip-flop that is mentioned when counting up unmarked output of the first bistable 5 and the output of the zero recognition gate flip-flop and fed from the output of said controlled AND gate to a control input of the inverter stage in common and each from one of the summation stages, via one of the Presetting stage serving both outputs of the second bistable toggle storage of the setpoint controlled AND gate, direction of setting the difference counter on the target

e) two trigger the outputs of the last-mentioned AND value and block the counter inputs via a blocking input of the anti-gate with one of a third bistable coincidence stage, and that Trigger stage supplied signal linking, in a further AND gate with the output reverse direction directly, in the forward direction, signals from the control input that is not marked in the idle state via a summation stage with the measurement signal output of the second bistable multivibrator additively linked, one of the counter 15 th AND gate are linked, its output upstream anticoincidence stage controlling connected to an input of the summation stage AND gate, and that the output signals of the

f) another output of the first bistable marked time base and output of the previous state AND gate linking the selection device, flip-flop and controlled by the zero detection gate

g) one of this AND gate and the output 20 th AND gate one of the blocking of the reverse des already described, the blocking input of the counter that is used for the forward input count unmarked output of the first bi-anti-coincidence level are fed and via a stable multivibrator and the output of the further AND gate with the output signals of the AND gate linking the selection device - summation stage linked via an OR gate controlled and the zero setting input of the counter 25 to the forward input of the anticoincidence stage OR gate, '"are offered.

h) a connection of the counter output »ZERO«. The invention is illustrated with the aid of the drawing.

with one of the preparatory inputs of the two-letter. In it shows.

th bistable multivibrator. F i g. 1 shows the circuit diagram of an exemplary embodiment

30 of the control arrangement according to the invention and

In contrast to the present invention, FIG. 2 shows the principal time course of the

Task is based on another solution of the older counter reading in the steady state for the

Patent 12 97366 set task to find the , _{at too} ki _one

the additional advantage of less effort _b ^. _{to ßem} «j

guaranteed with increased reliability. 35

According to the invention, this object is thereby achieved. 1 shown embodiment for a

solves that the counter is a presettable differential control arrangement according to the invention for syn-

counter is and that the means of control and pre-chronic technology are indicated. The one with the clock pulse

Character-weighted formation of the non-synchronized impulses of the measuring frequency (actual value)

Proportional time intervals and pulse numbers 40 /, · are offered to the input E _fi. You arrive

are provided so that the synchronized Im-. in the drawn rest position of the bistable

pulse of a time flip-flops F ₇ -, FFq and FFj ₁ , which determines the sampling period, via the AND gate

basis directly a preparation input of a first G _Ri and the summation stage S for backward input

bistable flip-flop are fed, the second gear E _AR of the difference counter Z upstream

Preparation input with the output of the zero anticoincidence level A. The counter counts down

recognitionatters of the difference counter is connected, from the preset setpoint to zero. Is the measuring

and their outputs over two common from the frenquency /, - less than their setpoint / _s , then the has

output of the zero detection gate controlled AND counter reading of the difference counter Z upon arrival

Gates the preparation inputs of a second, two-way synchronized one supplied by the time base T

control a stable multivibrator whose outputs have not yet reached zero via a 5 ° sampling pulse

two more AND gates the pulses of the actual frequency are sufficient. The clock pulse coincident with the sampling pulse

between an input of the forward pulse input stage FF switches to _T 'so that from the difference counter ofa upstream Antikoinzi-' gang C ₇ - the bistable multivibrator FF _P triggered and

denzstufe driving OR gate and an AND gate prepared via the inverter stage N '

Input one of the reverse input of the anticoagulant 55 G _{AT is switched} through; ■ Switch over the summation stage controlling the denz stage through the AND gate !; G _AP now receive pulses' of the frequency f ₀ = f _{P! 2}

and further that the in the idle state is not mar- to the output A _P and in the summation stage S. The

output of the first bistable multivibrator a differential counter continues to count with a frequency dec.

third, the half clock pulse frequency delivering bistable speaking of the sum .fp ^ - 'jr fc The achievement of the

Flip-flop triggers, and one of the inverters 60 counter reading zero is detected in gate G _{0 and}

stage inverted 'output signals of the Nüllerk- causes via the inverter stage N the blocking of the gate

prepared AND gate through _{switch G A} j and G _AP , the switching back of the flip-flop

tet, at the output of which the amount of the control FF ₇ in the starting position as well as via the AND gate

Softness proportional time intervals are available to the G _TR and the Voreiristelleineinrichtung SE the setting

are in a further AND gate with the 65 of the counter to the setpoint of the irr SE set

from the third bistable multivibrator supplied Im- counter reading Z _s by the clock pulse. If the

pulses of half the clock pulse frequency to obtain the counter reading O together with the time

the amount of control deviation proportional to the actual frequency / _; evoked exit

5 6

input pulse of the summation stage S, then this must be carried out and the output signals of the gate K _K j buffered in pulse and buffered after the summation stage S ,
setting the difference counter in reverse direction The respective amounts of the control deviations are counted. The intermediate storage takes place in the steady state at proportional time intervals in the summation stage S, which receives the output signals of the gate G _TR via a control 5 at the output A _{T of} the gate G _AT , pulse input. pay at the exit G _{AP available} . In addition, after presetting the difference counter Zw, as shown in FIG. 2, which counts the pulses of the actual frequency /, · only in the sampling time, the counter reading Z _{0 of} the differential downward direction, until the next counter Z in the steady-state approximation sampling pulse repeats the process described. io is proportional to the amount of the control deviation: The counter reading of the difference counter Z has at kon- Z _a = (f _iT - Z ₅ ) (1 ± /, / Z ₀ ). This approximation applies all the more constant control deviation in the steady-state supply, the larger J _{0 is} selected. The sign status in FIG. The basic time evaluation of the output signals shown in 2 a is based on the borrowed curve. Switching state of flip-flop FF ₀ . The following mean: Next, the case is considered where the actual 15 L potential at the flip-flop _{output C 0} , the controlled variable J _{1 is} greater than its setpoint / _s . The bistable deviation is positive: L-potential at the flip-flops off flip-flops should initially be in the drawn gear C ₀ , the control deviation is negative.
Rest position, the counter reading of the difference counter Z In those cases in which the time base Γ is at the preset value Z _s . By means of the delivered sampling pulse simultaneously with or, although the counting of the pulses of the actual frequency /, · via E _n , 20 after reaching the counter reading zero by G _R i, S and A , the counter reading is now zero before the one pulse of the actual frequency / _; , but reached before the arrival of a sampling pulse. When a further actual pulse arrives, gates G ₀ and G ₇ - _v switching of the toggle no output signal is given. Equal stage FF ₀ are prepared by the clock pulse. Then the flip-flops FF ₀ and the gate G _{Ri are} blocked and the gate GV ₁ through 35 FF ₇ , prepared via the gates G ₀ and G _TV or switched, so that the pulses of the actual frequency /, · for from the sampling pulse, from the clock pulse from the rest position forward input E _{AV of} the anticoincidence stage A switched. Since the count of the difference counter Z is long. The difference counter Z counts in the forward direction, remains unchanged, then continues from the direction at the same time. The arrival of a sampling pulse supplied by the time base T clock pulse, the flip-flops FF ₀ and FF _T , prepared causes the stage FF _T 30 via the gates G ₀ and G _TR or G ₀ alone, to which the clock pulse is switched, and thereby the initial position is switched back and the differential flip-flop FFp is triggered and the AND gate G _AT prepared by the inverter counter Z, prepared via the gates G ₀ , G _TR and stage N , is switched through the presetting device SE, to the setpoint Z _s . Then the FF _{9 is} preset. _{The pulse of} the frequency J ₀ - f Ph2 via the output C ₇ - occurring in the meantime at the flip-flop stage does not lead to gate G _AP to output A _P and through the sum output signals at the outputs A _T and A _P , as tion stage S and the anticoincidence stage A for the same time the gate G _AT via the inverter stage N reverse input E _{R of} the difference counter Z. Which is blocked. r. ■
Difference counter Z counts because J _{0 is} greater than / _; , in reverse Is in the .. pre-setting device SE of the reverse direction corresponding to the frequency / ₀ - /, ·. The 40 O value specified, then there is a new off again the counter reaches zero in the genus gear position of the bistable multivibrators, the detected from the Terg _0th It blocks the difference between the inverter stage N and the fact that the gate G _AT and G _AP and causes the _{reset gear C 0 of} the flip-flop FF ₀ in the starting position marten the flip-flop FF _T and, via the gate G _TR , which is sated . As a result, the pulses of the actual flip-flop FF _{0 get} into the starting position and via the 45 frequency /, which then always have a positive control gate G _TR and the presetting device SE means the deviation, via the gate G _Vi to the pre Setting the counter Z to the setpoint value of the counter upward input E _AV der. the 'difference counter Z headed Z ₃ by the clock pulse .. Then'! switched anticoincidence stage A. Switching again the pulses of the actual frequency /; alone in .back-. the flip-flops happens after the arrival of the counting upwards, and when the counter 5 ° time base T is reached, the process described starts from the case of positive control deviation, as described above for level zero,
front. With a constant control deviation - the Da has the time with the. to the; Reaching the counter reading again in the steady state. The pulses F i g which coincide with the counter reading zero. 2 b illustrated principal time course. the. Actual frequency /, · after '·. If the counter reading is zero again, 55 forward direction 'must be counted in, are timed with a pulse of the actual frequency /; together the output signals "of the gate G _TV , which only appear at the men, then this pulse must not go directly to the setpoint setting zero, immediately after the. advertising is incremented by the stored and after presetting the differential reverse channel of the anti-coincidence stage (e _ASR) to Renz counter Z in, reverse direction 60 block and the -. output signals of the _ Summationsden this purpose, with the aND gate G ^ ₁ stage, the co- S via the gates G ^ ₂ and G _{v to} the forward incidences between the output signals of the gate. Input E _{AV of} the anticoincidence stage A. terGy- ^ and Gy j recognized. The output signals of the The same happens with the pulses of the actual gate G _TR are used to block the counter inputs frequency /, ·, which reach the summation of the blocking input E _A $ of the anticoincidence stage A via the gate G _Ri .

For this purpose 2 sheets of drawings

Claims (2)

Patent claims: 1. Multiple control arrangement with frequency and time proportional signals, in which the actual values are represented by frequency-analog signals and the nominal values are set and / or entered numerically, and in which only one counter and means are provided for processing actual and nominal values per control loop its control and the signed-weighted formation of time intervals proportional to the control deviations, in particular a multiple control arrangement for ratio control, characterized in that the means for control and the signed-weighted formation of time intervals proportional to the control deviations are provided in such a way that the synchronized pulses of a time base determining the sampling time (T) are fed directly to a preparation input of a first bistable multivibrator (FF ₇ -), the second preparation input of which is connected to the output of the zero detection gate (G ₀ ) of the difference counter (Z), and its outputs (C ₇ -, C ₇ ) controlled via two controlled jointly by the output of the zero detection gate (G ₀₎ AND gates (G _TR, G _TV) preparing inputs of a second bistable flip-flop (FF _0), the outputs (C _0, C ₀₎ further has two AND gates ( G _Ri , G _{v /} ) the pulses of the actual frequency between an OR gate (G _v ) controlling the forward input (E _AV ) of an anticoincidence stage upstream of the difference counter (Z) and an input of a reverse input (E _AR ) of the anticoincidence stage ( A) toggle controlling summation stage (S) , and further that the output (C ₇ -) of the first bistable multivibrator (FF _T ) , which is not marked in the idle state, triggers a third bistable multivibrator (FFp) delivering half the clock pulse frequency, and one of the In an inverter stage (N) inverted output signals of the zero detection gate (G ₀ ) prepared AND gate (G _AT ) switches through, at the output (A _T ) of the amount of control deviation proportional time intervals are available which are linked in a further AND gate (G _AP ) with the pulses of half the clock pulse frequency supplied by the third bistable multivibrator (FF _P ) to obtain the amount of the control deviation of proportional pulse numbers, which in turn have a second input of the summation stage (S) control, and further that the output signals of the last-mentioned output (C ₇ -) of the first bistable multivibrator and the output of the zero detection gate (G ₀ ) controlled AND gate (G _TR ) are fed to a control input of the summation stage (S), via a The presetting device (SE) serving to store the setpoint value triggers the setting of the differential counter (Z) to the setpoint value and, via a blocking input (E _AS ) of the anticoincidence stage (A), blocks the counter inputs (E _v , E _R ) , and that they are in one further AND gate (G ^ ₁ ) with the output signals of the output C _0, which is not marked in the idle state, of the second bistable multivibrator (FF ₀ ) controlled AND -Gate (G _v> ), the output of which is connected to an input of the summation stage (S) , and that the output _{signals of the output (C 7} -) of the first bistable multivibrator (FF _T ) and of the zero detection gate ( G ₀ ) controlled AND gate (G _TV ) are fed to a blocking input (E _ASR ) of the anti-coincidence stage (Λ) which is used to block the reverse input (E _R ) of the counter (Z) and via a further AND gate (G ^ ₂ ) linked to the output signals of the summation stage (5) via an OR gate (G _v ) are offered to the forward input (E _AV ) of the anticoincidence stage (A) . 2. Control arrangement according to claim 1, characterized in that the output (C ₇ -) of the first bistable multivibrator (FF _T ) instead of a half the clock _{pulse frequency} f Pl2 delivering third bistable multivibrator (FFp) a fixed or adjustable, with the clock pulse frequency synchronized counting frequency / ₀ generating generator triggers.