DE1563626B2 - Control arrangement with frequency and time proportional signals using combined SoH and actual value conversion - Google Patents

Description

The invention relates to a multiple control arrangement with frequency and time proportional Signals in which the actual values are represented by frequency-analog signals and the target values are represented by numbers can be set and / or entered, and for the processing of actual and target values each Control loop only one counter and means are provided for its control and for signed-weighted formation time intervals proportional to the control deviations, in particular multiple control arrangements for ratio regulation.

Such an arrangement is in the book by C. Keßler, "Digitale Signalverarbeitung in der Regelstechnik", VDE book series, Volume 8, 1962, pp. 233 and 239.

Such control arrangements have the disadvantage that the size of the control deviations is included in the sampling period, which in the case of multi-channel arrangements (ratio control) must lead to a discontinuous detection of the measuring frequency. The loss of information that occurs does not allow an error-free integral formation. In addition, switching means must be provided in order to trigger the time base supplying the measuring time as a function of the maximum sampling time required in each case. ^!

In the earlier patent 12 97 366 is therefore the task made to eliminate these disadvantages inherent in the known arrangements.

The solution in the earlier patent is that the counter is a presettable counter and that the Means for controlling the counter and for the formation of a sign-weighted formation of the system deviations proportional The following time intervals are:

a) a preselection device controlled by the output of the counter for setting the setpoint,

b) one alternately from this and from one the time base signal with that through an inverter stage inverted output signal of the preselection device linking AND gate controlled, first bistable multivibrator,

c) two of the two outputs of this bistable multivibrator and the output of the preselection

3 4

Direction-controlled and the two preparation pulse numbers are linked, which in turn create one

control inputs of a second bistable trigger stage second input of the summation stage, and

controlling AND gate, further that the output signals of the last

d) two more of the output mentioned when counting up - the first bistable multivibrator unmarked output of the first bistable 5 and the output of the zero recognition gate flip-flop and from the output of said controlled AND gate to a control input of the Inverter stage are supplied together and each from one of the summation stage, via one of the Presetting stage serving both outputs of the second bistable toggle storage of the setpoint controlled AND gate, direction of setting the difference counter on the target

e) two trigger the outputs of the last-mentioned AND value and block the counter inputs via a blocking input of the anti-gate with one of a third bistable coincidence stage, and that Trigger stage supplied signal linking, in a further AND gate with the output reverse direction directly, in the forward direction, signals from the control input that is not marked in the idle state via a summation stage with the measurement signal output of the second bistable multivibrator additively linked, one of the counter 15 th AND gate are linked, its output upstream anticoincidence stage controlling connected to an input of the summation stage AND gate, and that the output signals of the

f) another output of the first bistable marked time base and output of the previous state AND gate linking the selection device, flip-flop and controlled by the zero detection gate

g) one of this AND gate and the output 20 th AND gate one of the blocking of the reverse des already described, the blocking input used for the forward input of the counter count unmarked output of the first bi-anti-coincidence level are fed and via a stable multivibrator and the output of the further AND gate with the output signals of the AND gate linking the selection device - summation stage linked via an OR gate controlled and the zero setting input of the counter 25 to the forward input of the anticoincidence stage OR gate, are offered.

h) a connection of the counter output »ZERO«. The invention is illustrated with the aid of the drawing.

with one of the preparatory inputs of the two-letter. In it shows.

th bistable multivibrator. F i g. 1 shows the circuit diagram of an exemplary embodiment

30 of the control arrangement according to the invention and

The present invention is in contrast to FIG. 2 the principal time course of the

Task is based on another solution of the older counter reading in the steady state for the

Patent 12 97366 set task to find the * with too small

the additional advantage of less effort _{b M to ßem} ' _{actual value}

guaranteed with increased reliability. 35

According to the invention, this object is thereby achieved. The embodiment shown in FIG. 1 solves that the counter is a presettable differential control arrangement according to the invention for synchronous counter and that the means for control and pre-chronic technology are specified. The formation of the non-synchronized pulses of the measurement frequency (actual variable), which is symbol-weighted with the clock pulse, in proportional time intervals and pulse numbers 40 / _; are offered to the input E _n. You get so provided that the synchronized Im- in the drawn rest position of the bistable pulse of a sampling period determining 'time flip-flops F ₇ -, FF ₀ and FF _P via the AND gate base directly to a preparation input of a first G _Ri and the Summation stage S are fed to the reverse bi-stable multivibrator, the second gear E _{AR of} which is the preparatory input connected upstream of the difference counter Z to the output of the zero 45 anticoincidence stage / 4. The counter counts backwards, connected to the differential counter, from the preset setpoint to zero. If the measurement and their outputs are less than their nominal value / _s , the output of the zero detection gate controlled AND count of the difference counter Z has the preparation inputs of a second one from the time base when the gate arrives T control the synchronized, stable multivibrator whose outputs exceed 50 sampling pulses and the counter reading is zero. The clock coincident with the scanning pulse between an input of the forward input pulse switches the stage FF _T , so that from the anti-coincidence counter upstream of the differential counter C ₇ - the bistable flip-flop FF _{P is} triggered and the OR gate and ^ inem the prepared via the inverter stage N AND gate input of the backward input of the Aiitikoihzi- 55 G _{AT is switched} through: Switch through the AND gate denzstufe controlling summation stage; G _AP now get pulses of the frequency f ₀ = f _P , ₂ and further that the in the idle state does not mar ^ to the output A _P and in the summation stage 5. The; kierte output of the first bistable multivibrator, a differential counter continues to count at a frequency, the bistable delivering half the clock pulse frequency, speaking the sum f _Pl ^ '+ /, ·. Reaching the flip-flop triggers, and one of the inverters '60 counter reading zero' is detected in / gate G ₀ and inverted output signals from the Nüllerken- causes the gate gate to be blocked via the inverter level N ; prepared AND gate switch-through ^; ter G _A7 - and G ^; ^y the downshift of the flip-flop stage, at the output of which the amount of the rule deviation FF _T in the Aüsgarigslage 'as well as time intervals proportional to the AND device deviation are available ter G _TR and the presetting device SE the setting, which are in a further AND gate with the 65 of the counter to the setpoint value set in SE of the Im counter reading Z ₅ supplied by the third bistable multivibrator by the clock pulse. If the pulsing of half the clock pulse frequency falls to obtain the counter reading O temporally together with the amount of the control deviation proportional to an output caused by the actual frequency J ₁

5 6

input pulse of the summation stage S, then this must be carried out and the output signals of the gate K _{K t} buffered in pulse and buffered after the summation stage S ,
setting the difference counter in reverse direction The respective amounts of the control deviations are counted. The intermediate storage takes place in the steady state at proportional time intervals in the summation stage 5, which for this purpose receives the output signals of the gate G _TR via a control 5 at the output A _{T of} the gate G _AT , pulse input. pay at the exit G _AP available. In addition, after presetting the difference counter Zw, as shown in FIG. 2, which counts the pulses of the actual frequency /, · only in the sampling time, the counter reading Z _{a of} the differential downward direction, until the next counter Z in the steady-state approximation sampling pulse repeats the process described. io is proportional to the amount of the control deviation: The counter reading of the difference counter Z has at kon- Z _a = (f _iT - Z _s ) (1 ± /, / Z ₀ ). This approximation applies all the more to the constant control deviation in the steady-state supply, the larger J _{0 is} selected. The sign status in FIG. The basic time evaluation of the output signals shown in 2 a is based on the borrowed curve. Switching state of flip-flop FF ₀ . The following mean: Next, the case is considered where the actual 15 L potential at _{the multivibrator output C 0} , the controlled variable /, is greater than its setpoint / _s . The bistable deviation is positive: L-potential at the flip-flops off flip-flops should initially be in the drawn gear C ₀ , the control deviation is negative.
Rest position, the count of the difference counter Z In those cases in which the time base T is at the preset value Z _s . With the supplied sampling pulse simultaneously with or, although the counting of the pulses of the actual frequency /, · via E _n , 20 after reaching the counter reading zero by G _Ri , S and A , the counter reading is now zero before the one pulse of the actual frequency / _; , but reached before the arrival of a sampling pulse. When a further actual pulse arrives, gate G ₀ and G _TV , the toggle switch is not output. Equal stage FF ₀ are prepared by the clock pulse. After that, the flip-flops FF ₀ and the gate G _{Ri are} blocked and the gate GV ₁ through- as FF ₇ -, prepared via the gates G ₀ and G _TV or switched, so that the pulses of the actual frequency /, · forward input E _{AV of} the anticoincidence stage A switched from the sampling pulse to the clock pulse from the rest position. Since the count of the difference counter Z is long. The difference counter Z counts in the forward direction, remains unchanged, then continues from the direction at the same time. The arrival of one of the time base T clock pulse, the flip-flops FF ₀ and FF _T, prepared supplied sampling pulse causes the stage FF ₇ - alone, switched 30 through gates G ₀ and G _TR or G ₀ by the clock pulse, and thereby the starting position is switched back and the differential flip-flop FFp triggered and the AND gate G _AT prepared by the inverter counter Z, prepared via the gates G ₀ , G _TR and stage N , switched through the presetting device SE, to the setpoint Z ₅ will. After that, the flip-flop FF _{P is} preset. The impulses of the frequency f ₀ = f _{P / 2 that} have been delivered to the flip-flop stage in the meantime _{via the 35 output C 7} - does not lead to gate G _AP to output v4 _P and through the sum output signals at outputs A _T and A _P , da tion stage 5 and the anticoincidence stage A to the same time the gate G _AT via the inverter stage N reverse input E _{R of} the difference counter Z. Which is blocked.

Difference counter Z counts, since / _{0 is} greater than /, -, in reverse. In the presetting device SE, the reverse direction is set in accordance with the frequency / ₀ . If the value O is specified, then there is a new reaching of the counter reading zero in the gate position of the bistable multivibrator, which is recognized by the ter G ₀ . It blocks the difference between the inverter stage N and the fact that the gate G _AT and G _AP and causes the _{reset gear C 0 of} the flip-flop FF ₀ in the starting position of the flip-flop FF _T and, via the gate G _TR , which is sated. As a result, the pulses of the actual flip-flop FF _{0 get} into the starting position and via the 45 frequency /, which then always mean a positive control gate G _TR and the presetting device SF- the deviation, via the gate G _vi to the pre Setting the counter Z to the setpoint value of the counter upward input E _{AV of} the dem; Difference counter Z head Z ₅ by the clock pulse. Thereafter . are switched anticoincidence stage A. Switching again the pulses of the actual frequency /, · only in reverse; the multivibrator takes place after the arrival of the counted from the upward direction, and when the counter time base Γ is reached, the sampling pulses supplied _: as above for level zero, the process described begins, in the case of positive control deviation,
front. With constant control deviation _; However, the Da has the time, with the re-attainment of the counter reading in the steady state, the pulses Fig. 2b which coincide with the counter reading zero. the actual frequency /, -: after the temporary storage in falls, the counter reading zero 55 must be counted in the forward direction, the output signals of the gate G _TV , which are only allowed in the men, _{must be timed together with a pulse of the actual frequency / r} this pulse, do not reach the target value setting zero immediately after the pre-difference meter Z, but must intermediate of the counter setting appear Z, used to change the stored and after the pre-setting, the differential reverse channel of the anti-coincidence stage (e _ASR) to Renz counter Z in, reverse direction and the output signals of the. Summatibnsden. For this purpose, with the AND gate G ^ _1, the cost stages via the GaUCrG ^ ₂ and G _{v are} the forward incidences between the output signals of the gate. to supply input E _{AV of} the anticoincidence level Ä , recognized by _{G 7} Vj and G _Vl. The output signals of the The same happens with the impulses of the actual gate G _TR to block the counter inputs frequency /, ·, which reach the summation of the blocking input E _{AS of} the anticoincidence stage A via the gate G _Ri .

For this purpose 2 sheets of drawings

Claims (2)

Patent claims: 1. Multiple control arrangement with frequency and time proportional signals, in which the actual values are represented by frequency-analog signals and the nominal values are set and / or entered numerically, and in which only one counter and means are provided for processing actual and nominal values per control loop its control and the signed-weighted formation of time intervals proportional to the control deviations, in particular multiple control arrangement for ratio control, characterized in that the means for control and for the signed-weighted formation of time intervals proportional to the control deviations are provided in such a way that the synchronized pulses of a time base determining the sampling time (T) are fed directly to a preparation input of a first bistable multivibrator (FF ₇ -), the second preparation input of which is connected to the output of the zero detection gate (G ₀ ) of the difference counter (Z), and its outputs (C ₇ -, C ₇ - Drive) via two controlled jointly by the output of the zero detection gate (G ₀₎ AND gates (G _TR, G _TV) preparing inputs of a second bistable flip-flop (FF _0), the outputs (C _0, C ₀₎ further has two AND gates (G _Ri , G _v i) the pulses of the actual frequency between an OR gate (G _v ) controlling the forward input (E _AV ) of an anticoincidence stage (A) connected upstream of the difference counter (Z) and an input of a reverse input (E _AR ) of the Anticoincidence stage (A) controlling summation stage (5) switch, and further that the output (C ₇ -) of the first bistable multivibrator (FF _T ) , which is not marked in the idle state, triggers a third bistable multivibrator (FFp) delivering half the clock pulse frequency, and a AND gate (G _AT ) prepared by the output signals of the zero detection gate (G ₀ ), which is inverted in an inverter stage (N), switches through, at whose output (A _T ) time intervals proportional to the amount of control deviation are available ng, which are linked in a further AND gate (G _AP ) with the pulses of half the clock pulse frequency supplied by the third bistable multivibrator (FF _P ) to obtain the amount of the control deviation of pulse numbers proportional to the amount of control deviation, which in turn have a second input of the summation stage (5th ) control, and further that the output _{signals of the last-mentioned output (C 7} -) of the first bistable multivibrator and the output of the zero detection gate (G ₀ ) controlled AND gate (G _TR ) are fed to a control input of the summation stage (S) a presetting device (SE) serving to store the setpoint value triggers the setting of the differential counter (Z) to the setpoint value and, via a lock input (E _AS ) of the anticoincidence stage (A), locks the counter inputs (E _v , E _R ) , and that they in another AND gate (G ^ ₁ ) with the output signals of the output C _0, which is not marked in the idle state, of the second bistable multivibrator (FF ₀ ) AND gate (G _Vi ) are linked, the output of which is connected to an input of the summation stage (5), and that the output signals of the _{output (C 7} ^{-) marked in the idle state of the first · 5} bistable multivibrator (FF _T ) and from Nullerkenidungsgatter (G ₀ ) controlled AND gate (G _TV ) to a blocking input (E _ASR ) of the anti-coincidence stage (A) serving to block the reverse input (E _R ) of the counter (Z) and via a further AND gate (G ^ ₂ ) linked to the output signals of the summation stage (S) via an OR gate (G _v ) are offered to the forward input (E _AV ) of the anticoincidence stage (A) . 2. Control arrangement according to claim 1, characterized in that the output (C ₇ -) of the first bistable flip-flop (FF _T ) instead of a half the clock pulse frequency f _{P / 2} delivering third bistable flip-flop (FFp) with a fixed or adjustable the clock pulse frequency synchronized counting frequency / ₀ generating generator triggers.