DE102012202281A1 - Semiconductor device includes semiconductor chip that includes upper and lower contact plates which are integrally connected to upper chip metallization and lower chip metallization by upper and lower connecting layers - Google Patents

Abstract

The semiconductor device has a semiconductor chip (1) that includes a semiconductor main structure (10) having an upper surface (10t) and lower surface (10b). The upper chip metallization (11) and lower chip metallization (12) are applied to the upper surface and lower surface respectively. A metallic upper contact plate (21) is integrally connected to the upper chip metallization by upper connecting layer (31). A lower contact plate (22) is integrally connected to the lower chip metallization by lower connecting layer (32). Independent claims are included for the following: (1) a pressing contact arrangement of semiconductor chip; and (2) a method for manufacturing semiconductor device.

Description

The present application relates to semiconductor devices in which one or more semiconductor chips are electrically contacted by means of pressure contacts. In conventional "press pack" arrangements, semiconductor chips are respectively inserted between two molybdenum platelets, pressed against each other and thereby electrically contacted, the corresponding contacts being designed only as pressure contacts. If impurities occur during assembly between the chips and the corresponding molybdenum platelets, these impurities will be pressed into the chip metallization of the semiconductor chip due to the pressing force causing contact pressure, where they may, for example, lead to gate-emitter short circuits or other damage. To avoid such damage, thick chip metallizations are used, but this leads to longer processing times in chip production and correspondingly higher costs.

The object of the present invention is to provide a solution to these problems. This object is achieved by a semiconductor device according to claim 1, by a pressure contact arrangement according to claim 11, by a semiconductor chip according to claim 12 and by a method for producing a semiconductor device according to claim 13. Embodiments and developments of the invention are the subject of dependent claims.

One aspect of the present invention relates to a semiconductor device having a semiconductor chip. The semiconductor chip has a semiconductor body with an upper side and a lower side opposite the upper side. On the upper side an upper chip metallization is applied, on the lower side a lower chip metallization. Furthermore, the semiconductor device comprises a metallic upper contact plate and a metallic lower contact plate. An upper connecting layer designed as a solder layer or as a sintered layer is arranged between the upper chip metallization and the upper contact plate and connects them in a materially bonded manner. In addition, a formed as a solder layer or as a sintered layer lower interconnect layer between the lower chip metallization and the lower contact plate is arranged and connects them cohesively with each other.

Since the connection between the contact plates and the semiconductor chip does not have to be made locally, but can take place under clean room conditions, for example, particularly thin chip metallizations can also be used without the risk of damage to the upper or lower chip metallization due to contamination. After the connection between the two contact plates and the semiconductor chip has been established, adequate mechanical protection of the chip metallizations and thus of the semiconductor chip by the contact plates is ensured.

The production of a "press pack" can then be realized, for example, by electrically contacting one or more such semiconductor devices, which are each protected by two contact plates, by means of a pressure contact arrangement, by clamping the semiconductor arrangements between an electrically conductive upper pressure piece and an electrically conductive lower pressure piece, such that an electrically conductive pressure contact is formed between the upper contact plate and the upper pressure piece in each of the semiconductor arrangements, and / or that an electrically conductive pressure contact is formed between the lower contact plate and the lower pressure piece.

The invention will be explained below with reference to the accompanying figures with reference to embodiments. Show it:

1 a cross section through a semiconductor chip;

2 a bottom view of the semiconductor chip according to 1 ;

3 a plan view of a semiconductor chip according to 1 ;

4 a plan view of an alternative embodiment of a semiconductor chip;

5 a vertical section through a semiconductor chip before it is connected to two contact plates;

6 the arrangement according to 5 after connecting the two contact plates to the semiconductor chip;

7 various steps of a method for connecting two contact plates to a semiconductor chip;

8th various steps of a method of simultaneously connecting a plurality of semiconductor chips in a wafer assembly to a bottom contact plate;

9 several steps of a method in which wafer chips produced in the wafer assembly and provided with contact plates are singulated;

10 an intermediate step of a method in which one of several in one Wafer composite interconnected semiconductor chips is provided with a top-side contact plate only if a previously performed on this semiconductor chip function test was successful;

11 a plan view of a semiconductor chip according to 3 which is equipped with an upper contact plate whose base is identical to the base of a top chip metallization;

12 a plan view of a semiconductor chip according to 4 which is equipped with an upper contact plate whose base is identical to the base of a top chip metallization;

13 a plan view of a semiconductor chip according to 3 which is equipped with an upper contact plate which projects laterally beyond a chip metallization of the semiconductor chip and over the semiconductor chip;

14 a plan view of a semiconductor chip according to 4 which is equipped with an upper contact plate which projects laterally beyond a chip metallization of the semiconductor chip and over the semiconductor chip;

15 a plan view of a semiconductor chip according to 3 which is equipped with an upper contact plate, which protrudes laterally neither over the semiconductor chip nor over a metallization of the semiconductor chip;

16 a plan view of a semiconductor chip according to 4 which is equipped with an upper contact plate, which protrudes laterally neither over the semiconductor chip nor over a metallization of the semiconductor chip;

17 a semiconductor chip, which is in each case materially connected to an upper and a lower contact plate, wherein a polymer is applied to an edge structure of the semiconductor chip;

18 a semiconductor chip, which is in each case materially connected to an upper and a lower contact plate, wherein a polymer is applied to an edge structure of the semiconductor chip, which extends to the lateral edge of the upper contact plate;

19 a semiconductor chip, which is in each case materially connected to an upper and a lower contact plate, wherein a polymer is applied to an edge structure of the semiconductor chip, which covers the lateral edge of the semiconductor chip and which extends to the lateral edges of the upper or lower contact plate;

20 an arrangement accordingly 19 in which the polymer was applied by means of a spraying or casting technique on the cohesive composite of the semiconductor chip and the two contact plates;

21 a pressure contact arrangement, in which a plurality of individual, in each case integrally connected to an upper and a lower contact plate semiconductor chips between two pressure pieces and thereby be electrically pressure-contacted by these;

22 a pressure contact arrangement in which a plurality of semiconductor chips connected to one another in the wafer composite are clamped between two pressure pieces and are thus electrically pressure-contacted by the latter, wherein the semiconductor chips are in each case materially connected to a separate upper contact plate, and are in each case materially connected to a lower contact plate common to all the semiconductor chips;

23 a cross section through a semiconductor chip to illustrate the thin upper and lower chip metallization;

24 a plan view of a portion of the semiconductor chip according to 23 ;

25 a view accordingly 5 with the difference that the upper and the lower contact plate are each formed as multilayer plates;

26 the components according to 25 after the cohesive connection of the two contact plates with the semiconductor chip;

27 a view accordingly 5 with the difference that the upper and the lower contact plate each have an aluminum nitride plate, which is covered by an aluminum layer; and

28 the components according to 27 after the cohesive connection of the two contact plates with the semiconductor chip.

In the figures, like reference characters designate like or equivalent parts.

1 shows a sectional view of a semiconductor chip 1 , This comprises a semiconductor body 10 , The semiconductor body 10 based on any semiconductor base material, for example, silicon, silicon carbide, gallium arsenide, germanium, etc. The semiconductor body 10 may comprise any combination of n-doped and p-doped semiconductor regions, dielectric layers, for example, of silicon oxide or silicon nitride, and electrically conductive compounds of metal and / or polycrystalline semiconductor material. The semiconductor body 10 may include any controllable semiconductor device such as a MOSFET, an IGBT, a J-FET or a thyristor, or a diode.

Furthermore, the semiconductor body designed as a flat plate has 10 a top 10t and one of the top 10t opposite bottom 10b on. The top 10t and the bottom 10t form the two largest sides of the semiconductor body in terms of area 10 , On the top 10t is an upper chip metallization 11 Applied to the bottom 10b a lower chip metallization 12 , In the chip metallizations 11 . 12 these are contact metallizations of the semiconductor chip 1 that serve the semiconductor chip 1 to contact the outside electrically. For example, it may be in the chip metallizations 11 and 12 a drain or source terminal, a source or drain terminal, an emitter or collector terminal, a collector or emitter terminal, an anode or cathode terminal or a cathode or anode terminal act.

2 shows a bottom view of the semiconductor chip 1 according to 1 , It can be seen that the lateral edge of the lower chip metallization 12 from the lateral edge of the semiconductor body 10 can be spaced. Alternatively, the bottom chip metallization could 12 but also up to the lateral edge of the semiconductor body 10 extend.

3 shows a plan view of the semiconductor chip 1 according to 1 , In this view it can be seen that a semiconductor chip 1 optionally may have a control terminal, such as a gate or base terminal, by another upper chip metallization 13 is formed. This further chip metallization 13 is also on top 10t applied. Alternatively, the further metallization could 13 a control terminal also on the bottom 10b be upset.

Depending on the type of in the semiconductor chip 1 realized component may be such a control terminal to a gate terminal or a base terminal. In the example according to 3 is the control terminal 13 in the area of a corner of the top 10t , According to another, in 4 shown embodiment, the chip metallization 13 a control terminal also annular from the upper chip metallization 11 be enclosed. This can be the metallization 13 the control terminal in particular in the middle of the bottom 10b are located. However, the position of the metallization 13 a control terminal not on the in the 3 and 4 limited variants shown. If it is in the semiconductor chip 1 realized component is a metal, is a metallization 13 a control connection is not required.

As further below on the basis of 5 and 6 It can be seen, a semiconductor chip 1 as previously explained with an upper contact plate 21 as well as with a lower contact plate 22 in each case cohesively to a semiconductor device 100 be connected, which has an upper contact surface 100t and one of the upper contact surfaces 100t opposite lower contact surface 100b , For this purpose, the upper contact plate 21 with the help of an upper connection layer 31 cohesively with the upper chip metallization 11 connected. Accordingly, the lower contact plate 22 with the help of a lower connection layer 32 cohesively with the lower chip metallization 12 connected. The thicknesses d21 and / or d22 of the upper contact plate 21 or the lower contact plate 22 can - independently of each other - for example, be at least 0.3 mm. Optionally, the thickness d21 and / or d22 of the upper contact plate 21 or the lower contact plate 22 - Also independently of each other - for example, at least 5 mm. The thicknesses d21 and / or d22 of the upper contact plate 21 or the lower contact plate 22 can - again independently, for example, less than 5 mm, for example, be at most 2.5 mm.

Unless the top 10t or the bottom 10b with a metallization 13 a control terminal is provided, the relevant contact plate 21 or 22 , which is on the same side as the metallization 13 , in the field of metallization 13 be left out of the control terminal.

The production of cohesive connections between the metallizations 11 . 12 and the contact plates 21 respectively. 22 can take place under increased purity conditions, eg in a clean room, so that the chip metallizations 11 and 12 not be damaged by contamination and the function of realized in the semiconductor chip device remains guaranteed.

At the connection layers 31 . 32 each may be solder layers or each sintered layers. Likewise it is possible that the upper connecting layer 31 as a solder layer and the lower connection layer 32 are formed as a sintered layer. Conversely, the upper connection layer can also be used 31 be as a sintered layer and the lower connecting layer 32 be formed as a solder layer.

If a connection layer 31 . 32 is formed as a solder layer, this may be in particular a diffusion solder layer. A diffusion solder layer is understood to mean a layer which is formed by material from the contact surfaces being diffused into the liquid solder from one or both of the metallic contact surfaces to be joined by means of a solder during the soldering process and forming one or more intermetallic phases together with the solder. which have a melting point which is higher than the melting point that the solder has before the soldering process.

The formation of intermetallic phases depends in particular on the soldering temperature, the soldering time and the thickness of the solder. To be in a connection layer 31 or 32 a high proportion of intermetallic phases and, consequently, a higher strength of this compound layer 31 respectively. 32 It is advantageous to achieve the bonding layers 31 respectively. 32 as thin as possible, since then the metal from the upper chip metallization 11 and / or the upper contact plate 21 or from the lower metallization layer 12 and / or the lower contact plate 22 diffused into the entire liquid solder or at least a large part thereof. For example, a connection layer 31 and or 32 have a proportion of at least 90 weight percent intermetallic phases.

For example, if the solder used contains tin and if one or both of the metals to be joined together, ie in the preparation of the upper bonding layer 31 the upper chip metallization 11 and / or the upper contact plate 21 , or in the production of the lower connection layer 32 the bottom chip metallization 12 and / or the lower contact plate 22 Containing copper, so can the tie layers 31 respectively. 32 after completion of the soldering process have one or more intermetallic copper-tin phases such as Cu ₆ Sn ₅ or Cu ₃ Sn. Cu ₆ Sn ₅ represents that of the intermetallic copper-tin phases with the lowest melting point (about 415 ° C). This ensures a sufficient strength of the compound even at high chip temperatures and contact pressures, as they occur for example in Presspack cells guaranteed ,

If one or both of the tie layers 31 or 32 are formed as sintered compounds, they can be prepared by means of a low-temperature sintering process (NTV). In the context of the present application, such a low-temperature sintering process is understood to be a process in which a sinterable paste is introduced between the joining partners to be joined together and sintered in a temperature range from 180 ° C. to 300 ° C. while the joining partners are pressed against one another, without a Temperature of 300 ° C to exceed, with these temperature data refer to the temperature of the sinterable paste. The contact pressure during the sintering may be, for example, 2 N / mm ² to 40 N / mm ² . Pastes which contain a mixture of a noble metal powder and a solvent are suitable as the sinterable paste. As a precious metal, for example, silver is suitable.

In order to increase the sinterability of the contact surfaces of the joining partners to be joined together, their surfaces can each optionally be provided with a noble metal layer, for example silver, palladium or gold. Of course, if a contact surface is already formed as a noble metal contact surface, such a noble metal coating can be dispensed with.

To a contact plate 21 respectively. 22 cohesively with an upper chip metallization 11 or with a lower chip metallization 12 to sinter, the sinterable paste is applied to one or both of the contact surfaces of the joint partners to be joined together before pressing the two joining partners together and dried to at least partially remove the solvent contained. After juxtaposing the joining partners, the dried sinterable paste extends continuously between the contact surfaces of the two joining partners to be joined together 11 and 21 respectively. 12 and 22 , Since the dried sinterable paste is no longer present as a paste after drying, the term "sinterable layer" is also used below.

An example of this will be in 7 shown in several steps. In this example, a single semiconductor chip 1 with an upper contact plate 21 as well as with a lower contact plate 22 sintered. For this purpose, in a first step (A1) a sinterable paste 32 ' on the the semiconductor body 10 opposite side of the lower chip metallization 12 applied and dried. Alternatively or additionally, the sinterable paste 32 ' also on the with the semiconductor chip 1 to be joined side of the lower contact plate 22 and dried, which is shown in step (A2).

Regardless of whether the application of the sinterable paste 32 ' According to steps (A1) and / or (A2), the semiconductor chip 1 and the lower contact plate 22 pressed together, leaving the sinterable layer between the lower metallization 12 and the lower contact plate 22 located. Then the sinterable layer 32 ' while maintaining the contact pressure as explained above sintered in a temperature range of 180 ° C to 300 ° C, wherein the temperature of the sinterable layer 32 ' is always kept less than or equal to 300 ° C. For this purpose, the temperature of the sinterable paste 32 ' at least for 1 second in the temperature range of 180 ° C to 300 ° C are tempered. The sintering process forms from the sinterable layer 32 ' a solid tie layer 32 showing the bottom chip metallization 12 with the lower contact plate 22 cohesively connects, resulting in 7 (B) is shown.

In a subsequent step, the upper contact plate 21 during a further sintering step with the aid of a sinterable layer 31 ' with the upper metallization 11 of the semiconductor chip 1 connected. The application and drying of the sinterable paste 31 ' , which can be constructed as well as the sinterable paste 32 ' , can, as in 7 (C1) is shown with the semiconductor chip 1 to be joined side of the upper contact plate 21 take place, and / or on the semiconductor body 10 opposite side of the upper chip metallization 11 , what in 7 (C2) is shown.

After application of the sinterable paste 31 ' become the upper contact plate 21 and the upper chip metallization 11 at intervening sinterable layer 31 ' pressed together and the sinterable layer 31 ' is sintered while maintaining the contact pressure in a temperature range of 180 ° C to 300 ° C, but not above 300 ° C, so that the sinterable layer 31 ' in a solid sintered layer 31 is transformed, which is the upper chip metallization 11 cohesively with the upper contact plate 21 connects what results in 7 (D) is shown.

While in the embodiment according to 7 a single semiconductor chip 1 in each case cohesively with an upper contact plate 21 and a lower contact plate 22 is done in another, based on 8th explained embodiment, the assembly of a plurality of semiconductor chips with a common lower contact plate in the wafer composite. This is a wafer 100 , which is a processed semiconductor body 110 comprising a plurality of individual semiconductor devices and having an upper chip metallization 11 structured upper metallization 111 as well as with a lower metallization 112 is provided at the lower metallization 112 with a contact plate 122 sintered.

As in 8th (A1), becomes a sinterable paste 132 ' on the the semiconductor body 110 opposite side of the lower metallization 112 and / or, as in 8th (A2) is shown on the wafer 100 to be joined side of the lower contact plate 122 , applied and dried. The wafer 100 and the lower contact plate 122 are then with the intervening sinterable layer 132 ' pressed together and sintered in the same way as previously described by 7 when sintering the lower metallization 12 with the lower contact plate 22 was explained. The structure of the sinterable paste or layer 132 ' corresponds to the structure of the sinterable paste or layer 32 ' , After annealing the sinterable layer 32 ' in a temperature range of 180 ° C to 300 ° C, without exceeding the temperature of 300 ° C, the sinterable layer 132 ' in a sintered layer 132 converted, which is the lower contact plate 122 with the lower metallization 112 of the wafer 100 cohesively connects, resulting in 8th (B) is shown.

Subsequently, the singulation of this composite takes place, so that as a result the individual semiconductor chips 1 of the wafer 100 as mutually independent semiconductor chips 1 present, each at their lower metallization 12 with a likewise isolated section 22 the lower contact plate 122 are sintered. The singulation of the wafer 100 and the associated lower contact plate 122 is carried out expediently during the same sawing step.

The construction of the isolated, in 8th (C) and with a lower contact plate 22 provided semiconductor chips 1 corresponds to the structure of in 7 (B) shown arrangement. Accordingly, another assembly of each of the upper chip metallization 11 with an upper contact plate 21 correspond to the basis of the 7 (C1), (C2) and (D) explained methods.

According to another, based on 9 explained method can be located in the wafer assembly semiconductor chips first with a common lower contact plate 122 sintered, as previously described with reference to 8th (A1), (A2) and (B) has been explained. Based on the arrangement according to 8th (B) can then be applied to the top chip metallization 11 each of the semiconductor chips has a separate top contact plate 21 be sintered. In this case, the same sintering method can be used as previously described with reference to 7 (C1), (C2) and (D), with the difference that the sintering takes place when the individual semiconductor chips 1 still in the wafer composite. The upper contact plates 21 can be done sequentially or during a common Niedertemperatursinterschrittes. In a common sintering step, the placement of the individual upper contact plates 21 on the respective upper chip metallization 11 successively or temporally parallel to each other. 9 (A) shows the arrangement after sintering.

Thereafter, the composite, for example by sawing, to individual, each with an upper contact plate 21 and with a lower one contact plate 22 provided semiconductor chips, resulting in 9 (B) is shown.

If subsequently it should turn out that one made in this way and with contact plates 21 . 22 provided semiconductor chip 10 is not functional, this of course means a waste of the material especially for the contact plates 21 . 22 , This can be partially avoided by having the individual chips of the in 8th (B) shown wafers 100 each tested for their electrical function and only then with an upper contact plate 21 equipped and materially connected to this, if the respective semiconductor chip 10 has proved to be functional in a previous test. At a corresponding, in 10 Example shown was in the wafer composite 110 the third semiconductor chip from the left faulty and was therefore not with an upper contact plate 21 Mistake.

In the above-explained sintering process, the lower bonding layer was first used 132 and then the upper tie layers 31 produced by sintering in each case in the temperature range from 180 ° C to less than or equal to 300 ° C. In principle, the order of manufacture can also be reversed.

Likewise, an upper sinterable paste 31 ' and a lower sinterable paste 32 ' respectively. 132 ' be sintered at the same time, by first both the upper sinterable paste 31 ' on the upper contact plate 21 and / or the upper chip metallization 11 is applied, as well as the lower sinterable paste 32 ' or 132 ' on the lower contact plate 22 respectively. 122 and / or the lower chip metallization 12 or wafer metallization 112 is applied. The applied sinterable pastes 31 ' . 32 ' respectively. 132 ' can then in a common drying step to sinterable layers 31 ' . 32 ' respectively. 132 ' be dried.

After the drying step, the lower contact plate (s) may then initially be, for example 22 respectively. 122 using the sinterable layers 32 ' respectively. 132 ' prefixed to each other by pre-sintering. The composite pre-sintered in this manner can then be made using the sinterable layer (s). 31 ' with one or more upper contact plates 21 equipped and permanently sintered for a period of at least 1 second in a temperature range of 180 ° C to 300 ° C. In this annealing step, the pre-sintered connection is finally sintered, ie, the presintered sinterable layers 32 'and 132' are finally sintered for at least 1 second in a temperature range of 180 ° C to 300 ° C. Optionally, prior to final sintering, a pre-sintering step may be performed, through which the one or more upper contact plates 21 prefixed to the pre-sintered composite.

For the purposes of the present invention, presintering means an annealing step in which the respective sinterable paste 31 ' . 32 ' respectively. 132 ' annealed for a period of at least 0.5 seconds at a temperature in the range of about 90 ° C to about 140 ° C and thereby strengthened to the extent that by the respective sinterable layer 31 ' . 32 ' respectively. 132 ' metallizations to be joined together 11 . 12 respectively. 112 and contact plates 21 . 22 respectively. 122 prefixed to each other, so that the prefixed unit can be further processed easily. The contact pressure with which the parts to be joined together are pressed against each other during the annealing step for pre-sintering can be, for example, 0.01 N / mm ² to 0.1 N / mm ² .

The pre-sintering can take place, for example, by using a paste or layer which is not sinterable 31 ' . 32 ' or 132 ' provided contact plate 21 . 22 respectively. 122 preheated and onto which with a sinterable layer 31 ' . 32 ' respectively. 132 ' provided chip metallization 11 . 12 respectively. 112 is pressed, so that the heat of the preheated contact plate 21 . 22 respectively. 122 the presintering effect. Alternatively or additionally, the heat required for pre-sintering can also be supplied by means of a heatable pressing tool which forms the semiconductor chip 1 and the contact plate to be connected by pre-sintering 21 . 22 respectively. 122 pressed together.

Previously, the production of cohesive connections between upper contact plates 21 and upper chip metallizations 11 as well as between lower contact plates 22 and lower chip metallizations 12 based on the production of sintered upper and lower tie layers 31 respectively. 32 explained. The connection layers shown and explained in the figures 31 . 32 However, they could also be formed as solder layers, if in their preparation instead of a sinterable paste 31 ' . 32 ' . 132 ' a lot is used. Such a solder may also be formed as a paste and, as explained with reference to the preceding figures, applied to one or both of the respective contact surfaces to be joined together. As an alternative to a solder formed as a paste, a solder plate can also be inserted between the contact surfaces to be connected to one another and used to solder these contact surfaces together by melting the solder plate and subsequently cooling the liquid solder. Instead of applying a solder as a paste on a contact surface or as a solder plate on a contact surface, it can also be deposited galvanically on the respective contact surface. The following is the application of a solder on a Contact surface described using the example of a solder paste, but the solder can instead also be deposited galvanically on the respective contact surface or placed as a solder plate on this contact surface. Regardless of the type of solder and its order on a contact surface, the solder is - instead of the explained sintering process - melted and then cooled to its solidification, so that a solid, cohesive solder joint between the upper chip metallization 11 and the upper contact plate 21 and / or between the lower chip metallization 12 and the lower contact plate 22 arises, or, if a plurality of semiconductor chips interconnected in a wafer composite 1 with a common lower contact plate 122 be connected between the lower metallization 112 of the wafer composite 110 and one of the connected semiconductor chips 1 common lower contact plate 122 ,

It is also possible, first, a solid, cohesive solder joint between the upper chip metallization 11 and the upper contact plate 21 and between the lower chip or wafer metallization 12 / 112 and the lower contact plate 22 / 122 first by making the top chip metallization 11 provided with a solder and then against the preheated upper contact plate 21 is pressed. Thereafter, the composite formed thereby from the upper contact plate 21 and the upper chip metallization 11 at the lower chip or wafer metallization 12 / 112 with the lower contact plate 22 respectively. 122 be connected by the provided with a solder lower contact plate 22 respectively. 122 is pressed against the preheated composite.

As already mentioned, sintered connections and soldered connections can also be used in combination with one another in the case of a semiconductor component. For this purpose, for example, a diffusive solder in paste form on the lower chip metallization 12 or wafer metallization 112 applied and then together with the semiconductor chip 1 against the preheated lower contact plate 32 respectively. 132 be pressed, so that the solder by the heat of the preheated lower contact plate 32 respectively. 132 melts and a solder joint between the lower chip metallization 12 or wafer metallization 112 and the lower contact plate 32 respectively. 132 arises. After that, the with a sinterable paste 31 ' provided upper contact plate 21 with the sinterable paste 31 ' ahead against the upper chip metallization 11 already with the lower contact plate 32 respectively. 132 connected semiconductor chips 1 pressed and with the upper chip metallization 11 be sintered by the sinterable paste 31 ' is tempered for a period of at least 1 second in a temperature range of 180 ° C to 300 ° C, while the upper contact plate 31 against the semiconductor chip 1 remains pressed. Optionally, this annealing step may be preceded by a presintering step in which the sinterable paste 31 ' when against the upper contact plate 31 pressed semiconductor chip 1 is presintered as explained above.

To achieve the best possible thermal and electrical connection of the semiconductor chip 10 to the upper contact plate 21 and / or to the lower contact plate 22 to reach the contact plate 21 or 22 the chip metallization in question 11 respectively. 12 completely or substantially completely cover, which is exemplified below by way of example 11 to 16 is explained. Shown is in each case a plan view of the semiconductor chip 10 which according to the 3 ( 11 . 13 and 15 ) respectively. 4 ( 12 . 14 and 16 ), wherein the upper chip metallization 11 each with an upper contact plate 21 by means of a bonding layer 31 (concealed) is firmly bonded. In the arrangements according to the 11 and 12 is the base of the upper contact plate 21 identical to the surface of the upper metallization layer 21 , In the arrangements according to the 13 and 14 extends the upper contact plate 21 laterally across the surface of the upper chip metallization 11 and optionally also over the lateral edge of the semiconductor body 10 out. As far as the semiconductor chip 10 and the upper chip metallization 11 in the 13 and 14 through the overlying contact plate 21 are concealed, their course is indicated by dashed lines. By the contact plate 21 the semiconductor body 10 surmounted by its lateral edges, is the semiconductor chip 10 protected against mechanical damage of the chip edges. In the arrangements according to the 15 and 16 is the upper contact plate 21 in the lateral direction in each case from the edge of the upper chip metallization 11 slightly spaced.

A device in a semiconductor chip 1 According to the present invention, optionally may have an edge structure, ie a region in which an electric field is degraded, which at a high, the semiconductor chip 1 applied reverse voltage at the edge of a pn junction. Above such an edge structure can, as in 17 is shown, the semiconductor chip 1 on its top 10t in a peripheral area of the top 10t in which these are above the upper chip metallization 11 extends, with a polymer 15 be provided. In this case, such a polymer 15 also the lateral edge of the contact plate 21 completely or at least partially overlay, which is exemplary in 18 is shown.

In the arrangement according to 19 became the polymer 15 so applied that it is the lateral edge of the arrangement with the semiconductor chip 1 , the Tie layers 31 . 32 and the contact plates 21 . 22 completely covered.

The same applies to the arrangement according to 20 in which case the application of the polymer 15 characterized in that the composite of semiconductor chip 1 , Tie layers 31 . 32 and contact plates 21 . 22 was placed in a mold and potted or overmolded with the polymer at the lateral edge.

If in a semiconductor device according to the invention, in which a semiconductor chip or wafer 1 with two contact plates 21 and 22 respectively. 122 each cohesively connected, a polymer or other passivation 15 is provided, the maximum thickness d15, which allows this passivation 15 perpendicular to the normal directions of the upper contact surface 100t and the lower contact surface 100b should be less than or equal to 1 mm.

Optionally, it may be provided that a semiconductor device according to the present invention has no housing, or that - if a housing is present - this extends beyond any of the planes in which the upper contact surface 100t or the lower contact surface 100b run.

This ensures that the upper contact surface 100t and the lower contact surface 100b represent the most projecting towards their surface normal parts of the semiconductor device. The upper contact surface 100t and the lower contact surface 100b are thereby through the the semiconductor body 1 opposite sides of the upper contact plate 21 or the lower contact plate 22 / 122 given.

One or more semiconductor chips 1 as previously explained with contact plates 21 . 22 were provided can be installed in a pressure contact arrangement. For this purpose, the one or more already by means of material connections 31 . 32 with contact plates 21 . 22 provided semiconductor chips 10 such between an electrically conductive upper pressure piece 51 and an electrically conductive lower pressure piece 52 clamped that between each of the upper contact plates 21 and the upper pressure piece 51 an electrically conductive pressure contact is formed, and / or that between each lower contact plate 22 and the lower pressure piece 52 an electrically conductive pressure contact is formed, as in 21 is shown. This may be an optional dielectric frame 60 be provided, with the lower pressure piece 52 can be connected or loose on this, and for each semiconductor chip 1 has its own recording area. Optionally, a connection structure 55 be provided, which serves, possibly existing control terminals such as gate or base terminals or other terminals of the semiconductor chips 1 , for example for temperature monitoring, to interconnect. In such a connection structure 55 it may be, for example, a circuit board.

Instead of individual semiconductor chips 1 However, a composite with two or more semiconductor chips, which are still in the wafer assembly or in a non-separated portion of a wafer, between an upper pressure piece 51 and a lower pressure piece 52 be clamped in what 22 is shown. For this purpose, for example, one with a lower contact plate 122 and one with an upper contact plate 21 provided wafer composite with two or more semiconductor chips of a not yet isolated portion of a wafer composite can be used, as exemplified in the 9 and 10 is shown.

Due to the cohesive connection of both the upper and the lower chip metallization with an upper contact plate 11 or with a lower contact plate 12 can the upper chip metallization 11 and the bottom chip metallization 12 can be made with a conventional thickness in bonded semiconductors. In contrast, the thickness of the chip metallization must be 11 . 12 in normal press assemblies, because of the possible damage mechanisms, they can be partially increased by a factor of 2 to 3, which requires special processes. For the purposes of the present invention is as upper chip metallization 11 or as the lower chip metallization 12 a planar layer that extends substantially over the entire surface of a terminal contact, in particular a drain, source, emitter, collector, anode or cathode contact, without being interrupted by a dielectric or a semiconductor material. As in 23 is shown schematically, the upper chip metallization 11 with the help of metallic or by polycrystalline semiconductor material filled contact holes 17 to deeper areas of the semiconductor body 10 be electrically connected. These filled contact holes 17 are not considered components of the upper chip metallization 11 considered. The same applies to the lower chip metallization 12 , provided that correspondingly filled contact openings are provided here. Thus, for the determination of the thickness d11 of the upper chip metallization 11 and the thickness d12 of the lower chip metallization 12 calculated only metallizations, which have a larger contiguous base.

Accordingly, for each non-interrupted by a dielectric or by a semiconductor material flat portion applies 61 respectively. 62 the upper chip metallization 11 or the lower chip metallization 12 which has a base area of at least 1 mm ² , that its thickness d61 or d62 may be smaller than 8 microns In this sense, as a planar portion, a section is understood, which is bounded above and below by two mutually parallel planes E1, E2 , as well as laterally by a circumferential wall W, which runs at any point perpendicular to these planes E1 and E2.

24 shows a plan view of the semiconductor chip 1 according to 23 , wherein the lateral boundaries of such sections 61 and 62 are shown in dashed lines. Also marked are areas A61 at the top 10t or A62 at the bottom 10b that from the sections 61 respectively. 62 be covered. The surfaces A61 and A62 thus provide bases of the sections 61 respectively. 62 unlike in 24 represented the bases A61, A62 of the sections 61 respectively. 62 not necessarily be rectangular. Rather, any contiguous, unbroken bases A61, A62 are also possible.

The above-discussed upper contact plates 21 or lower contact plates 22 and 122 can be made of any materials, such as molybdenum. Likewise, these contact plates 21 . 22 . 122 but also be formed by a composite of two or more metal layers, which can be prepared, for example, by the individual layers are rolled together. By way of example, the show 25 and 26 , which otherwise the 5 respectively. 6 correspond, upper contact plates 21 or lower contact plates 22 , each consisting of a sequence of layers with three metal layers 211 . 210 . 212 respectively. 221 . 220 . 222 are formed. The contact layers 211 . 212 . 221 . 222 may for example consist of copper, the metal layers 210 and 220 for example, iron.

According to another example, an upper and / or a lower contact plate 21 . 22 . 122 also consist of AlSiC (aluminum silicon carbide). With this but also other materials, linear thermal expansion coefficients similar to those of semiconductor material can be adjusted. For example, an upper and / or a lower contact plate 21 . 22 . 122 have a linear thermal expansion coefficient of less than or equal to 6 ppm / K or less than or equal to 5 ppm / K. For example, one, several or each of the contact plates 21 . 22 . 122 , independently, have a linear coefficient of thermal expansion in the range of 4.8 ppm / K to 8 ppm / K. As materials for this example, metal matrix composites (MMC) as the aforementioned AlSiC, but also other MMC materials can be used.

According to yet another, in 27 shown example, an upper and / or a lower contact plates 21 . 22 (as well as 122 according to the 8th to 10 ) one platelet each 215 respectively. 225 of aluminum nitride (AlN), which, for example in a casting process, partially or completely with an aluminum coating 216 respectively. 226 was wrapped. 28 shows the arrangement after the material connection of the contact plates 21 . 22 with the semiconductor chip 1 ,

Claims (17)

A semiconductor device comprising: a semiconductor chip ( 1 ) with a semiconductor body ( 10 ), which has a top ( 10t ) and one of the top ( 10t ) opposite bottom ( 10b ) having; - one on top ( 10t ) applied top chip metallization ( 11 ); - one on the bottom ( 10b ) applied lower chip metallization ( 12 ); a metallic upper contact plate ( 21 ); a metallic lower contact plate ( 22 ); a top connecting layer formed as a solder layer or as a sintered layer (US Pat. 31 ) between the upper chip metallization ( 11 ) and the upper contact plate ( 21 ) is arranged and connects them cohesively; and a lower connecting layer formed as a solder layer or as a sintered layer (US Pat. 32 ) between the lower chip metallization ( 12 ) and the lower contact plate ( 22 ) is arranged and connects them cohesively. Semiconductor arrangement according to Claim 1, in which the metallic upper contact plate ( 21 ) and the metallic lower contact plate ( 22 ) each have a thickness (d21, d22) of at most 2.5 mm; and / or the metallic upper contact plate ( 21 ) and the metallic lower contact plate ( 22 ) each have a thickness (d21, d22) of at least 5 mm have. A semiconductor device according to claim 1 or 2, wherein the upper chip metallization ( 11 ) a flat, unbroken section ( 61 ) having at least 1 mm ^{2 of} the upper side ( 10t ) covered; and / or the lower chip metallization ( 12 ) a flat, unbroken section ( 62 ), the at least 1 mm ^{2 of} the underside ( 10b ) covered. A semiconductor device according to any one of the preceding claims, wherein the thickness (d61) of any plane and continuous section ( 61 ) of the upper chip metallization ( 11 ) having a footprint of at least 1 mm ² , is at most 8 μm; and or where the thickness (d62) of any plane and continuous section ( 62 ) of the lower chip metallization ( 12 ), which has a footprint of at least 1 mm ² , not more than 8 microns. Semiconductor arrangement according to one of the preceding claims, in which the upper contact plate ( 21 ) Molybdenum or consists of molybdenum; and / or the lower contact plate ( 22 ) Molybdenum or consists of molybdenum. Semiconductor arrangement according to one of Claims 1 to 5, in which the upper contact plate ( 21 ) two copper layers ( 211 . 212 ) and a first iron layer ( 210 ), the one ( 212 ) of the copper layers ( 211 . 212 ) on the semiconductor chip ( 1 ) facing side and the other ( 211 ) of the copper layers ( 211 . 212 ) on the semiconductor chip ( 1 ) facing away from the first iron layer ( 210 ) is located; and / or the lower contact plate ( 22 ) two copper layers ( 221 . 222 ) and a second iron layer ( 220 ), the one ( 221 ) of the copper layers ( 221 . 222 ) on the semiconductor chip ( 1 ) facing side and the other ( 222 ) of the copper layers ( 221 . 222 ) on the semiconductor chip ( 1 ) facing away from the second iron layer ( 220 ) is located. Semiconductor arrangement according to one of the preceding claims, in which the upper contact plate ( 21 ) consists of aluminum silicon carbide and / or the lower contact plate ( 22 ) consists of aluminum silicon carbide. Semiconductor arrangement according to one of Claims 1 to 7, in which the upper contact plate ( 21 ) a tile ( 215 aluminum nitride (AlN), partially or completely covered by aluminum ( 216 ) is wrapped; and / or the lower contact plate ( 22 ) a tile ( 225 aluminum nitride (AlN), partially or completely covered by aluminum ( 226 ) is wrapped. A semiconductor device according to any one of the preceding claims, which has no housing; or that does not have a housing that extends beyond a plane in which one of the semiconductor body ( 10 ) facing away ( 100t . 100b ) of the upper contact plate ( 21 ) or the lower contact plate ( 22 . 122 ) runs. A semiconductor device according to any one of the preceding claims, comprising: a flat top contact surface ( 100t ) formed by the semiconductor body ( 10 ) facing away ( 100t ) of the upper contact plate ( 21 ) is formed; a flat bottom contact surface ( 100b ) formed by the semiconductor body ( 10 ) facing away ( 100b ) of the lower contact plate ( 22 . 122 ) is formed; the upper contact surface ( 100t ) and the lower contact surface ( 100b ) which are the most projecting parts of the semiconductor device in the direction of their respective surface normals. Pressure contact arrangement comprising: an electrically conductive upper pressure piece ( 51 ); an electrically conductive lower pressure piece ( 52 ); one or more semiconductor devices according to one of the preceding claims, each of which is connected between the upper pressure piece ( 51 ) and the lower pressure piece ( 52 ) is clamped so that - between the upper contact plate ( 21 ) and the upper pressure piece ( 51 ) an electrically conductive pressure contact is formed; and / or - between the lower contact plate ( 22 ) and the lower pressure piece ( 52 ) An electrically conductive pressure contact is formed. Semiconductor chip ( 1 ) comprising: a semiconductor body ( 10 ), which has a top ( 10t ) and one of the top ( 10t ) opposite bottom ( 10b ) having; one on top ( 10t ) applied top chip metallization ( 11 ); and one on the bottom ( 10b ) applied lower chip metallization ( 12 ); wherein - the thickness (d61) of any plane and continuous section ( 61 ) of the upper chip metallization ( 11 ) having a footprint of at least 1 mm ² , is at most 8 μm; and / or the thickness (d62) of any plane and continuous section ( 62 ) of the lower chip metallization ( 12 ), which has a footprint of at least 1 mm ² , not more than 8 microns. Method for producing a semiconductor device according to one of Claims 1 to 10, comprising the steps of: providing a semiconductor chip ( 1 ), the - a semiconductor body ( 10 ) with a contact page ( 10t . 10b ) having; and - one on the contact page ( 10t . 10b ) applied chip metallization ( 11 . 12 . 112 ); Providing a metallic contact plate ( 21 . 22 . 122 ); Producing a sintered connection between a first contact surface of the chip metallization ( 11 . 12 . 112 ) and a second contact surface of the contact plate ( 21 . 22 . 122 ) by - Applying a first noble metal layer on the first contact surface, if this is not already formed as a noble metal surface; - Applying a second noble metal layer on the second contact surface, if this is not already formed as a noble metal surface; Application of a sinterable layer ( 31 ' . 32 ' . 132 ' ) comprising a noble metal powder, - on the first contact surface or, if previously provided with a first noble metal layer, on the first noble metal layer; and / or - on the second contact surface or, if previously provided with a second noble metal layer, on the second noble metal layer; - pressing together the semiconductor chip ( 1 ) and the contact plate ( 21 . 22 ) relative to each other so that the first contact surface and the second contact surface face each other and the paste ( 31 ' . 32 ' . 132 ' ) is located between the first contact surface and the second contact surface; Sintering the sinterable layer ( 31 ' . 32 ' . 132 ' ) while the semiconductor chip ( 1 ) and the contact plate ( 21 . 22 ) are pressed together by annealing the sinterable layer. Process according to Claim 13, in which the paste ( 31 ' . 32 ' . 132 ' ) is pre-sintered after application and before annealing in the range of 180 ° C to 300 ° C by, before and / or during the semiconductor chip ( 1 ) and the contact plate ( 21 . 22 ) are tempered for a period of at least 0.5 seconds in a temperature range of 90 ° C to 140 ° C, wherein the contact pressure in the range of 0.01 N / mm ² to 0.1 N / mm ² . Method according to Claim 13 or 14, in which the semiconductor chip ( 1 ) is present during annealing in the temperature range of 180 ° C to 300 ° C as part of a not yet separated wafer, and in which the wafer is separated after sintering. Method according to Claim 15, in which the contact plate ( 21 . 22 ) is separated together with the wafer. Method according to Claim 15, in which the contact plate ( 21 . 22 ) is connected by sintering in the temperature range of 180 ° C to 300 ° C only with a portion of the wafer, after the separation of the wafer complete component of the semiconductor chip ( 1 ).

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