Nothing Special   »   [go: up one dir, main page]

CN212277179U - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

Info

Publication number
CN212277179U
CN212277179U CN202021102476.3U CN202021102476U CN212277179U CN 212277179 U CN212277179 U CN 212277179U CN 202021102476 U CN202021102476 U CN 202021102476U CN 212277179 U CN212277179 U CN 212277179U
Authority
CN
China
Prior art keywords
substrate
vias
sensor die
semiconductor package
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202021102476.3U
Other languages
Chinese (zh)
Inventor
邓登峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Silan Microelectronics Co Ltd
Original Assignee
Hangzhou Silan Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hangzhou Silan Microelectronics Co Ltd filed Critical Hangzhou Silan Microelectronics Co Ltd
Priority to CN202021102476.3U priority Critical patent/CN212277179U/en
Application granted granted Critical
Publication of CN212277179U publication Critical patent/CN212277179U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The utility model provides a semiconductor package structure, external pad set up in the back of second base plate, and supreme transmission is down followed to the signal of sensor, and the back of first base plate does not receive blockking of external pad, can with determinand direct contact or with the air large tracts of land contact, effectively utilized the back of first base plate as the heat conduction face, improved heat-conducting efficiency.

Description

Semiconductor packaging structure
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a semiconductor packaging structure.
Background
Packaging is a process in which a die with an integrated circuit is placed on a substrate for load bearing, pins are led out, and then the die is fixed and packaged into a whole. The package may be in various forms, and may include dual in-line package (DIP), quad flat no-lead package (QFN), Land Grid Array (LGA), Ball Grid Array (BGA), and the like.
The traditional sensor is packaged by epoxy resin molding compound and DFN frame, and the packaging mode has poor heat conduction effect on the front side due to the fact that the thermal resistance of the epoxy resin molding compound on the front side is large and the thickness of the epoxy resin molding compound exceeds 200um, and heat conduction needs to be carried out through the back side. Meanwhile, the back surface also needs to be manufactured with an external bonding pad to be welded on the PCB, so that the back surface cannot be effectively utilized, a heat conduction path is increased, and the heat conduction efficiency is not high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor package structure can prevent that external pad from influencing heat-conduction, and then improves heat-conduction efficiency.
In order to achieve the above object, the present invention provides a semiconductor package structure, including:
a first substrate;
a sensor die on a front side of the first substrate;
a second substrate on a front side of the first substrate and covering the sensor die, the front side of the first substrate being opposite the front side of the second substrate;
the third substrate is positioned between the first substrate and the second substrate, the third substrate is provided with an accommodating space penetrating through the front surface and the back surface of the third substrate, and the sensor tube core is positioned in the accommodating space;
and the external bonding pads are positioned on the back surface of the second substrate and are electrically connected with corresponding pins of the sensor tube core.
Optionally, the sensor die is a temperature sensor die.
Optionally, the first substrate, the second substrate and the third substrate are all PCB boards.
Optionally, the first substrate includes a plurality of first vias penetrating through the front surface and the back surface thereof, the back surface of the first substrate is a temperature sensing surface, and the temperature sensing surface is used for acquiring heat and transferring the heat to the sensor die through the first vias.
Optionally, the sensor die is a non-temperature sensor die.
Optionally, the first substrate is a DBC plate.
Optionally, the first substrate includes a plurality of first via holes penetrating through the front surface and the back surface of the first substrate, the back surface of the first substrate is a heat dissipation surface, and the first via holes transfer heat of the sensor die to the heat dissipation surface.
Optionally, the first via holes are uniformly distributed in an area of the first substrate corresponding to the accommodating space.
Optionally, the second substrate includes a plurality of second via holes penetrating through the front and back surfaces thereof, the third substrate includes a plurality of third via holes penetrating through the front and back surfaces thereof, one end of each second via hole is electrically connected with the corresponding external bonding pad, and the other end of each second via hole is electrically connected with the corresponding pin of the sensor die through the corresponding third via hole.
Optionally, the second via hole corresponds to the third via hole one to one, the second via hole and both ends of the third via hole are provided with first internal connection pads, the second via hole is electrically connected with the corresponding third via hole through the corresponding first internal connection pads, and the second via hole is electrically connected with the corresponding pin of the sensor tube core through the corresponding second internal connection pads and the corresponding lead.
Optionally, the second internal connection pads are disposed on the front surface of the first substrate and divided into two groups, corresponding ones of the two groups of second internal connection pads are electrically connected, one group of second internal connection pads is located outside the area of the first substrate corresponding to the receiving space and electrically connected to the first internal connection pads of the corresponding second vias, and the other group of second internal connection pads is located inside the area of the first substrate corresponding to the receiving space and electrically connected to the corresponding pins of the sensor die through the leads.
Optionally, the method further includes:
a thermally conductive adhesive layer between the back surface of the sensor die and the front surface of the first substrate to bond the back surface of the sensor die to the front surface of the first substrate;
and the heat conduction encapsulating glue layer covers the front surface of the sensor tube core and circumferentially extends to cover part of the front surface of the first substrate so as to isolate the sensor tube core from the outside.
Optionally, the sensor die comprises:
a first back gold layer covering a back side of the sensor die.
Optionally, the sensor die has a thickness of less than 60 microns.
Optionally, the first substrate further includes:
and the second back gold layer covers the back surface of the first substrate.
Optionally, a gold plating layer covers an area of the front surface of the first substrate corresponding to the accommodating space.
Optionally, the thickness of the first substrate is less than 200 microns.
The utility model provides a semiconductor packaging structure has following beneficial effect:
(1) the external bonding pad is arranged on the back surface of the second substrate, signals of the sensor are transmitted from bottom to top, the back surface of the first substrate is not blocked by the external bonding pad and can be in direct contact with an object to be measured or in large-area contact with air, the back surface of the first substrate is effectively utilized as a heat conduction surface, and the heat conduction efficiency is improved;
(2) arranging a sensor tube core in the accommodating space of the third substrate and arranging the sensor tube core on the front surface of the first substrate, and transferring heat between the back surface of the first substrate and the sensor tube core by utilizing the first through hole, so that the heat conduction efficiency is improved, and the heat conduction path is shortened;
(3) when the sensor tube core is the temperature sensor tube core, heat is transferred to the sensor tube core from the back surface of the first substrate through the first through hole, so that temperature detection is realized, and the accuracy and the sensitivity of the temperature detection are improved by shortening a heat conduction path;
(4) when the sensor tube core is a non-temperature sensor tube core, heat is transferred from the sensor tube core to the back surface of the first substrate through the first through hole, so that heat dissipation of the sensor tube core is realized, and the heat dissipation effect is improved by shortening a heat conduction path;
(5) the second through hole and the third through hole are respectively arranged in the second substrate and the third substrate, so that detection signals of the sensor tube core can be transmitted, and meanwhile, the third substrate also has the function of supporting the second substrate;
(6) the back surface of the sensor tube core is directly bonded on the front surface of the first substrate through the heat-conducting bonding glue layer, so that three-dimensional and all-dimensional efficient heat conduction of the sensor tube core can be further realized, the temperature detection precision is improved, and the heat conductivity of the heat-conducting bonding glue is good, so that the temperature detection cannot be adversely affected;
(7) the first back gold layer and the second back gold layer are respectively arranged on the back surface of the sensor tube core and the back surface of the first substrate, so that the heat conduction efficiency is further improved, and the second back gold layer can enlarge the temperature sensing area and simultaneously prevent the temperature sensing surface from being oxidized;
(8) the thickness of the control sensor die is less than 60 microns and the thickness of the first substrate is less than 200 microns, thereby further shortening the thermal conduction path.
Drawings
Fig. 1 is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first substrate in a semiconductor package structure according to an embodiment of the present invention;
wherein the reference numerals are:
100-a first substrate; 100 a-the front side of the first substrate; 100b — the back side of the first substrate; 101-a first via;
200-a second substrate; 200 a-the front side of the second substrate; 200 b-the back side of the second substrate; 201-external connection pad; 202-a second via;
300-a third substrate; 300 a-the front side of the third substrate; 300 b-the back side of the third substrate; 301-a receiving space, 302-a third via hole;
203. 303-first inner bond pad; 102. 103-second inner bond pad;
400-a sensor die; 401-lead;
501-heat conducting adhesive layer; 502-heat conducting potting adhesive layer.
Detailed Description
The following description of the embodiments of the present invention will be described in more detail with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in simplified form and are not to precise scale, and are provided for convenience and clarity in order to facilitate the description of the embodiments of the present invention.
Example one
Fig. 1 is a schematic view of a semiconductor package structure provided in an embodiment of the present invention, and fig. 2 is a schematic view of a first substrate 100 in the semiconductor package structure provided in an embodiment of the present invention. As shown in fig. 1 and fig. 2, the semiconductor package structure provided in this embodiment includes a first substrate 100, a second substrate 200, a third substrate 300, a sensor die 400, and a plurality of external pads 201. The first substrate 100, the third substrate 300 and the second substrate 200 are sequentially overlapped to form a sandwich structure, and the first substrate 100, the second substrate 200, the third substrate 300 and the sensor die 400 have opposite front and back surfaces. Specifically, the first substrate 100 has opposing front and back surfaces 100a, 100b, the second substrate 200 has opposing front and back surfaces 200a, 200b, the third substrate 300 has opposing front and back surfaces 300a, 300b, and the front surface of the sensor die 400 is the electrical connection surface thereof.
The third substrate 300 is disposed on the front surface 100a of the first substrate 100, and the back surface 300b of the third substrate 300 is attached to the front surface 100a of the first substrate 100. The third substrate 300 has a receiving space 301 penetrating through the front surface 300a and the back surface 300b thereof, the sensor die 400 is received in the receiving space 301 and located on the front surface 100a of the first substrate 100, and the back surface (a surface different from the electrical connection surface) of the sensor die 400 is attached to the front surface 100a of the first substrate 100. The second substrate 200 is disposed on the front surface 300a of the third substrate 300, and the front surface 200a of the second substrate 200 is attached to the front surface 300a of the third substrate 300. In this way, the front surface 100a of the first substrate 100 is opposite to the front surface 200a of the second substrate 200, the first substrate 100 plays a role in bearing, the second substrate 200 plays a role in covering, and the front surfaces 100a and 200a of the first substrate 100 and the second substrate 200 respectively cover two ends of the accommodating space 301, so as to seal the accommodating space 301 to isolate the outside from the sensor die 400, thereby protecting the sensor die 400.
In this embodiment, the sensor die 400 is first mounted on the front surface 100a of the first substrate 100 by a reflow process, and the sensor die 400 may be thinned and gold-backed before mounting to support a reflow operation. Then, the back surface 300b of the third substrate 300 is disposed on the front surface 100a of the first substrate 100 through a reflow process, the back surface 300b of the third substrate 300 is disposed with an annular land, and the bottom of the accommodating space 301 is sealed by reflow. Finally, the front surface 200a of the second substrate 200 is disposed on the front surface 300a of the third substrate 300 through a reflow soldering process, the front surface 200a of the second substrate 200 is provided with an annular welding area, and the top of the accommodating space 301 is sealed through reflow soldering, so that the sealing effect is improved.
In this embodiment, the sensor die 400 is a temperature sensor die. The back surface 100b of the first substrate 100 is a temperature sensing surface and can be directly contacted with an object to be measured, and heat of the object to be measured is transferred to the sensor die 400 through a plurality of first via holes 101 which are arranged in the first substrate 100 and penetrate through the front surface 100a and the back surface 100b of the first substrate to realize temperature detection; external bonding pad 201 set up in the back 200b of second base plate 200 and with sensor die 400's corresponding pin electric connection, external bonding pad 201 for example can with a PCB board electric connection, the signal accessible that sensor die 400 detected external bonding pad 201 transmit to on the PCB board, through signal processing, can obtain the temperature of testee. It can be understood that the utility model discloses will the back 100b of first base plate 100 will as the temperature sensing face external pad 201 set up in the back 200b of second base plate 200, both positions are carried on the back mutually, and the during operation does not influence each other, compares in prior art, the utility model provides a temperature sensing face does not receive external pad 201 block direct and the determinand contact, has shortened heat-conduction path, improves the accuracy and the sensitivity that the temperature detected.
In this embodiment, the first via 101 is located in a region of the first substrate 100 corresponding to the accommodating space 301, so that heat can be better transferred to the sensor die 400.
Further, the second substrate 200 includes a plurality of second vias 202 penetrating through the front surface 200a and the back surface 200b thereof, the third substrate 300 includes a plurality of third vias 302 penetrating through the front surface 300a and the back surface 300b thereof, one end of each of the second vias 202 is electrically connected to a corresponding external pad 201, and the other end is electrically connected to a corresponding pin of the sensor die 400 through the third via 302.
With reference to fig. 1 and fig. 2, the front surface of the sensor die 400 has 4 pins, the second via 202, the third via 302, and the external pad 201 have 4 pins, and the second via 202, the third via 302, and the external pad 201 are in one-to-one correspondence.
The front surface 100a of the first substrate 100 is provided with 4 second inner contact pads 103 and 4 second inner contact pads 102, where the 4 second inner contact pads 103 are a group of second inner contact pads, and the 4 second inner contact pads 102 are another group of second inner contact pads. The 4 second inner pads 102 are distributed on the peripheries of the 4 second inner pads 103, and one second inner pad 102 is electrically connected to one second inner pad 103 correspondingly. The 4 second internal connection pads 103 are located in an area of the first substrate 100 corresponding to the accommodating space 301, and the 4 second internal connection pads 102 are located outside the area of the first substrate 100 corresponding to the accommodating space 301. The front surface 300a and the back surface 300b of the third substrate 300 respectively have 4 first inner pads 303, and two ends of each third via hole 302 are electrically connected to one first inner pad 303 of the front surface 300a and the back surface 300b of the third substrate 300 respectively. The front surface 200a and the back surface 200b of the second substrate 200 respectively have 4 first inner pads 203, and two ends of each second via 202 are electrically connected to one first inner pad 203 of the front surface 200a and the back surface 200b of the second substrate 200 respectively.
Each pin of the sensor die 400 is electrically connected to the corresponding second inner bonding pad 103 through a lead 401, each second inner bonding pad 102 is electrically connected to the corresponding first inner bonding pad 303 on the back surface 300b of the third substrate 300, each first inner bonding pad 303 on the front surface 300a of the third substrate 300 is electrically connected to the corresponding first inner bonding pad 203 on the front surface 200a of the second substrate 200, and each first inner bonding pad 203 on the back surface 200b of the second substrate 200 is electrically connected to the corresponding outer bonding pad 201. In this way, each pin of the sensor die 400 can be electrically connected to the corresponding external pad 201 through the second via 202 and the third via 302, so as to realize signal connection between the sensor die 400 and the PCB.
It should be understood that the sensor die 400 of the present invention is not limited to having 4 pins, the number of pins of the sensor die 400 can be any number, and the number of the second via 202 and the third via 302 can also be adjusted according to the number of pins of the sensor die 400, which is not limited by the present invention.
Further, a heat conductive adhesive layer 501 is disposed between the back surface of the sensor die 400 and the front surface 100a of the first substrate 100, and the back surface of the sensor die 400 is directly bonded to the front surface 100a of the first substrate 100 through the heat conductive adhesive layer 501, so that efficient heat conduction of the sensor die 400 in three dimensions and all directions can be further achieved, the accuracy of temperature detection is improved, and the heat conductive adhesive has good heat conductivity and does not have adverse effects on temperature detection. Of course, the present invention is not limited to the use of the thermal conductive adhesive layer 501 to bond the sensor die 400 to the front surface 100a of the first substrate 100, and other bonding materials with high thermal conductivity may be used.
It should be understood that the temperature sensor die 400 may also be directly disposed on the front surface 100a of the first substrate 100 by using a reflow process, and the thermal adhesive layer 501 may be omitted.
The front surface of the sensor die 400 is provided with a heat conductive potting layer 502, and the heat conductive potting layer 502 covers the front surface of the sensor die 400 and extends circumferentially to cover a portion of the front surface 100a of the first substrate 100. As such, the thermal conductive encapsulant layer 502 may completely encapsulate the front and side surfaces of the sensor die 400, thereby isolating the sensor die 400 from the outside and preventing the outside from invading the sensor die 400.
In this embodiment, the thickness of the sensor die 400 is controlled to be less than 60 microns, which facilitates heat transfer from the substrate on the backside of the sensor die 400 to the internal sensing devices.
Further, the back surface of the sensor die 400 is formed with a first back gold layer by a back gold process, and the first back gold layer may be made of a back gold material.
In this embodiment, the thickness of the first substrate 100 is controlled to be less than 200 μm, so that the heat conduction distance can be further shortened and the heat conduction efficiency can be improved.
Further, a second back gold layer is formed on the back surface 100b of the first substrate 100 through a back gold process, and the effect of the second back gold layer is the same as that of the first back gold layer, and the second back gold layer can further improve the thermal conductivity of the first substrate 100. Moreover, the second gold backing layer can completely cover the back surface 100b of the first substrate 100, so that the whole back surface 100b of the first substrate 100 can sense temperature, the area of heat conduction is increased when in use, and the second gold backing layer can prevent the back surface 100b of the first substrate 100 from being oxidized due to air contact, thereby protecting the temperature sensing surface.
It can be understood that the structure of the first back gold layer may be the same as that of the first back gold layer, and redundant description is omitted here.
In this embodiment, the first substrate 100, the second substrate 200, and the third substrate 300 are single-layer PCB boards, and BT core material, FR4 core material, ceramic core material, or other core materials may be used. As an alternative embodiment, the first substrate 100, the second substrate 200, and the third substrate 300 may also be at least two layers of PCB boards, which is not limited by the present invention.
Optionally, the first via hole 101, the second via hole 202, and the third via hole 302 may be plated copper plug holes in a PCB, and a gold plating process is performed on an area of the first substrate 100 where the sensor die 400 is disposed to form a gold plating layer, in this embodiment, the gold plating layer covers an area of the first substrate 100 corresponding to the accommodating space 301, so as to reduce thermal resistance.
In this embodiment, the planar shapes of the first substrate 100, the second substrate 200, the third substrate 300 and the sensor die 400 are all square, the planar shape of the accommodating space 301 is a petal shape, and the sensor die 400 may be disposed in the center of the accommodating space 301 to enhance the reliability of the structure.
It is understood that the planar shapes of the first substrate 100, the second substrate 200, the third substrate 300, and the sensor die 400 are not limited to being square, and the planar shape of the accommodating space 301 is not limited to being a petal shape, but may be any other possible shapes. Optionally, the planar shapes of the first substrate 100, the second substrate 200, the third substrate 300 and the sensor die 400 are the same, and the planar shape of the accommodating space 301 may be the same as or different from the planar shapes of the first substrate 100, the second substrate 200, the third substrate 300 and the sensor die 400.
Example two
Referring to fig. 1 and fig. 2, unlike the first embodiment, the sensor die 400 is a non-temperature sensor die. At this time, the back surface 100b of the first substrate 100 is a heat dissipation surface, and the first via 101 may transfer heat generated by the sensor die 400 during operation to the heat dissipation surface, so as to implement a heat dissipation function of the sensor die 400. The heat dissipation effect may be improved by shortening the thermal conduction path between the sensor die 400 and the heat dissipation surface.
Further, in this embodiment, the first substrate 100, the second substrate 200, and the third substrate 300 may all be single-layer PCB boards, and optionally, the first substrate 100 may be a DBC board, and since the DBC board has high thermal conductivity, the heat dissipation effect may be further improved.
To sum up, in the semiconductor package structure provided by the utility model, external pad sets up in the back of second base plate, and supreme transmission is down followed to the signal of sensor, and the back of first base plate does not receive blockking of external pad, can with determinand direct contact or with air large tracts of land contact, effectively utilized the back of first base plate as the heat conduction face, improved heat-conducting efficiency.
Furthermore, a sensor tube core is arranged in the accommodating space of the third substrate and arranged on the front surface of the first substrate, and heat is transferred between the back surface of the first substrate and the sensor tube core by utilizing the first through hole, so that the heat conduction efficiency is improved, and the heat conduction path is shortened.
Further, when the sensor die is a temperature sensor die, heat is transferred from the back surface of the first substrate to the sensor die through the first via hole, so that temperature detection is realized, and accuracy and sensitivity of temperature detection are improved by shortening a heat conduction path.
Further, when the sensor tube core is a non-temperature sensor tube core, heat is transferred from the sensor tube core to the back surface of the first substrate through the first through hole, heat dissipation of the sensor tube core is achieved, and the heat dissipation effect is improved by shortening a heat conduction path.
Furthermore, a second through hole and a third through hole are respectively arranged in the second substrate and the third substrate, so that detection signals of the sensor tube core can be transmitted, and meanwhile, the third substrate also has the function of supporting the second substrate.
Further, the back of the sensor tube core is directly bonded on the front of the first substrate through the heat-conducting adhesive layer, so that high-efficiency heat conduction of the sensor tube core in a three-dimensional and all-dimensional mode can be further achieved, the temperature detection precision is improved, the heat conductivity of the heat-conducting adhesive is good, and adverse effects on temperature detection cannot be caused.
Furthermore, the first back gold layer and the second back gold layer are arranged on the back surface of the sensor tube core and the back surface of the first substrate respectively, so that the heat conduction efficiency is further improved, and the second back gold layer can enlarge the temperature sensing area and prevent the temperature sensing surface from being oxidized.
Further, the thickness of the control sensor die is less than 60 microns and the thickness of the first substrate is less than 200 microns, thereby further shortening the thermal conduction path.
The above description is only for the preferred embodiment of the present invention, and does not limit the present invention. Any technical personnel who belongs to the technical field, in the scope that does not deviate from the technical scheme of the utility model, to the technical scheme and the technical content that the utility model discloses expose do the change such as the equivalent replacement of any form or modification, all belong to the content that does not break away from the technical scheme of the utility model, still belong to within the scope of protection of the utility model.

Claims (16)

1. A semiconductor package structure, comprising:
a first substrate;
a sensor die on a front side of the first substrate;
a second substrate on a front side of the first substrate and covering the sensor die, the front side of the first substrate being opposite the front side of the second substrate;
the third substrate is positioned between the first substrate and the second substrate, the third substrate is provided with an accommodating space penetrating through the front surface and the back surface of the third substrate, and the sensor tube core is positioned in the accommodating space;
and the external bonding pads are positioned on the back surface of the second substrate and are electrically connected with corresponding pins of the sensor tube core.
2. The semiconductor package structure of claim 1, wherein the sensor die is a temperature sensor die.
3. The semiconductor package structure of claim 1, wherein the first substrate, the second substrate, and the third substrate are all PCB boards.
4. The semiconductor package structure of claim 3, wherein the first substrate includes a plurality of first vias through the front and back surfaces thereof, and wherein the back surface of the first substrate is a temperature sensing surface for capturing heat and transferring the heat to the sensor die through the first vias.
5. The semiconductor package structure of claim 1, wherein the first substrate is a DBC board.
6. The semiconductor package structure of claim 5, wherein the first substrate includes a plurality of first vias through the front and back surfaces thereof, the back surface of the first substrate being a heat spreading surface, the first vias transferring heat from the sensor die to the heat spreading surface.
7. The semiconductor package structure of claim 4 or 6, wherein the first vias are uniformly distributed in an area of the first substrate corresponding to the accommodating space.
8. The semiconductor package structure of claim 1, wherein the second substrate includes a plurality of second vias through the front and back surfaces thereof, and the third substrate includes a plurality of third vias through the front and back surfaces thereof, one ends of the second vias being electrically connected to corresponding external pads, and the other ends of the second vias being electrically connected to corresponding pins of the sensor die through the third vias.
9. The semiconductor package structure of claim 8, wherein the second vias correspond to the third vias one-to-one, first inner pads are disposed at two ends of each of the second vias and the third vias, the second vias are electrically connected to the corresponding third vias through the corresponding first inner pads, and the second vias are electrically connected to the corresponding pins of the sensor die through the corresponding second inner pads and leads.
10. The semiconductor package structure of claim 9, wherein the second inner pads are disposed on the front surface of the first substrate and are divided into two groups, and corresponding second inner pads of the two groups of second inner pads are electrically connected, wherein one group of second inner pads is located outside the area of the first substrate corresponding to the receiving space and electrically connected to corresponding first inner pads of the second vias, and the other group of second inner pads is located inside the area of the first substrate corresponding to the receiving space and electrically connected to corresponding pins of the sensor die through the leads.
11. The semiconductor package structure of claim 1, further comprising:
a thermally conductive adhesive layer between the back surface of the sensor die and the front surface of the first substrate to bond the back surface of the sensor die to the front surface of the first substrate;
and the heat conduction encapsulating glue layer covers the front surface of the sensor tube core and circumferentially extends to cover part of the front surface of the first substrate so as to isolate the sensor tube core from the outside.
12. The semiconductor package structure of claim 1, wherein the sensor die comprises:
a first back gold layer covering a back side of the sensor die.
13. The semiconductor package structure of claim 1, wherein the sensor die is less than 60 microns thick.
14. The semiconductor package structure of claim 1, wherein the first substrate further comprises:
and the second back gold layer covers the back surface of the first substrate.
15. The semiconductor package structure of claim 1, wherein a gold plating layer covers a region of the front surface of the first substrate corresponding to the accommodating space.
16. The semiconductor package structure of claim 1, wherein the first substrate has a thickness of less than 200 microns.
CN202021102476.3U 2020-06-12 2020-06-12 Semiconductor packaging structure Active CN212277179U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202021102476.3U CN212277179U (en) 2020-06-12 2020-06-12 Semiconductor packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202021102476.3U CN212277179U (en) 2020-06-12 2020-06-12 Semiconductor packaging structure

Publications (1)

Publication Number Publication Date
CN212277179U true CN212277179U (en) 2021-01-01

Family

ID=73882884

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202021102476.3U Active CN212277179U (en) 2020-06-12 2020-06-12 Semiconductor packaging structure

Country Status (1)

Country Link
CN (1) CN212277179U (en)

Similar Documents

Publication Publication Date Title
US5977633A (en) Semiconductor device with metal base substrate having hollows
JP2878243B2 (en) Multi-electronic device package
US7196403B2 (en) Semiconductor package with heat spreader
US9472485B2 (en) Hybrid thermal interface material for IC packages with integrated heat spreader
US5291062A (en) Area array semiconductor device having a lid with functional contacts
US7691681B2 (en) Chip scale package having flip chip interconnect on die paddle
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
JP4828164B2 (en) Interposer and semiconductor device
US20020034066A1 (en) Heat dissipation ball grid array package
CN102420217A (en) Multi-chip semiconductor packages and assembly thereof
KR20010090379A (en) Semiconductor package
CN101165866A (en) Integrated circuit package and method of making same
KR20030018642A (en) Stack chip module
KR20170084174A (en) Sensing chip encapsulation component and electronic device with same
JP4075204B2 (en) Multilayer semiconductor device
CN212277179U (en) Semiconductor packaging structure
CN212482727U (en) Semiconductor packaging structure
JPH09199629A (en) Semiconductor device
JP2000232186A (en) Semiconductor device and its manufacture
US7235889B2 (en) Integrated heatspreader for use in wire bonded ball grid array semiconductor packages
CN102332410A (en) Packaging method and structure of chip
US9997445B2 (en) Substrate interconnections for packaged semiconductor device
JPH09331004A (en) Semiconductor device
TWM267628U (en) Packaging structure with drill holes formed directly below an underfill layer
CN216012531U (en) Lora temperature measuring device of integrated microcontroller

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant