CN210778574U

CN210778574U - DBC structure suitable for high-voltage power device module packaging

Info

Publication number: CN210778574U
Application number: CN201921548298.4U
Authority: CN
Inventors: 姚金才; 陈宇; 朱超群
Original assignee: Shenzhen Hester Technology Co ltd
Current assignee: Shenzhen Hester Technology Co ltd
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2020-06-16
Anticipated expiration: 2029-09-18

Abstract

The utility model discloses a DBC structure suitable for high-voltage power device module encapsulation, including well ceramic insulating layer, well ceramic insulating layer's both sides are provided with copper layer and lower copper layer respectively, upward be provided with high temperature resistant insulating medium layer on the copper layer. The utility model discloses when carrying out chip and DBC welding, the chip is fixed inside the concave surface on DBC copperplate, and the skew can no longer appear in the chip position, improves the yield of chip paster and the yield of whole process and the reliability of final product, adopts this DBC structure to carry out the module encapsulation, all can carry out high-voltage testing behind packaging technology, discovers bad product in advance, handles in advance, reduces the encapsulation cost.

Description

DBC structure suitable for high-voltage power device module packaging

Technical Field

The utility model relates to the field of semiconductor technology, specifically be a DBC structure suitable for high-voltage power device module encapsulation.

Background

The DBC (direct copper bonding) is a key component of a power device module package, and generally comprises an upper copper layer, a middle ceramic insulating layer and a lower copper layer, and has main functions of realizing interconnection of multiple chips in different topological structures, realizing electrical isolation of devices, serving as a main heat dissipation channel of the devices, and the like. Wherein, the copper layer under the DBC is usually soldered on the bottom plate of the module by solder, and is mainly used for realizing the connection between the DBC and the bottom plate. The upper copper layer is usually connected with the back metal of the power device chip through solder, so that the multiple chips are interconnected in different topologies.

Because the side of the back side of the chip that is connected to the upper copper layer of the DBC is a flat surface, the surface of the upper copper layer of the existing DBC is typically designed to be fabricated as a flat surface with respect to the chip contact area and the periphery (other than the electrical isolation of the device), as shown in fig. 1.

When a chip in the module packaging process is welded with a DBC (direct bonded copper) and the surface of a copper layer on the DBC is smooth, the chip can be deviated from a preset position frequently, the subsequent technological process is influenced, the product can be seriously failed even, the product failure rate is raised, and the packaging cost is increased.

With the development of new materials and new chip technologies, particularly the development of SiC materials and process technologies, the chip withstand voltage is improved, the chip size of the same specification is reduced, and the terminal size of the SiC power device with the same withstand voltage is far smaller than that of the Si device, which brings certain difficulties to the test in the device module packaging process. Because the surface of the copper layer on the DBC is a plane with the contact area and the periphery (except the electrical isolation of a device) of the chip, when a high-voltage test is carried out after the copper layer is welded with the back of the chip, a high-voltage arc is generated at the periphery of the chip, and the chip is easy to break down at high voltage through the periphery of the chip due to the small size of the terminal of the chip, thereby damaging the chip. Therefore, in the current high-voltage device, especially a SiC high-voltage power device, in the module packaging process, the high-voltage test is not performed until after glue filling, and the test except the high voltage is performed before glue filling, so that even if the device is in voltage withstanding state, the device cannot be detected, and the packaging cost is greatly increased.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a DBC structure suitable for high-voltage power device module encapsulation, when carrying out chip and DBC welding, the chip is fixed inside the concave surface on DBC copperplate, the skew can no longer appear in the chip position, the yield of improvement chip paster and whole process and the reliability of final product, adopt this DBC structure to carry out module encapsulation, can all carry out high-voltage testing behind packaging technology, discover bad product in advance, handle in advance, reduce the encapsulation cost, in order to solve the problem that proposes among the above-mentioned background art.

In order to achieve the above object, the utility model provides a following technical scheme:

a DBC structure suitable for module packaging of a high-voltage power device comprises a middle ceramic insulating layer, wherein an upper copper layer and a lower copper layer are respectively arranged on two sides of the middle ceramic insulating layer, and a high-temperature-resistant insulating medium layer is arranged on the upper copper layer; the welding surface of the upper copper layer is provided with at least one concave surface for placing a chip, and the high-temperature-resistant insulating medium layer is arranged on the peripheral side surface of the concave surface; the depth of the concave surface is smaller than the sum of the thickness of the soldering lug and the thickness of the chip by 1-2 mm; the shape of the concave surface is the same as that of the chip, and the size of the concave surface is larger than that of the chip by 0.5-1 mm; the high-temperature-resistant insulating medium layer is fixedly bonded on the upper copper layer welding surface, at least one high-temperature-resistant insulating medium layer is arranged, and welding holes are formed in the high-temperature-resistant insulating medium layer; the welding hole is communicated with the upper copper layer; the depth of the welding hole is smaller than the sum of the thickness of the welding sheet and the thickness of the chip by 1-2 mm.

Preferably, the shape of the solder hole is the same as that of the chip, and the size of the solder hole is 0.5-1 mm larger than that of the chip; the voltage withstanding value of the high-temperature resistant insulating medium layer is higher than that of the chip; the temperature resistance of the high-temperature-resistant insulating medium layer is higher than the highest welding temperature in the module packaging process.

Compared with the prior art, the beneficial effects of the utility model are that:

when the DBC structure is adopted to weld a chip and a DBC, the chip is fixed inside the concave surface of the copper layer on the DBC, the position of the chip can not deviate any more, and the yield of chip mounting, the yield of the whole technological process and the reliability of a final product are improved.

When the DBC structure is used for module packaging, high-voltage testing can be carried out after a packaging process, defective products are found in advance, processing is carried out in advance, and packaging cost is reduced.

Drawings

FIG. 1 is a diagram of a DBC structure in the prior art;

fig. 2 is a schematic structural diagram of a DBC according to the present invention;

fig. 3 is a schematic cross-sectional view of fig. 2 of the present invention;

fig. 4 is a schematic diagram illustrating a welding process between a DBC structure and a chip according to the present invention;

fig. 5 is a schematic structural view of another DBC according to the present invention;

fig. 6 is a schematic cross-sectional view of fig. 5 of the present invention;

fig. 7 is a schematic diagram of another DBC structure and chip bonding according to the present invention.

In the figure: 1. coating a copper layer; 2. a middle ceramic insulating layer; 3. a lower copper layer; 4. a concave surface; 5. a high temperature resistant insulating medium layer; 6. and (7) welding holes.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Example 1

Referring to fig. 2-4, the present invention provides a technical solution:

the DBC structure comprises a middle ceramic insulating layer 2, wherein an upper copper layer 1 and a lower copper layer 3 are respectively arranged on two sides of the middle ceramic insulating layer 2, and a high-temperature-resistant insulating medium layer 5 is arranged on the upper copper layer 1.

At least one concave surface 4 for placing a chip is arranged on the welding surface of the upper copper layer 1, the high-temperature-resistant insulating medium layer 5 is arranged on the peripheral side surface of the concave surface 4, the depth of the concave surface 4 is 1-2 mm smaller than the sum of the thickness of the welding piece and the thickness of the chip, the shape of the concave surface 4 is the same as that of the chip, and the size of the concave surface 4 is 0.5-1 mm larger than that of the chip.

The withstand voltage value of the high-temperature-resistant insulating medium layer 5 is higher than that of the chip, and the temperature resistance of the high-temperature-resistant insulating medium layer 5 is higher than the highest welding temperature in the module packaging process.

Example 2

Referring to fig. 5-7, the difference from embodiment 1 is:

the high-temperature-resistant insulating dielectric layer 5 is fixedly bonded on the welding surface of the upper copper layer 1, at least one high-temperature-resistant insulating dielectric layer 5 is arranged, a welding hole 6 is formed in the high-temperature-resistant insulating dielectric layer 5, the welding hole 6 is communicated with the upper copper layer 1, the depth of the welding hole 6 is 1-2 mm smaller than the sum of the thickness of a welding piece and the thickness of a chip, the shape of the welding hole 6 is the same as that of the chip, and the size of the welding hole 6 is 0.5-1 mm larger than that of the chip.

To sum up, the utility model discloses lie in the high temperature resistant insulating medium layer 2 or the high temperature resistant insulating medium layer 2 that the surface of last copper layer 1 that this DBC mechanism had increased the concave surface 4 and concave surface 4 around the fixed chip position with traditional DBC's main difference, the copper layer 1 surface contains a plurality of welding holes 6. The concave surface 4 or the solder hole 6 is provided for fixing the chip position and avoiding the chip offset when the chip is mounted. The high-temperature-resistant insulating medium layer 2 around the concave surface 4 or the welding hole 6 can avoid the breakdown of a chip during high-voltage testing, and the structure is formed in the DBC production process, so that the complexity of the packaging process cannot be increased, the packaging efficiency can be improved, and the packaging cost can be reduced.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A DBC structure suitable for module packaging of a high-voltage power device comprises a middle ceramic insulating layer (2), and is characterized in that: an upper copper layer (1) and a lower copper layer (3) are respectively arranged on two sides of the middle ceramic insulating layer (2), and a high-temperature-resistant insulating medium layer (5) is arranged on the upper copper layer (1); at least one concave surface (4) for placing a chip is arranged on the welding surface of the upper copper layer (1), and the high-temperature-resistant insulating medium layer (5) is arranged on the peripheral side surface of the concave surface (4); the depth of the concave surface (4) is smaller than the sum of the thickness of the soldering lug and the thickness of the chip by 1-2 mm; the shape of the concave surface (4) is the same as that of the chip, and the size of the concave surface (4) is 0.5-1 mm larger than that of the chip; the high-temperature-resistant insulating medium layer (5) is fixedly bonded on the welding surface of the upper copper layer (1), at least one high-temperature-resistant insulating medium layer (5) is arranged, and welding holes (6) are formed in the high-temperature-resistant insulating medium layer (5); the welding hole (6) is communicated with the upper copper layer (1); the depth of the welding hole (6) is smaller than the sum of the thickness of the welding sheet and the thickness of the chip by 1-2 mm; the shape of the welding hole (6) is the same as that of the chip, and the size of the welding hole (6) is larger than that of the chip by 0.5-1 mm; the voltage withstanding value of the high-temperature resistant insulating medium layer (5) is higher than that of the chip; the temperature resistance of the high-temperature-resistant insulating medium layer (5) is higher than the highest welding temperature in the module packaging process.