CN217881530U - P type solar cell, cell module and photovoltaic system - Google Patents

Abstract

The application is suitable for the technical field of solar cells, and provides a P-type solar cell, a cell module and a photovoltaic system. A P-type solar cell includes: a P-type silicon wafer; the tunneling oxide layer, the doped polycrystalline silicon layer, the first passivation layer and the first electrode are sequentially stacked on the first surface of the P-type silicon wafer, the first electrode is a silver electrode, and the first electrode penetrates through the first passivation layer to be in contact with the doped polycrystalline silicon; the aluminum oxide layer, the second passivation layer and the second electrode are sequentially stacked on the second surface of the P-type silicon wafer, the second electrode comprises an aluminum electrode, the aluminum oxide layer and the second passivation layer are provided with slotted regions, the P-type silicon wafer below the slotted regions forms an invaginated region, the second electrode penetrates through the slotted regions, an aluminum doped layer is formed on the surfaces of the invaginated region, and an aluminum-silicon alloy layer is filled in the invaginated region. Therefore, the manufactured P-type solar cell can resist radiation on two sides, so that attenuation caused by radiation is reduced, the cost is low, and the photoelectric conversion efficiency is high.

Description

P-type solar cell, cell module and photovoltaic system

Technical Field

The application belongs to the technical field of solar cells, and particularly relates to a P-type solar cell, a cell module and a photovoltaic system.

Background

Solar cell power generation is a sustainable clean energy source that can convert sunlight into electrical energy using the photovoltaic effect of semiconductor p-n junctions.

In the related art, a silicon nitride layer is generally provided on a solar cell, or a silicon oxide layer and a silicon nitride layer are provided on a solar cell, thereby reducing reflection of sunlight. However, the attenuation of the solar cell is too high in environments with strong ultraviolet radiation, such as plateaus, seas or outer spaces, and a high failure risk is caused.

Therefore, how to improve the radiation resistance effect of the solar cell becomes a problem to be solved urgently.

SUMMERY OF THE UTILITY MODEL

The application provides a P type solar cell, battery pack and photovoltaic system, aims at solving the problem of how to improve the anti-radiation effect of solar cell.

In a first aspect, the present application provides a P-type solar cell comprising:

a P-type silicon wafer;

the tunneling oxide layer, the doped polysilicon layer, the first passivation layer and the first electrode are sequentially stacked on the first surface of the P-type silicon wafer, the first electrode is a silver electrode, and the first electrode penetrates through the first passivation layer to be in contact with the doped polysilicon;

the aluminum oxide layer, the second passivation layer and the second electrode are sequentially stacked on the second surface of the P-type silicon wafer, the second electrode comprises an aluminum electrode, the aluminum oxide layer and the second passivation layer are provided with a slotted region, the P-type silicon wafer below the slotted region forms an invaginated region, the second electrode penetrates through the slotted region, an aluminum doped layer is formed on the surface of the invaginated region, and an aluminum-silicon alloy layer is filled in the invaginated region.

Optionally, the second electrode includes a fine grid, a main grid and a pad, the fine grid is an aluminum conductor, the main grid includes a first silver conductive part, and/or the pad includes a second silver conductive part.

Optionally, the second electrode is a composite fine grid, the composite fine grid includes an aluminum fine grid and a silver fine grid, and the silver fine grid is arranged on one side of the aluminum fine grid away from the P-type silicon wafer.

Optionally, the silver fine grid covers the top surface and the side surfaces of the aluminum fine grid.

Optionally, the difference between the width of the silver fine grid and the width of the aluminum fine grid is 5 μm to 20 μm.

Optionally, the silver fine grid has a thickness of 5 μm to 10 μm.

Optionally, the sum of the thicknesses of the aluminum fine gate and the aluminum doped layer and the aluminum-silicon alloy layer is 10 μm to 40 μm.

Optionally, the aluminum fine grid width is 30 μm to 80 μm.

Optionally, the width of the grooved region is 10 μm to 35 μm.

Optionally, the width of the recessed region is greater than the width of the grooved region.

Optionally, a width of the aluminum-silicon alloy layer is greater than a width of the trenched region, and the aluminum-silicon alloy layer is locally covered with the second passivation layer.

Optionally, a ratio of a surface area of the recessed region to a projected area in a thickness direction is greater than 1.05.

Optionally, the invagination depth of the invagination region is greater than 3 μm.

In a second aspect, the present application provides a cell module comprising the P-type solar cell of any of the above.

In a third aspect, the present application provides a photovoltaic system including the above-described cell assembly.

The application provides a P type solar cell, battery pack and photovoltaic system because first face is equipped with the doping polycrystalline silicon layer, and the second face is equipped with the aluminium oxide layer, so the P type solar cell who makes can two-sided antiradiation to reduce the decay that the radiation leads to. Meanwhile, the P-type solar cell is low in cost and high in photoelectric conversion efficiency.

Drawings

Fig. 1 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a P-type solar cell according to an embodiment of the present application;

fig. 3 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present application;

fig. 4 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present application;

fig. 5 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present application;

fig. 6 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present application;

fig. 7 is a schematic flow chart illustrating a method for manufacturing a P-type solar cell according to an embodiment of the present application;

FIG. 8 is a schematic structural diagram of a P-type solar cell according to an embodiment of the present application;

description of the main element symbols:

the solar cell comprises a P-type solar cell 10, a P-type silicon wafer 101, an inner sunken region 1011, a tunneling oxide layer 11, a doped polycrystalline silicon layer 12, a first passivation layer 13, a first electrode 14, an aluminum oxide layer 15, a second passivation layer 16, a second electrode 17, an aluminum fine grid 171, a silver fine grid 172, an aluminum doped layer 181 and an aluminum-silicon alloy layer 182.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The anti-radiation effect of the solar cell in the related technology is poor, and the P-type solar cell can resist radiation on two sides because the first surface of the P-type silicon wafer is provided with the doped polycrystalline silicon layer and the second surface is provided with the alumina layer, so that the attenuation caused by radiation is reduced. Meanwhile, the P-type solar cell is low in cost and high in photoelectric conversion efficiency.

Example one

Referring to fig. 1 and fig. 2, a method for manufacturing a P-type solar cell 10 of the present embodiment includes:

step S11: providing a P-type silicon wafer 101;

step S12: etching and cleaning the P-type silicon wafer 101;

step S13: preparing a tunneling oxide layer 11 on a first surface of a P-type silicon wafer 101;

step S14: preparing a doped polycrystalline silicon layer 12 on the tunneling oxide layer 11;

step S17: preparing an alumina layer 15 on the second surface of the P-type silicon wafer 101;

step S18: preparing a first passivation layer 13 on the doped polysilicon layer 12;

step S19: preparing a second passivation layer 16 on the alumina layer 15;

step S20: performing laser grooving on the second surface of the P-type silicon wafer 101;

step S21: forming a first electrode 14 on the first surface by using silver paste, wherein the first electrode 14 contacts the doped polycrystalline silicon layer 12 through the first passivation layer 13;

step S22: forming a sunken area 1011 on the second surface of the P-type silicon wafer 101 by etching;

step S23: and forming a second electrode 17 in the recessed region by using an aluminum paste, forming an aluminum doped layer 181 on the surface of the recessed region 1011 through the grooved region of the second electrode 17, and filling the recessed region 1011 with an aluminum-silicon alloy layer 182.

In the method for manufacturing the P-type solar cell 10 according to the embodiment of the present application, the doped polysilicon layer 12 is disposed on the first surface, and the aluminum oxide layer 15 is disposed on the second surface, so that the manufactured P-type solar cell 10 can resist radiation on both surfaces, thereby reducing attenuation caused by radiation. Meanwhile, the P-type solar cell 10 manufactured in this way is low in cost and high in photoelectric conversion efficiency.

Specifically, in step S12, the first side may be planarized by etching cleaning, so that the doped polysilicon layer 12 is passivated well. The texture surface can also be etched and cleaned, so that the light trapping effect is realized, the reflection loss of sunlight is reduced, and the light facing surface can be a first surface and/or a second surface.

Specifically, in step S13, the oxide layer 11 may be formed by thermal oxidation, chemical oxidation, PECVD, ALD, or the like. The thickness of the tunneling oxide layer 11 is 0.5nm-5nm. For example, 0.5nm, 1nm, 3nm, 4nm, 5nm. The thickness of the tunnel oxide layer 11 is preferably 0.7nm to 1.5nm. For example, 0.7nm, 1nm, 1.2nm, 1.5nm.

Specifically, in step S13, the tunnel oxide layer 11 includes one or more of a silicon oxide layer and an aluminum oxide layer. Preferably, the tunnel oxide layer 11 is a silicon oxide layer.

Further, the tunnel oxide layer 11 may be prepared by thermal oxidation and solution oxidation. Further, in the case of preparing the tunnel oxide layer 11 by thermal oxidation, oxygen and nitrogen may be introduced at 500 to 800 ℃ to perform thermal oxidation for 5 to 60min, thereby forming a silicon oxide layer on the P-type silicon wafer 101. In the case of preparing the tunnel oxide layer 11 by solution oxidation, H in a solution ratio of 4 ₂ SO ₄ And H ₂ O ₂ The mixed solution of the solutions is subjected to oxidation preparation, thereby forming a silicon oxide layer on the P-type silicon wafer 101.

Further, the tunnel oxide layer 11 may also be prepared by PECVD.

Specifically, in step S14, the doped polysilicon layer 12 has a thickness of 20nm to 400nm. For example, 20nm, 50nm, 100nm, 300nm, 400nm. The doped polysilicon layer 12 is preferably 80nm to 180nm thick. For example, 80nm, 100nm, 120nm, 150nm, 180nm.

Specifically, in step S14, the entire tunneling layer may be covered with the doped polysilicon layer 12, and the first electrode 14 burns through the first passivation layer 13 to contact the doped polysilicon layer 12 when the P-type silicon wafer 101 is sintered. Thus, the doped polysilicon layer 12 is covered on the whole surface, and the electrode does not penetrate through, so that the radiation resistance effect is better. Moreover, since the first electrode 14 is in contact with the polysilicon, the passivation effect is better.

It is understood that in other embodiments, the doped polysilicon layer 12 may also be covered in a partial region of the tunneling layer.

Specifically, in step S14, the doped polysilicon layer 12 may be a phosphorus-doped monocrystalline silicon layer with a sheet resistance <60ohm/squ. In this manner, a smaller number of first electrodes 14 may be used, thereby saving cost.

Specifically, in step S14, the doped polysilicon layer 12 may be prepared on the tunnel oxide layer 11 by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) apparatus, an LPCVD (Low Pressure Chemical Vapor Deposition) apparatus, or a PVD (Physical Vapor Deposition) apparatus. Therefore, the temperature required by the PECVD equipment for deposition is lower, energy can be saved, and the minority carrier lifetime attenuation in the silicon wafer caused by high temperature can be reduced. The LPCVD equipment has better step coverage capability and higher deposition rate and output. PVD is chain transmission, so that the yield is higher and the cost is lower when a thin film is deposited. Thus, the quality of the battery is improved, and the cost is reduced.

Specifically, in step S17, the alumina layer 15 is 1nm to 30nm thick. For example, 1nm, 2nm, 10nm, 15nm, 28nm, 30nm. The alumina layer 15 preferably has a thickness of 2nm to 6nm. For example, 2nm, 3nm, 4nm, 5nm, and 6nm.

Specifically, in step S17, the aluminum oxide Layer 15 may be prepared on the second side of the P-type silicon wafer 101 using a PECVD apparatus, an ALD (Atomic Layer Deposition) apparatus, or a PVD apparatus. Therefore, the temperature required by the deposition by adopting the PECVD equipment is lower, energy can be saved, and the minority carrier lifetime attenuation in the silicon wafer caused by high temperature can be reduced. The film layer manufactured by the ALD device is good in uniformity, compact and free of holes, and the thickness of the film is accurately controlled. Thus, the quality of the battery is improved, and the cost is reduced.

Note that step S18 may be before or after step S17. The flow in the figures is merely an example and is not a limitation on the order of the steps. The order of the steps can be scrambled in a rational manner.

Specifically, in step S18, the first passivation layer 13 may be prepared by ALD, PECVD, PVD, or the like. The thickness of the first passivation layer 13 is 10nm to 200nm. For example, 10nm, 50nm, 100nm, 150nm, 200nm. The thickness of the first passivation layer 13 is preferably 50nm to 100nm. For example, 50nm, 60nm, 80nm, 100nm.

Specifically, in step S18, the first passivation layer 13 includes a first silicon nitride layer, and step S18 includes: a first silicon nitride layer is prepared on the doped polysilicon layer 12 using PECVD equipment.

Specifically, in step S19, the second passivation layer 16 may be prepared by ALD, PECVD, PVD, or the like. The thickness of the second passivation layer 16 is 10nm to 200nm. For example, 10nm, 50nm, 100nm, 150nm, 200nm. Preferably 50nm to 100nm. For example, 50nm, 60nm, 80nm, 100nm.

Specifically, in step S19, the second passivation layer 16 includes a second silicon nitride layer, and step S19 includes: a second silicon nitride layer is prepared on the aluminum oxide layer 15 using a PECVD apparatus.

Therefore, the silicon nitride layer is used for antireflection, so that the loss of sunlight can be reduced, the utilization rate of the sunlight is improved, and the photoelectric conversion efficiency is improved. Meanwhile, hydrogen ions can be combined with dangling bonds, recombination centers are reduced, and a passivation effect is achieved. Moreover, the PECVD equipment ensures that the silicon nitride layer has fewer pinholes and is not easy to crack, thereby being beneficial to improving the film forming quality of the silicon nitride layer.

Further, the silicon nitride layer may be one or more layers. In the case where the silicon nitride layers are multilayered, a refractive index gradient may be formed between adjacent two silicon nitride layers. Thus, gradient extinction is realized through the refractive index gradient, and the utilization rate of sunlight is further improved.

Specifically, in step S20, a laser may be used to open dot-shaped holes on the second passivation layer and the aluminum oxide layer of the P-type silicon wafer 101. Further, the diameter of the dot-shaped holes is 25 μm to 45 μm. For example, 25 μm, 27 μm, 30 μm, 32 μm, 35 μm, 40 μm, and 45 μm. Further, the distance between the adjacent dot-shaped holes in the length direction of the fine grid is 400-800 μm. For example, 400 μm, 420 μm, 500 μm, 600 μm, 700 μm, 780 μm, 800 μm. Further, the interval between the adjacent dot-shaped holes in the width direction of the fine gate is 500 μm to 1000 μm. For example, 500. Mu.m, 520. Mu.m, 600. Mu.m, 800. Mu.m, 980. Mu.m, 1000. Mu.m.

Specifically, in step S20, a laser may be used to open discontinuous linear grooves in the second passivation layer and the aluminum oxide layer of the P-type silicon wafer 101. Further, the length of the linear groove is 0.1mm-0.5mm. For example, 0.1mm, 0.2mm, 0.3mm, 0.4mm, 0.5mm. Further, the width of the linear groove is 25 μm to 45 μm. For example, 25 μm, 28 μm, 30 μm, 35 μm, 38 μm, 40 μm, and 45 μm. Further, the distance between the adjacent linear grooves in the length direction of the fine grid is 0.2mm-1mm. For example, 0.2mm, 0.4mm, 0.8mm, 1mm. Further, the distance between the adjacent linear grooves in the width direction of the fine grid is 0.5mm-1mm. For example, 0.5mm, 0.6mm, 0.8mm, 1mm.

Specifically, in step S20, a continuous linear groove may be opened in the second passivation layer and the aluminum oxide layer of the P-type silicon wafer 101 by using a laser. Specifically, the width of the groove is 2 μm to 100 μm. For example, 2 μm, 5 μm, 8 μm, 15 μm, 30 μm, 70 μm, 100 μm. Preferably, the width of the grooved region is 10 μm to 35 μm. For example, 10 μm, 12 μm, 15 μm, 20 μm, 28 μm, 30 μm, 35 μm.

Specifically, in step S21, the first electrode 14 may be formed using screen printing. Therefore, the efficiency and the precision of electrode manufacturing are higher, and the quality of the battery is improved. In other embodiments, the first electrode 14 can be formed by electroplating copper, sputtering, vacuum evaporation, or the like.

Specifically, in step S21, the width of the first electrode 14 is 2 μm to 400 μm. For example, 2 μm, 10 μm, 100 μm, 300 μm, 400 μm. The width of the first electrode 14 is preferably 10 μm to 70 μm. For example, 10 μm, 20 μm, 50 μm, 65 μm, 70 μm.

Specifically, in step S21, the thickness of the first electrode 14 is 2 μm to 40 μm. For example, 2 μm, 10 μm, 15 μm, 30 μm, and 40 μm. The thickness of the first electrode 14 is preferably 5 μm to 20 μm. For example, 5 μm, 10 μm, 15 μm, and 20 μm.

Specifically, in step S23, the second electrode 17 may be formed by screen printing. Therefore, the efficiency and the precision of electrode manufacturing are higher, and the quality of the battery is improved. In other embodiments, the second electrode 17 may be formed by electroplating copper, sputtering, vacuum evaporation, or the like.

Specifically, in step S23, the width of the second electrode 17 is 2 μm to 400 μm. For example, 2 μm, 10 μm, 100 μm, 300 μm, 400 μm. The width of the second electrode 17 is preferably 10 μm to 70 μm. For example, 10 μm, 20 μm, 50 μm, 65 μm, and 70 μm.

Specifically, in step S23, the thickness of the second electrode 17 is 2 μm to 40 μm. For example, 2 μm, 10 μm, 15 μm, 30 μm, and 40 μm. The thickness of the second electrode 17 is preferably 5 μm to 20 μm. For example, 5 μm, 10 μm, 15 μm, and 20 μm.

Specifically, in step S23, the aluminum doped layer 181 is an aluminum-doped single crystal silicon layer, and forms a P + surface field. The aluminum silicon alloy layer 182 is located between the aluminum doped layer 181 and the second electrode 17. In this way, the contact of the P + surface field with the second electrode 17 is achieved through the aluminum-silicon alloy layer 182.

Specifically, an aluminum doped layer 181 is formed on the surface of the recess region 1011, and the aluminum-silicon alloy layer 182 fills the recess region 1011. Thus, the contact area between the aluminum doped layer 181 and the aluminum-silicon alloy layer 182 can be effectively increased, and the extended electrode and the surface contact resistance of the body region can be reduced, thereby alleviating the contradiction between the light shielding area of the electrode and the resistance.

It is understood that the second electrode 17 contacts the P-type silicon wafer 101 through the conductive contact layer 18 of the P-type solar cell 10. The conductive contact layer 18 comprises an aluminium doped layer 181 and an aluminium-silicon alloy layer 182.

It is understood that the first electrode 14 and the second electrode 17 may be formed by sintering after the slurry is applied.

Referring to fig. 3, optionally, after step S14 and before step S17, the manufacturing method includes:

step S15: and etching the P-type silicon wafer 101 with the doped polycrystalline silicon layer 12, and removing the doped polycrystalline silicon layer 12 on the side surface and the second surface of the P-type silicon wafer 101.

Thus, the doped polysilicon layer 12 generated by the electroplating process is removed, and the preparation of the aluminum oxide layer 15 is prevented from being influenced. Note that there is generally no wraparound phenomenon when the doped polysilicon is prepared using PECVD equipment. In the preparation of doped polysilicon using LPCVD equipment, there is generally a phenomenon of strike-through.

Specifically, the doped polysilicon layer 12 may be dry etched, or the doped polysilicon layer 12 may be wet etched. Further, the doped polysilicon layer 12 may be etched by an acidic solution.

Referring to fig. 4, optionally, step S12 includes:

step S121: etching the P-type silicon wafer 101, and removing a damaged layer of the P-type silicon wafer 101;

step S122: cleaning the P-type silicon wafer 101;

after step S15, the manufacturing method includes:

step S16: and texturing the second surface of the P-type silicon wafer 101.

Therefore, the damaged layer is removed firstly, and then the doped polycrystalline silicon generated by the winding plating is removed for texturing, so that the waste can be avoided, and the efficiency is improved. It will be appreciated that if the texturing is done prior to removal of the doped polysilicon produced by the blanket plating, the texturing is likely to be etched together with the removal of the doped polysilicon produced by the blanket plating, resulting in inefficiencies.

Specifically, in step S121, the P-type silicon wafer 101 may be etched by using an acidic solution to remove a damaged layer of the P-type silicon wafer 101. Further, the acidic solution may be HF and HNO ₃ The solution was mixed.

Specifically, in step S122, the P-type silicon wafer 101 may be cleaned with clean water. Further, the P-type silicon wafer 101 can be washed by clear water; the P-type silicon wafer 101 may also be immersed in clear water.

Specifically, in step S16, the second surface of the P-type silicon wafer 101 may be texturized using an alkaline solution. Further, the alkaline solution may be KOH or NaOH solution.

Referring to fig. 5, optionally, step S12 includes:

step S123: etching the P-type silicon wafer 101, removing the damage layer of the P-type silicon wafer 101 and forming a textured surface on the second surface;

step S124: and cleaning the P-type silicon wafer 101.

Therefore, the suede is formed while the damage layer is removed, two steps are not needed, and the manufacturing efficiency can be improved. It will be appreciated that this is the case without the wraparound plating, without the need to remove the doped polysilicon produced by the wraparound plating.

Specifically, in step S123, the P-type silicon wafer 101 may be etched using an alkaline solution and the second side of the P-type silicon wafer 101 may be textured. Further, the alkaline solution may be a KOH or NaOH solution.

Specifically, in step S124, the P-type silicon wafer 101 may be cleaned with clean water. Further, the P-type silicon wafer 101 may be rinsed with clear water; the P-type silicon wafer 101 may also be immersed in clear water.

Referring to fig. 6, optionally, the second electrode 17 includes a fine grid, a main grid and a pad, the fine grid is an aluminum conductor, and the step S23 includes:

step S231: forming an aluminum conductor in the sunken area by using aluminum paste;

step S232: a main grid and a bonding pad are formed on the aluminum conductor, the main grid including a first silver conductive portion, and/or the bonding pad including a second silver conductive portion.

In this manner, at least one of the main grid and the bonding pad includes a silver conductive portion to facilitate soldering when manufacturing the battery assembly.

Specifically, in step S231, an aluminum conductor may be formed by screen printing; the aluminum conductor can also be formed by sputtering, vacuum evaporation and other processes.

Specifically, in step S232, the master gate includes a first silver conductive portion, and the pad includes a second silver conductive portion; the main grid can also comprise a first silver conductive part, and the pad does not comprise a second silver conductive part; it is also possible that the main gate does not include a first silver conductive portion and the pad includes a second silver conductive portion. Further, in the case where the main grid includes the first silver conductive portion, a portion of the main grid may be the first silver conductive portion, or the entire main grid may be the first silver conductive portion. When the bonding pad includes the second silver conductive portion, a portion which can be bonded may be the second silver conductive portion, or the entire bonding pad may be the second silver conductive portion.

Specifically, in step S232, the silver conductive portion may be formed by screen printing; the silver conductive portion may be formed by sputtering, vacuum evaporation, or the like.

Referring to fig. 7 and 8, optionally, the second electrode 17 includes an aluminum fine grid 171 and a silver fine grid 172, and step S23 includes:

step S233: forming an aluminum fine grid 171 in the recessed area by using aluminum paste;

step S234: a silver fine grid 172 is formed on the aluminum fine grid 171, and the aluminum fine grid 171 and the silver fine grid 172 are formed as a composite fine grid.

In this way, ohmic contact is formed by autodoping of the aluminum fine grid 171, and current is efficiently drawn out by the strong conductivity of the silver fine grid 172. Also, since the aluminum fine grid 171 serves as a contact electrode, the thickness of the silver fine grid 172 can be thinner. Therefore, the composite fine grid has low cost and simple process while the photoelectric conversion efficiency is ensured.

Specifically, in step S233, the aluminum fine grid 171 may be formed on the second face by screen printing using an aluminum paste. Therefore, the efficiency and the precision of manufacturing the aluminum fine grid 171 are higher, and the quality of the battery is improved. In other embodiments, the aluminum fine grid 171 can be formed by sputtering, vacuum evaporation, or the like.

Specifically, in step S234, the silver fine grid 172 may be formed by screen printing. Therefore, the efficiency and the precision of manufacturing the silver fine grid 172 are higher, and the quality of the battery is improved. In other embodiments, the silver fine grid 172 may be formed by sputtering, vacuum evaporation, or the like.

Referring to fig. 8, optionally, step S234 includes: the silver fine grid 172 covers the top and side surfaces of the aluminum fine grid 171. In this way, the contact area between the silver fine grids 172 and the aluminum fine grids 171 is large, so that the conductive effect between the silver fine grids 172 and the aluminum fine grids 171 is better.

It is understood that in other embodiments, the silver fine grid 172 covers only the top surface of the aluminum fine grid 171, and does not cover the side surface of the aluminum fine grid 171; the silver fine grids 172 may cover only the side surfaces of the aluminum fine grids 171 without covering the top surfaces of the aluminum fine grids 171.

Specifically, the silver fine grid 172 entirely covers the top surface of the aluminum fine grid 171, and entirely covers the side surfaces of the aluminum fine grid 171. In this way, the contact area between the silver fine grid 172 and the aluminum fine grid 171 is larger, so that the electric conduction effect between the silver fine grid 172 and the aluminum fine grid 171 is better.

It is understood that in other embodiments, the silver fine grid 172 may cover a partial area of the top surface of the aluminum fine grid 171; the silver fine grid 172 may cover a partial area of the side surface of the aluminum fine grid 171. For example, the silver fine grid 172 may form a hollowed-out region.

Alternatively, the aluminum fine grid 171 is covered to a thickness less than 1/2 of the thickness of the silver fine grid 172. The aluminum fine grids 171 are covered to a thickness of, for example, 1/3, 1/4, 1/5, 1/6 of the thickness of the silver fine grids 172. Therefore, the thickness ratio of the silver fine grid 172 to the aluminum fine grid 171 is in a proper range, so that poor overall conductivity caused by too small thickness ratio can be avoided, and too high cost caused by too large thickness ratio can also be avoided.

Alternatively, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is 5 μm to 20 μm. For example, 5 μm, 6 μm, 10 μm, 15 μm, 20 μm. Therefore, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is within a proper range, the silver fine grid 172 covered on the side surface of the aluminum fine grid 171 due to too small width difference can be prevented from being thin, the poor conducting effect can be avoided, the silver fine grid 172 covered on the side surface of the aluminum fine grid 171 due to too large width difference can be prevented from being thick, and the high cost can be avoided.

Optionally, the silver fine grid 172 is 5 μm to 10 μm thick. For example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. Therefore, the thickness of the silver fine grid 172 is in a proper range, poor conducting effect caused by too small thickness of the silver fine grid 172 can be avoided, and high cost caused by too large thickness of the silver fine grid 172 can also be avoided.

Alternatively, the sum of the thicknesses of the aluminum fine gate 171, the aluminum doped layer 181, and the aluminum-silicon alloy layer 182 is 10 μm to 40 μm. For example, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 40 μm. Therefore, the sum of the thicknesses is in a proper range, so that the ohmic contact formed by self-doping of the aluminum fine grid 171 is better, and the current is led out efficiently.

Alternatively, the aluminum fine grid 171 is 30 μm-80 μm wide. For example, 30 μm, 40 μm, 50 μm, 70 μm, 80 μm. Thus, the width of the aluminum fine grid 171 is in a proper range, which is beneficial to efficiently leading out the current.

Optionally, the width of the invaginated region 1011 is greater than the width of the grooved region. Optionally, the width of the aluminum-silicon alloy layer 182 is greater than the width of the trenched region, and the aluminum-silicon alloy layer 182 is locally covered with the second passivation layer 16. Thus, a larger invagination region 1011 can be formed by a narrower slotting region, so that the contact area of the aluminum doping layer 181 and the silicon wafer is larger, the contact area of the aluminum doping layer 181 and the aluminum-silicon alloy layer 182 is larger, the expanded electrode and the surface contact resistance of the body region can be reduced, and the contradiction between the light shielding area of the electrode and the resistance is relieved.

Optionally, the ratio of the surface area of the invaginated region 1011 to the projected area in the thickness direction is greater than 1.05. Thus, the recessed region 1011 is made larger, the contact area between the aluminum doped layer 181 and the silicon wafer is made larger, the contact area between the aluminum doped layer 181 and the aluminum-silicon alloy layer 182 is made larger, the extended electrode and the surface contact resistance of the body region can be reduced, and the contradiction between the light shielding area of the electrode and the resistance is relieved.

Optionally, the invagination region 1011 has an invagination depth of greater than 3 μm. For example, 3 μm, 4 μm, 5 μm, and 6 μm. Thus, the surface area of the invaginated region 1011 is increased by making the invagination depth large.

In the related art, the front emitter reverse dark saturation current density (J0) of the PERC cell is 20fA/cm ² The contact area J0 is 600fA/cm ² The back non-contact area J0 is 3fA/cm ² The contact area J0 is 500fA/cm ² . The front emitter J0 of the Topcont cell was 10fA/cm ² The contact area J0 is 800fA/cm ² The back non-contact area J0 is 2fA/cm ² The contact area J0 is 50fA/cm ² 。

In the P-type solar cell 10 manufactured by the method for manufacturing the P-type solar cell 10 of the present embodiment, the first surface J0 is 2fA/cm ² The contact area J0 is 50fA/cm ² The non-contact area J0 of the second surface is 2fA/cm ² The contact area J0 is 500fA/cm ² 。

If the contact area ratio is 2%, the J0 of the PERC cell in the related art is 43.54fA/cm ² . The method of manufacturing P-type solar cell 10 of this example produces P-type solar cell 10 with J0 of 14.92fA/cm ² . Obviously, the P-type solar cell 10 manufactured by the method for manufacturing the P-type solar cell 10 of the present embodiment has better electrical properties.

For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.

Example two

The P-type solar cell 10 of the present embodiment is manufactured by the method for manufacturing the P-type solar cell 10 of any one of the first embodiment.

In the method for manufacturing the P-type solar cell 10 according to the embodiment of the present application, the doped polysilicon layer 12 is disposed on the first surface, and the aluminum oxide layer 15 is disposed on the second surface, so that the manufactured P-type solar cell 10 can resist radiation on both surfaces, thereby reducing attenuation caused by radiation. Meanwhile, the P-type solar cell 10 manufactured in this way is low in cost and high in photoelectric conversion efficiency.

For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.

EXAMPLE III

The P-type solar cell 10 of the present embodiment includes:

a P-type silicon wafer 101;

the tunneling oxide layer 11, the doped polysilicon layer 12, the first passivation layer 13 and the first electrode 14 are sequentially stacked on the first surface of the P-type silicon wafer 101, the first electrode 14 is a silver electrode, and the first electrode 14 penetrates through the first passivation layer 13 and is in contact with the doped polysilicon;

the aluminum oxide layer 15, the second passivation layer 16 and the second electrode 17 are sequentially stacked on the second surface of the P-type silicon wafer 101, the second electrode 17 comprises an aluminum electrode, the aluminum oxide layer 15 and the second passivation layer 16 are provided with a slotted region, the P-type silicon wafer 101 below the slotted region forms an invaginated region 1011, the second electrode 17 penetrates through the slotted region, an aluminum doped layer 181 is formed on the surface of the invaginated region 1011, and an aluminum-silicon alloy layer 182 is filled in the invaginated region 1011.

In the P-type solar cell 10 of the embodiment of the present application, since the doped polysilicon layer 12 is disposed on the first surface and the aluminum oxide layer 15 is disposed on the second surface, the manufactured P-type solar cell 10 can resist radiation on both surfaces, thereby reducing attenuation caused by radiation. Meanwhile, the P-type solar cell 10 manufactured in this way is low in cost and high in photoelectric conversion efficiency.

Optionally, the second electrode 17 comprises a fine grid, a main grid and a pad, the fine grid being an aluminum conductor, the main grid comprising a first silver conductor portion, and/or the pad comprising a second silver conductor portion.

Optionally, the second electrode 17 is a composite fine grid, the composite fine grid includes an aluminum fine grid 171 and a silver fine grid 172, and the silver fine grid 172 is disposed on a side of the aluminum fine grid 171 facing away from the P-type silicon wafer 101.

Optionally, the silver fine grid 172 covers the top and side surfaces of the aluminum fine grid 171.

Alternatively, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is 5 μm to 20 μm.

Optionally, the silver fine grid 172 is 5 μm to 10 μm thick.

Alternatively, the sum of the thicknesses of the aluminum fine gate 171 and the aluminum doped layer 181 and the aluminum-silicon alloy layer 182 is 10 μm to 40 μm.

Alternatively, the aluminum fine grid 171 is 30 μm-80 μm wide.

Optionally, the width of the grooved region is 10 μm-35 μm.

Optionally, the width of the invaginated region 1011 is greater than the width of the grooved region.

Optionally, the width of the aluminum-silicon alloy layer 182 is greater than the width of the trenched region, and the aluminum-silicon alloy layer 182 is locally covered with the second passivation layer 16.

Optionally, the ratio of the surface area of the invaginated region 1011 to the projected area in the thickness direction is greater than 1.05.

Optionally, the invagination depth of the invagination region 1011 is greater than 3 μm.

For further explanation and description of this embodiment, reference may be made to other parts of this document, especially to embodiment one, and further description is omitted here to avoid redundancy.

Example four

The cell module of the present embodiment includes the P-type solar cell 10 of the second embodiment or the third embodiment.

In the cell module of the embodiment of the present application, since the doped polysilicon layer 12 is disposed on the first surface and the aluminum oxide layer 15 is disposed on the second surface, the manufactured P-type solar cell 10 can be radiation-resistant on both surfaces, thereby reducing attenuation caused by radiation. Meanwhile, the P-type solar cell 10 manufactured in this way is low in cost and high in photoelectric conversion efficiency.

For further explanation and explanation of the embodiment, reference may be made to other parts of the text, and in order to avoid redundancy, further description is omitted here.

EXAMPLE five

The photovoltaic system of this embodiment includes the cell assembly of the fourth embodiment.

In the photovoltaic system of the embodiment of the present application, since the doped polysilicon layer 12 is disposed on the first surface and the aluminum oxide layer 15 is disposed on the second surface, the manufactured P-type solar cell 10 can resist radiation on both surfaces, thereby reducing attenuation caused by radiation. Meanwhile, the P-type solar cell 10 manufactured in this way is low in cost and high in photoelectric conversion efficiency.

In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, roof power stations, water surface power stations, etc., and can also be applied to devices or apparatuses that generate electricity by using solar energy, such as user solar power sources, solar street lamps, solar cars, solar buildings, etc. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system can be applied in all fields requiring solar energy for power generation. Taking a photovoltaic power generation system network as an example, a photovoltaic system may include a photovoltaic array, a combiner box and an inverter, the photovoltaic array may be an array combination of a plurality of battery modules, for example, the plurality of battery modules may constitute a plurality of photovoltaic arrays, the photovoltaic array is connected to the combiner box, the combiner box may combine currents generated by the photovoltaic array, and the combined currents are converted into alternating currents required by a utility grid through the inverter and then are connected to the utility grid to realize solar power supply.

For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.

The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed. Furthermore, the particular features, structures, materials, or characteristics described in connection with the embodiments or examples disclosed herein may be combined in any suitable manner in any one or more of the embodiments or examples.

Claims (15)

1. A P-type solar cell, comprising:

a P-type silicon wafer;

the tunneling oxide layer, the doped polycrystalline silicon layer, the first passivation layer and the first electrode are sequentially stacked on the first surface of the P-type silicon wafer, the first electrode is a silver electrode, and the first electrode penetrates through the first passivation layer to be in contact with the doped polycrystalline silicon;

the aluminum oxide layer, the second passivation layer and the second electrode are sequentially stacked on the second surface of the P-type silicon wafer, the second electrode comprises an aluminum electrode, the aluminum oxide layer and the second passivation layer are provided with a slotted region, the P-type silicon wafer below the slotted region forms an invaginated region, the second electrode penetrates through the slotted region, an aluminum doped layer is formed on the surface of the invaginated region, and an aluminum-silicon alloy layer is filled in the invaginated region.

2. The P-type solar cell according to claim 1, wherein the second electrode comprises a fine grid, a main grid and a pad, the fine grid is an aluminum conductor, the main grid comprises a first silver conductor part, and/or the pad comprises a second silver conductor part.

3. The P-type solar cell according to claim 1, wherein the second electrode is a composite fine grid, the composite fine grid comprises an aluminum fine grid and a silver fine grid, and the silver fine grid is arranged on one side of the aluminum fine grid, which faces away from the P-type silicon wafer.

4. The P-type solar cell according to claim 3, wherein the silver fine grid covers the top and side surfaces of the aluminum fine grid.

5. The P-type solar cell according to claim 3, wherein the difference between the width of the silver fine grid and the width of the aluminum fine grid is 5 μm to 20 μm.

6. The P-type solar cell according to claim 3, wherein the silver fine grid has a thickness of 5 μm to 10 μm.

7. The P-type solar cell according to claim 3, wherein the sum of the thicknesses of the aluminum fine grid and the aluminum doped layer and the aluminum-silicon alloy layer is 10 μm to 40 μm.

8. The P-type solar cell according to claim 3, wherein the aluminum fine grid has a width of 30-80 μm.

9. The P-type solar cell according to claim 1, wherein the width of the grooved region is 10-35 μ ι η.

10. The P-type solar cell of claim 1, wherein the width of the recessed region is greater than the width of the grooved region.

11. The P-type solar cell according to claim 1, wherein the aluminum-silicon alloy layer has a width greater than a width of the grooved region, the aluminum-silicon alloy layer being locally covered with the second passivation layer.

12. The P-type solar cell according to claim 1, wherein a ratio of a surface area of the recessed region to a projected area in a thickness direction is greater than 1.05.

13. The P-type solar cell according to claim 1, wherein the recessed region has a recess depth of more than 3 μ ι η.

14. A cell module comprising the P-type solar cell according to any one of claims 1 to 13.

15. A photovoltaic system comprising the cell assembly of claim 14.

Images