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CN115000214B - P-type solar cell, manufacturing method thereof, cell assembly and photovoltaic system - Google Patents

P-type solar cell, manufacturing method thereof, cell assembly and photovoltaic system Download PDF

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CN115000214B
CN115000214B CN202210718401.5A CN202210718401A CN115000214B CN 115000214 B CN115000214 B CN 115000214B CN 202210718401 A CN202210718401 A CN 202210718401A CN 115000214 B CN115000214 B CN 115000214B
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aluminum
layer
silicon wafer
type silicon
fine grid
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CN115000214A (en
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王永谦
许文理
张建军
杨新强
陈刚
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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Zhejiang Aiko Solar Energy Technology Co Ltd
Guangdong Aiko Technology Co Ltd
Tianjin Aiko Solar Energy Technology Co Ltd
Zhuhai Fushan Aixu Solar Energy Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/041—Provisions for preventing damage caused by corpuscular radiation, e.g. for space applications
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
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    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
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    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
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Abstract

The application is applicable to the technical field of solar cells and provides a P-type solar cell, a manufacturing method thereof, a cell assembly and a photovoltaic system. The manufacturing method of the P-type solar cell comprises the following steps: providing a P-type silicon wafer; etching and cleaning the P-type silicon wafer; preparing a tunneling oxide layer on a first surface of a P-type silicon wafer; preparing a doped polysilicon layer on the tunneling oxide layer; preparing an alumina layer on the second surface of the P-type silicon wafer; preparing a first passivation layer on the doped polysilicon layer; preparing a second passivation layer on the aluminum oxide layer; carrying out laser grooving on the second surface of the P-type silicon wafer; forming a first electrode on the first surface by using silver paste, wherein the first electrode passes through the first passivation layer to contact the doped polysilicon layer; forming an invagination area on the second surface of the P-type silicon wafer by etching; and forming a second electrode in the invagination area by using the aluminum paste, forming an aluminum doped layer on the surface of the invagination area by the second electrode through the grooving area, and filling the invagination area with the silicon alloy layer.

Description

P-type solar cell, manufacturing method thereof, cell assembly and photovoltaic system
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a P-type solar cell, a manufacturing method thereof, a cell assembly and a photovoltaic system.
Background
Solar cell power generation is a sustainable clean energy source that uses the photovoltaic effect of semiconductor p-n junctions to convert sunlight into electrical energy.
In the related art, a silicon nitride layer is generally provided in a solar cell, or a silicon oxide layer and a silicon nitride layer are provided in a solar cell, thereby reducing reflection of sunlight. However, this results in solar cells that attenuate too much in environments where ultraviolet radiation is intense, such as in altitude, sea or space, creating a high risk of failure.
Based on this, how to improve the anti-radiation effect of the solar cell becomes a problem to be solved.
Disclosure of Invention
The application provides a P-type solar cell, a manufacturing method thereof, a cell assembly and a photovoltaic system, and aims to solve the problem of how to improve the anti-radiation effect of the solar cell.
In a first aspect, a method for manufacturing a P-type solar cell provided in the present application includes:
providing a P-type silicon wafer;
etching and cleaning the P-type silicon wafer;
preparing a tunneling oxide layer on a first surface of the P-type silicon wafer;
preparing a doped polysilicon layer on the tunneling oxide layer;
preparing an alumina layer on the second surface of the P-type silicon wafer;
preparing a first passivation layer on the doped polysilicon layer;
preparing a second passivation layer on the aluminum oxide layer;
carrying out laser grooving on the second surface of the P-type silicon wafer;
forming a first electrode on the first face using silver paste, the first electrode contacting the doped polysilicon layer through the first passivation layer;
forming an invagination area on the second surface of the P-type silicon wafer by etching;
and forming a second electrode in the invagination area by using aluminum paste, wherein the second electrode forms an aluminum doped layer on the surface of the invagination area through a grooving area and fills an aluminum-silicon alloy layer in the invagination area.
Optionally, after the step of preparing the doped polysilicon layer on the tunneling oxide layer, before the step of preparing the aluminum oxide layer on the second side of the P-type silicon wafer, the manufacturing method includes:
and etching the P-type silicon wafer on which the doped polysilicon layer is prepared, and removing the doped polysilicon layer on the second surface of the side surface of the P-type silicon wafer.
Optionally, etching and cleaning the P-type silicon wafer, including:
etching the P-type silicon wafer and removing the damaged layer of the P-type silicon wafer;
cleaning the P-type silicon wafer;
after the step of etching the P-type silicon wafer on which the doped polysilicon layer is prepared, the manufacturing method comprises the following steps:
and texturing the second surface of the P-type silicon wafer.
Optionally, etching and cleaning the P-type silicon wafer, including:
etching the P-type silicon wafer, removing the damaged layer of the P-type silicon wafer and forming a suede on the second surface;
and cleaning the P-type silicon wafer.
Optionally, preparing a doped polysilicon layer on the tunneling oxide layer, including:
and preparing the doped polysilicon layer on the tunneling oxide layer by using a PECVD device or an LPCVD device.
Optionally, the first passivation layer includes a first silicon nitride layer, and preparing the first passivation layer on the doped polysilicon layer includes:
and preparing the first silicon nitride layer on the doped polysilicon layer by using a PECVD device.
Optionally, the second passivation layer includes a second silicon nitride layer, and preparing the second passivation layer on the aluminum oxide layer includes:
and preparing the second silicon nitride layer on the aluminum oxide layer by using a PECVD device.
Optionally, the second electrode includes a fine gate, a main gate and a bonding pad, the fine gate is an aluminum conductor, the second electrode is formed on the second surface by using aluminum paste, and the method includes:
forming the aluminum conductor in the invagination structure using an aluminum paste;
the main gate and the bonding pad are formed on the aluminum conductor, the main gate including a first silver conductive portion, and/or the bonding pad including a second silver conductive portion.
Optionally, the second electrode includes an aluminum fine grid and a silver fine grid, forming the second electrode on the second face using an aluminum paste, including:
forming the aluminum fine grid on the invagination structure by using aluminum slurry;
and forming the silver fine grid on the aluminum fine grid, wherein the aluminum fine grid and the silver fine grid are formed into a composite fine grid.
Optionally, forming the silver fine grid on the aluminum fine grid includes:
and covering the top surface and the side surfaces of the aluminum fine grid with the silver fine grid.
Optionally, the thickness of the aluminum fine grid is less than 1/2 of the thickness of the silver fine grid.
Optionally, the difference between the width of the silver fine grid and the width of the aluminum fine grid is 5 μm to 20 μm.
Optionally, the silver fine grid has a thickness of 5 μm to 10 μm.
Optionally, the sum of the thicknesses of the aluminum fine gate, the aluminum doped layer and the aluminum silicon alloy layer is 10 μm to 40 μm.
Optionally, the aluminum fine gate width is 30 μm to 80 μm.
Optionally, the width of the grooved region is 10 μm-35 μm.
Optionally, the width of the recessed region is greater than the width of the slotted region.
Optionally, the width of the aluminum-silicon alloy layer is larger than the width of the slotting region, and the aluminum-silicon alloy layer is locally covered with the second passivation layer.
Optionally, the ratio of the surface area of the invaginated area to the projected area in the thickness direction is greater than 1.05.
Optionally, the invagination depth of the invagination region is greater than 3 μm.
In a second aspect, the P-type solar cell provided in the present application is manufactured by using the manufacturing method of the P-type solar cell of any one of the above.
In a third aspect, the present application provides a P-type solar cell, including:
p-type silicon wafer;
the first electrode is a silver electrode, and the first electrode passes through the first passivation layer to be in contact with the doped polysilicon;
the aluminum oxide layer, the second passivation layer and the second electrode are sequentially laminated on the second surface of the P-type silicon wafer, the second electrode comprises an aluminum electrode, a slotting area is formed on the aluminum oxide layer and the second passivation layer, an invagination area is formed on the P-type silicon wafer under the slotting area, the second electrode penetrates through the slotting area, an aluminum doping layer is formed on the surface of the invagination area, and an aluminum-silicon alloy layer is filled in the invagination area.
Optionally, the second electrode includes a fine gate, a main gate, and a bonding pad, the fine gate is an aluminum conductor, the main gate includes a first silver conductive portion, and/or the bonding pad includes a second silver conductive portion.
Optionally, the second electrode is a composite fine grid, the composite fine grid comprises an aluminum fine grid and a silver fine grid, and the silver fine grid is arranged on one side of the aluminum fine grid, which is away from the P-type silicon wafer.
Optionally, the silver fine grid covers the top surface and the side surfaces of the aluminum fine grid.
Optionally, the difference between the width of the silver fine grid and the width of the aluminum fine grid is 5 μm to 20 μm.
Optionally, the silver fine grid has a thickness of 5 μm to 10 μm.
Optionally, the sum of the thicknesses of the aluminum fine gate, the aluminum doped layer and the aluminum silicon alloy layer is 10-40 μm.
Optionally, the aluminum fine gate width is 30 μm to 80 μm.
Optionally, the width of the grooved region is 10 μm-35 μm.
Optionally, the width of the recessed region is greater than the width of the slotted region.
Optionally, the width of the aluminum-silicon alloy layer is larger than the width of the slotting region, and the aluminum-silicon alloy layer is locally covered with the second passivation layer.
Optionally, the ratio of the surface area of the invaginated area to the projected area in the thickness direction is greater than 1.05.
Optionally, the invagination depth of the invagination region is greater than 3 μm.
In a third aspect, the present application provides a cell assembly comprising a P-type solar cell according to any one of the above.
In a fourth aspect, the present application provides a photovoltaic system comprising the above-described cell assembly.
According to the P-type solar cell, the manufacturing method thereof, the cell assembly and the photovoltaic system, as the doped polycrystalline silicon layer is arranged on the first surface, and the aluminum oxide layer is arranged on the second surface, the manufactured P-type solar cell can resist radiation on two sides, and therefore attenuation caused by radiation is reduced. Meanwhile, the cost for manufacturing the P-type solar cell is low, and the photoelectric conversion efficiency is high.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a P-type solar cell according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a P-type solar cell according to an embodiment of the present application;
FIG. 3 is a flow chart of a method for fabricating a P-type solar cell according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of a method for fabricating a P-type solar cell according to an embodiment of the present disclosure;
FIG. 5 is a flow chart of a method for fabricating a P-type solar cell according to an embodiment of the present disclosure;
FIG. 6 is a flow chart of a method for fabricating a P-type solar cell according to an embodiment of the present disclosure;
fig. 7 is a flow chart of a method for fabricating a P-type solar cell according to an embodiment of the disclosure;
fig. 8 is a schematic structural diagram of a P-type solar cell according to an embodiment of the present application;
description of main reference numerals:
the solar cell comprises a P-type solar cell 10, a P-type silicon wafer 101, an invagination region 1011, a tunneling oxide layer 11, a doped polysilicon layer 12, a first passivation layer 13, a first electrode 14, an aluminum oxide layer 15, a second passivation layer 16, a second electrode 17, an aluminum fine gate 171, a silver fine gate 172, an aluminum doped layer 181 and an aluminum silicon alloy layer 182.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
In the related art, the solar cell has poor anti-radiation effect, and the P-type solar cell can resist radiation on two sides because the doped polysilicon layer is arranged on the first surface of the P-type silicon wafer and the aluminum oxide layer is arranged on the second surface of the P-type silicon wafer, so that attenuation caused by radiation is reduced. Meanwhile, the cost for manufacturing the P-type solar cell is low, and the photoelectric conversion efficiency is high.
Example 1
Referring to fig. 1 and 2, the method for manufacturing a P-type solar cell 10 of the present embodiment includes:
step S11: providing a P-type silicon wafer 101;
step S12: etching and cleaning the P-type silicon wafer 101;
step S13: preparing a tunneling oxide layer 11 on a first surface of a P-type silicon wafer 101;
step S14: preparing a doped polysilicon layer 12 on the tunneling oxide layer 11;
step S17: preparing an alumina layer 15 on the second surface of the P-type silicon wafer 101;
step S18: preparing a first passivation layer 13 on the doped polysilicon layer 12;
step S19: preparing a second passivation layer 16 on the alumina layer 15;
step S20: laser grooving is carried out on the second surface of the P-type silicon wafer 101;
step S21: forming a first electrode 14 on the first surface using silver paste, the first electrode 14 contacting the doped polysilicon layer 12 through the first passivation layer 13;
step S22: forming an invagination region 1011 on the second surface of the P-type silicon wafer 101 by etching;
step S23: the second electrode 17 is formed in the recess region using aluminum paste, the second electrode 17 forms an aluminum doped layer 181 on the surface of the recess region 1011 through the grooved region and fills the recess region 1011 with an aluminum silicon alloy layer 182.
According to the manufacturing method of the P-type solar cell 10, the doped polysilicon layer 12 is arranged on the first surface, and the aluminum oxide layer 15 is arranged on the second surface, so that the manufactured P-type solar cell 10 can resist radiation on both sides, and attenuation caused by radiation is reduced. Meanwhile, the cost of manufacturing the P-type solar cell 10 is low, and the photoelectric conversion efficiency is high.
Specifically, in step S12, the first surface may be flattened by etching and cleaning, so that passivation of the doped polysilicon layer 12 is better. The light-trapping effect can be realized by etching and cleaning the light-directing surface, so that the reflection loss of sunlight is reduced, and the light-directing surface can be the first surface and/or the second surface.
Specifically, in step S13, the tunnel oxide layer 11 may be formed by thermal oxidation, chemical oxidation, PECVD, ALD, or the like. The thickness of the tunnel oxide layer 11 is 0.5nm-5nm. For example, 0.5nm, 1nm, 3nm, 4nm, 5nm. The thickness of the tunnel oxide layer 11 is preferably 0.7nm to 1.5nm. For example, 0.7nm, 1nm, 1.2nm, 1.5nm.
Specifically, in step S13, the tunnel oxide layer 11 includes one or more of a silicon oxide layer and an aluminum oxide layer. Preferably, the tunnel oxide layer 11 is a silicon oxide layer.
Further, the tunnel oxide layer 11 may be prepared by thermal oxidation and solution oxidation. Further, in the case of preparing the tunnel oxide layer 11 by thermal oxidation, oxygen and nitrogen may be introduced at 500-800 ℃ to perform thermal oxidation for 5-60min, thereby forming a silicon oxide layer on the P-type silicon wafer 101. In the case of preparing the tunnel oxide layer 11 by solution oxidation, H may be used in a solution ratio of 4:1 to 1:4 2 SO 4 And H is 2 O 2 The mixed solution of the solutions is prepared by oxidation, thereby forming a silicon oxide layer on the P-type silicon wafer 101.
Further, the tunnel oxide layer 11 may also be prepared by PECVD.
Specifically, in step S14, the doped polysilicon layer 12 has a thickness of 20nm to 400nm. For example, 20nm, 50nm, 100nm, 300nm, 400nm. The doped polysilicon layer 12 preferably has a thickness of 80nm to 180nm. For example 80nm, 100nm, 120nm, 150nm, 180nm.
Specifically, in step S14, the doped polysilicon layer 12 may be covered on the entire surface of the tunneling layer, and the first electrode 14 burns through the first passivation layer 13 to contact the doped polysilicon layer 12 when sintering the P-type silicon wafer 101. Thus, the doped polysilicon layer 12 covers the whole surface, and the electrode does not pass through, so the radiation-resistant effect is better. Further, since the first electrode 14 is in contact with the polysilicon, the passivation effect is better.
It will be appreciated that in other embodiments, the doped polysilicon layer 12 may also be overlaid on a partial region of the tunneling layer.
Specifically, in step S14, the doped polysilicon layer 12 may be a phosphorus doped monocrystalline silicon layer with a sheet resistance <60ohm/squ. In this way, a smaller number of first electrodes 14 may be used, thereby saving costs.
Specifically, in step S14, the doped polysilicon layer 12 may be prepared on the tunnel oxide layer 11 using a PECVD (Plasma Enhanced Chemical Vapor Deposition ) apparatus, an LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition) apparatus, or a PVD (Physical Vapor Deposition ) apparatus. Therefore, the temperature required by deposition by adopting PECVD equipment is lower, so that energy sources can be saved, and minority carrier lifetime attenuation in the silicon wafer caused by high temperature can be reduced. The LPCVD equipment has better step coverage capability and higher deposition rate and output. While PVD is chain transfer, the productivity is higher and the cost is lower when depositing thin films. Thus, the quality of the battery is advantageously improved and the cost is reduced.
Specifically, in step S17, the thickness of the alumina layer 15 is 1nm to 30nm. For example, 1nm, 2nm, 10nm, 15nm, 28nm, 30nm. The thickness of the alumina layer 15 is preferably 2nm to 6nm. For example, 2nm, 3, 4nm, 5nm, 6nm.
Specifically, in step S17, the aluminum oxide layer 15 may be prepared on the second side of the P-type silicon wafer 101 using a PECVD apparatus, an ALD (Atomic Layer Deposition ) apparatus or a PVD apparatus. Therefore, the temperature required by deposition by adopting PECVD equipment is lower, so that energy sources can be saved, and minority carrier lifetime attenuation in the silicon wafer caused by high temperature can be reduced. The film layer manufactured by the ALD equipment is good in uniformity, compact and free of holes, and the thickness of the film is accurately controlled. Thus, the quality of the battery is advantageously improved and the cost is reduced.
Note that step S18 may precede or follow step S17. The flow in the drawings is merely an example and is not a limitation of the order of the steps. The order of the steps may be disturbed in a reasonable manner.
Specifically, in step S18, the first passivation layer 13 may be prepared by an ALD, PECVD, PVD or the like process. The thickness of the first passivation layer 13 is 10nm to 200nm. For example, 10nm, 50nm, 100nm, 150nm, 200nm. The thickness of the first passivation layer 13 is preferably 50nm to 100nm. For example 50nm, 60nm, 80nm, 100nm.
Specifically, in step S18, the first passivation layer 13 includes a first silicon nitride layer, and step S18 includes: a first silicon nitride layer is prepared on the doped polysilicon layer 12 using a PECVD apparatus.
Specifically, in step S19, the second passivation layer 16 may be prepared by an ALD, PECVD, PVD or the like process. The thickness of the second passivation layer 16 is 10nm-200nm. For example, 10nm, 50nm, 100nm, 150nm, 200nm. Preferably 50nm to 100nm. For example 50nm, 60nm, 80nm, 100nm.
Specifically, in step S19, the second passivation layer 16 includes a second silicon nitride layer, and step S19 includes: a second silicon nitride layer was prepared on the aluminum oxide layer 15 using a PECVD apparatus.
Thus, the silicon nitride layer is used for antireflection, so that the loss of sunlight can be reduced, the utilization rate of the sunlight can be improved, and the photoelectric conversion efficiency can be improved. Meanwhile, hydrogen ions can be combined with dangling bonds, so that the recombination center is reduced, and the passivation effect is achieved. Moreover, the PECVD equipment enables pinholes of the silicon nitride layer to be fewer, is not easy to crack, and is beneficial to improving the film forming quality of the silicon nitride layer.
Further, the silicon nitride layer may be one or more layers. In the case where the silicon nitride layers are multi-layered, a refractive index gradient may be formed between adjacent two silicon nitride layers. Thus, gradient extinction is realized through refractive index gradient, and the utilization rate of sunlight is further improved.
Specifically, in step S20, a laser may be used to open point holes on the second passivation layer and the alumina layer of the P-type silicon wafer 101. Further, the diameter of the dot-shaped hole is 25 μm to 45 μm. For example 25 μm, 27 μm, 30 μm, 32 μm, 35 μm, 40 μm, 45 μm. Further, the pitch between adjacent dot-shaped holes in the longitudinal direction of the fine grid is 400 μm to 800 μm. For example 400 μm, 420 μm, 500 μm, 600 μm, 700 μm, 780 μm, 800 μm. Further, the pitch between adjacent dot-shaped holes in the width direction of the fine gate is 500 μm to 1000 μm. For example 500 μm, 520 μm, 600 μm, 800 μm, 980 μm, 1000 μm.
Specifically, in step S20, a discontinuous line groove may be formed on the second passivation layer and the alumina layer of the P-type silicon wafer 101 by using a laser. Further, the length of the linear groove is 0.1mm-0.5mm. For example 0.1mm, 0.2mm, 0.3mm, 0.4mm, 0.5mm. Further, the width of the linear groove is 25 μm to 45 μm. For example 25 μm, 28 μm, 30 μm, 35 μm, 38 μm, 40 μm, 45 μm. Further, the interval between the adjacent linear grooves in the longitudinal direction of the fine grating is 0.2mm-1mm. For example 0.2mm, 0.4mm, 0.8mm, 1mm. Further, the pitch between the adjacent linear grooves in the width direction of the fine gate is 0.5mm to 1mm. For example 0.5mm, 0.6mm, 0.8mm, 1mm.
Specifically, in step S20, a continuous line groove may be formed on the second passivation layer and the alumina layer of the P-type silicon wafer 101 by using a laser. Specifically, the slot width is 2 μm to 100 μm. For example, 2 μm, 5 μm, 8 μm, 15 μm, 30 μm, 70 μm, 100 μm. Preferably, the width of the grooved region is 10 μm-35 μm. For example, 10 μm, 12 μm, 15 μm, 20 μm, 28 μm, 30 μm, 35 μm.
Specifically, in step S21, the first electrode 14 may be formed using screen printing. Therefore, the efficiency and the precision of manufacturing the electrode are higher, and the quality of the battery is improved. In other embodiments, the first electrode 14 may also be formed using copper plating, sputtering, vacuum evaporation, and the like.
Specifically, in step S21, the width of the first electrode 14 is 2 μm to 400 μm. For example, 2 μm, 10 μm, 100 μm, 300 μm, 400 μm. The width of the first electrode 14 is preferably 10 μm to 70 μm. For example, 10 μm, 20 μm, 50 μm, 65 μm, 70 μm.
Specifically, in step S21, the thickness of the first electrode 14 is 2 μm to 40 μm. For example, 2 μm, 10 μm, 15 μm, 30 μm, 40 μm. The thickness of the first electrode 14 is preferably 5 μm to 20 μm. For example, 5 μm, 10 μm, 15 μm, 20 μm.
Specifically, in step S23, the second electrode 17 may be formed by screen printing. Therefore, the efficiency and the precision of manufacturing the electrode are higher, and the quality of the battery is improved. In other embodiments, the second electrode 17 may also be formed by electroplating copper, sputtering, vacuum evaporation, or the like.
Specifically, in step S23, the width of the second electrode 17 is 2 μm to 400 μm. For example, 2 μm, 10 μm, 100 μm, 300 μm, 400 μm. The width of the second electrode 17 is preferably 10 μm to 70 μm. For example, 10 μm, 20 μm, 50 μm, 65 μm, 70 μm.
Specifically, in step S23, the thickness of the second electrode 17 is 2 μm to 40 μm. For example, 2 μm, 10 μm, 15 μm, 30 μm, 40 μm. The thickness of the second electrode 17 is preferably 5 μm to 20 μm. For example, 5 μm, 10 μm, 15 μm, 20 μm.
Specifically, in step S23, the aluminum doped layer 181 is an aluminum doped monocrystalline silicon layer, forming a p+ surface field. An aluminum-silicon alloy layer 182 is located between the aluminum-doped layer 181 and the second electrode 17. In this way, contact of the p+ surface field with the second electrode 17 is achieved by the aluminum silicon alloy layer 182.
Specifically, aluminum doped layer 181 is formed on the surface of recessed region 1011, and aluminum-silicon alloy layer 182 fills in recessed region 1011. In this way, the contact area between the aluminum doped layer 181 and the aluminum silicon alloy layer 182 can be effectively increased, and the expansion electrode and the surface contact resistance of the body region can be reduced, so that the contradiction between the shading area of the electrode and the resistance can be relieved.
It is understood that the second electrode 17 contacts the P-type silicon wafer 101 through the conductive contact layer 18 of the P-type solar cell 10. Conductive contact layer 18 includes an aluminum doped layer 181 and an aluminum silicon alloy layer 182.
It is understood that the first electrode 14 and the second electrode 17 may be formed by sintering after the slurry is applied.
Referring to fig. 3, optionally, after step S14, before step S17, the manufacturing method includes:
step S15: etching is performed on the P-type silicon wafer 101 on which the doped polysilicon layer 12 is prepared, and the doped polysilicon layer 12 on the side surface and the second surface of the P-type silicon wafer 101 is removed.
In this way, the doped polysilicon layer 12 generated by the plating is removed, and the preparation of the aluminum oxide layer 15 is prevented from being influenced. Note that when doped polysilicon is prepared using a PECVD apparatus, there is typically no wraparound phenomenon. When doped polysilicon is prepared using an LPCVD apparatus, there is generally a wraparound phenomenon.
Specifically, the doped polysilicon layer 12 may be etched by a dry method, or the doped polysilicon layer 12 may be etched by a wet method. Further, the doped polysilicon layer 12 may be etched by an acidic solution.
Referring to fig. 4, optionally, step S12 includes:
step S121: etching the P-type silicon wafer 101 and removing the damaged layer of the P-type silicon wafer 101;
step S122: cleaning the P-type silicon wafer 101;
after step S15, the manufacturing method includes:
step S16: the second side of the P-type silicon wafer 101 is textured.
Therefore, the damaged layer is removed firstly, and then the doped polysilicon generated by winding plating is removed and then the texturing is carried out, so that the waste can be avoided, and the efficiency is improved. It will be appreciated that if texturing is performed prior to removal of the doped polysilicon produced by the wraparound process, the texturing is susceptible to etching along with removal of the doped polysilicon produced by the wraparound process, resulting in inefficiency.
Specifically, in step S121, the P-type silicon wafer 101 may be etched using an acidic solution, and the damaged layer of the P-type silicon wafer 101 may be removed. Further, the acidic solution may be HF and HNO 3 The solution was mixed.
Specifically, in step S122, the P-type silicon wafer 101 may be cleaned with clean water. Further, the P-type silicon wafer 101 may be rinsed with clean water; the P-type silicon wafer 101 may also be immersed in clean water.
Specifically, in step S16, the second surface of the P-type silicon wafer 101 may be textured with an alkaline solution. Further, the alkaline solution may be a KOH or NaOH solution.
Referring to fig. 5, optionally, step S12 includes:
step S123: etching the P-type silicon wafer 101, removing the damaged layer of the P-type silicon wafer 101 and forming a suede on the second surface;
step S124: the P-type silicon wafer 101 is cleaned.
Therefore, the suede is formed while the damaged layer is removed, two steps are not needed, and the manufacturing efficiency can be improved. It will be appreciated that this is the case without wrap-around plating, and that there is no need to purge the doped polysilicon created by the wrap-around plating.
Specifically, in step S123, the P-type silicon wafer 101 may be etched using an alkaline solution and the second surface of the P-type silicon wafer 101 may be textured. Further, the alkaline solution may be a KOH or NaOH solution.
Specifically, in step S124, the P-type silicon wafer 101 may be cleaned with clean water. Further, the P-type silicon wafer 101 may be rinsed with clean water; the P-type silicon wafer 101 may also be immersed in clean water.
Referring to fig. 6, optionally, the second electrode 17 includes a fine gate, a main gate and a bonding pad, the fine gate is an aluminum conductor, and step S23 includes:
step S231: forming an aluminum conductor in the recessed area using an aluminum paste;
step S232: a main gate including a first silver conductive portion and/or a pad including a second silver conductive portion are formed on the aluminum conductor.
In this manner, at least one of the main gate and the bonding pad includes a silver conductive portion to facilitate soldering in manufacturing the battery assembly.
Specifically, in step S231, an aluminum conductor may be formed by screen printing; the aluminum conductors may also be formed by sputtering, vacuum evaporation, and the like.
Specifically, in step S232, the main gate may include a first silver conductive portion, and the pad may include a second silver conductive portion; the main grid can also comprise a first silver conductive part, and the bonding pad does not comprise a second silver conductive part; the main gate may further include no first silver conductive portion, and the pad includes a second silver conductive portion. Further, in the case where the main gate includes the first silver conductive portion, the portion of the main gate may be the first silver conductive portion, or the main gate may be the first silver conductive portion entirely. In the case where the pad includes the second silver conductive portion, the portion of the pad may be the second silver conductive portion, or the pad may be the second silver conductive portion entirely.
Specifically, in step S232, a silver conductive portion may be formed by screen printing; sputtering, vacuum evaporation, etc. may also be used to form the silver conductive portion.
Referring to fig. 7 and 8, optionally, the second electrode 17 includes an aluminum fine grid 171 and a silver fine grid 172, and step S23 includes:
step S233: forming aluminum fine grid 171 in the invagination area using aluminum paste;
step S234: silver fine grid 172 is formed on aluminum fine grid 171, and aluminum fine grid 171 and silver fine grid 172 are formed as composite fine grid.
In this way, ohmic contact is formed by self-doping of the aluminum fine gate 171, and current is efficiently conducted out by the strong conductivity of the silver fine gate 172. Further, since the aluminum fine grid 171 serves as a contact electrode, the thickness of the silver fine grid 172 may be thinner. Thus, the cost of the composite fine grid is low and the process is simple while the photoelectric conversion efficiency is ensured.
Specifically, in step S233, the aluminum fine grid 171 may be formed on the second face by screen printing using an aluminum paste. Thus, the aluminum fine grid 171 is manufactured with higher efficiency and accuracy, which is advantageous for improving the quality of the battery. In other embodiments, the aluminum fine gate 171 may also be formed using sputtering, vacuum evaporation, or the like.
Specifically, in step S234, the silver fine grid 172 may be formed by screen printing. Thus, the silver fine grid 172 is manufactured with higher efficiency and precision, which is beneficial to improving the quality of the battery. In other embodiments, sputtering, vacuum evaporation, etc. processes may also be used to form the silver fine grid 172.
Referring to fig. 8, optionally, step S234 includes: silver fine grid 172 is covered on the top and side surfaces of aluminum fine grid 171. In this way, the contact area of the silver fine grid 172 and the aluminum fine grid 171 is large, so that the conductive effect between the silver fine grid 172 and the aluminum fine grid 171 is better.
It will be appreciated that in other embodiments, the silver fine grid 172 may cover only the top surface of the aluminum fine grid 171 and not cover the side surfaces of the aluminum fine grid 171; the silver fine grid 172 may not cover the top surface of the aluminum fine grid 171 and may cover only the side surface of the aluminum fine grid 171.
Specifically, the silver fine grid 172 covers the entire surface of the aluminum fine grid 171 and covers the entire surface of the side surface of the aluminum fine grid 171. In this way, the contact area of the silver fine grid 172 and the aluminum fine grid 171 is made larger, so that the conduction effect between the silver fine grid 172 and the aluminum fine grid 171 is made better.
It will be appreciated that in other embodiments, silver fine grid 172 may cover a portion of the top surface of aluminum fine grid 171; the silver fine grid 172 may cover a partial region of the side surface of the aluminum fine grid 171. For example, the silver fine grid 172 may form a hollowed-out region.
Optionally, the aluminum fine grid 171 is covered with a thickness less than 1/2 of the thickness of the silver fine grid 172. The thickness of the aluminum fine grid 171 is, for example, 1/3, 1/4, 1/5, 1/6 of the thickness of the silver fine grid 172. In this way, the thickness ratio of the silver fine grid 172 to the aluminum fine grid 171 is in a proper range, so that poor overall conductivity caused by too small thickness ratio can be avoided, and too high cost caused by too large thickness ratio can be avoided.
Alternatively, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is 5 μm to 20 μm. For example, 5 μm, 6 μm, 10 μm, 15 μm, 20 μm. In this way, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is in a proper range, so that the situation that the silver fine grid 172 covered by the side surface of the aluminum fine grid 171 is thinner due to the too small difference in width can be avoided, the poor conductive effect is avoided, the situation that the silver fine grid 172 covered by the side surface of the aluminum fine grid 171 is thicker due to the too large difference in width can be avoided, and the high cost is avoided.
Optionally, the silver fine grid 172 has a thickness of 5 μm to 10 μm. For example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. In this way, the thickness of the silver fine grid 172 is in a proper range, so that poor conductive effect caused by too small thickness of the silver fine grid 172 can be avoided, and higher cost caused by too large thickness of the silver fine grid 172 can also be avoided.
Alternatively, the sum of the thicknesses of the aluminum fine gate 171, the aluminum doped layer 181, and the aluminum-silicon alloy layer 182 is 10 μm to 40 μm. For example, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 40 μm. Therefore, the sum of the thicknesses is in a proper range, so that the ohmic contact formed by self-doping of the aluminum fine grid 171 is good, and the high-efficiency current guiding out is facilitated.
Alternatively, the aluminum fine grid 171 has a width of 30 μm to 80 μm. For example 30 μm, 40 μm, 50 μm, 70 μm, 80 μm. In this way, the width of the aluminum fine grid 171 is in a proper range, which is beneficial to efficiently leading out the current.
Optionally, the width of the recessed region 1011 is greater than the width of the slotted region. Optionally, the width of the aluminum-silicon alloy layer 182 is greater than the width of the grooved region, and the aluminum-silicon alloy layer 182 is locally covered with the second passivation layer 16. Thus, a larger inward-sinking region 1011 can be formed through a narrower slotting region, so that the contact area between the aluminum doped layer 181 and the silicon wafer is larger, the contact area between the aluminum doped layer 181 and the aluminum silicon alloy layer 182 is larger, and the expanded electrode and the surface contact resistance of the body region can be reduced, thereby relieving the contradiction between the shading area of the electrode and the resistance.
Alternatively, the ratio of the surface area of the depressed region 1011 to the projected area in the thickness direction is greater than 1.05. Thus, the invagination area 1011 is larger, the contact area between the aluminum doped layer 181 and the silicon wafer is larger, the contact area between the aluminum doped layer 181 and the aluminum silicon alloy layer 182 is larger, and the expansion electrode and the surface contact resistance of the body region can be reduced, so that the contradiction between the shading area of the electrode and the resistance is relieved.
Alternatively, the invagination depth of the invagination region 1011 is greater than 3 μm. For example, 3 μm, 4 μm, 5 μm, 6 μm. In this way, the surface area of the recessed region 1011 is increased by making the recessed depth larger.
In the related art, the front emitter reverse dark saturation current density (J0) of the PERC cell was 20fA/cm 2 Contact area J0 is 600fA/cm 2 The back non-contact region J0 was 3fA/cm 2 Contact area J0 is 500fA/cm 2 . Front emitter J0 of Topcont cell is 10fA/cm 2 Contact area J0 is 800fA/cm 2 The back non-contact region J0 was 2fA/cm 2 Contact area J0 is 50fA/cm 2 。
The first surface J0 of the P-type solar cell 10 manufactured by the manufacturing method of the P-type solar cell 10 of the embodiment is 2fA/cm 2 Contact area J0 is 50fA/cm 2 The second surface non-contact area J0 is 2fA/cm 2 Contact area J0 is 500fA/cm 2 。
If the area ratio of the contact areas is 2%, the J0 of the PERC cell in the related art is 43.54fA/cm 2 . The J0 of the P-type solar cell 10 manufactured by the manufacturing method of the P-type solar cell 10 of the embodiment is 14.92fA/cm 2 . Obviously, the electrical performance of the P-type solar cell 10 manufactured by the manufacturing method of the P-type solar cell 10 of the present embodiment is better.
Other explanations and illustrations of this embodiment are made to other parts of this document, and are not repeated here to avoid redundancy.
Example two
The P-type solar cell 10 of the present embodiment is manufactured by the manufacturing method of the P-type solar cell 10 according to any one of the first embodiment.
According to the manufacturing method of the P-type solar cell 10, the doped polysilicon layer 12 is arranged on the first surface, and the aluminum oxide layer 15 is arranged on the second surface, so that the manufactured P-type solar cell 10 can resist radiation on both sides, and attenuation caused by radiation is reduced. Meanwhile, the cost of manufacturing the P-type solar cell 10 is low, and the photoelectric conversion efficiency is high.
Other explanations and illustrations of this embodiment are made to other parts of this document, and are not repeated here to avoid redundancy.
Example III
The P-type solar cell 10 of the present embodiment includes:
a P-type silicon wafer 101;
the first electrode 14 is a silver electrode, and the first electrode 14 passes through the first passivation layer 13 to be in contact with the doped polysilicon;
the aluminum oxide layer 15, the second passivation layer 16 and the second electrode 17 are sequentially stacked on the second surface of the P-type silicon wafer 101, the second electrode 17 comprises an aluminum electrode, the aluminum oxide layer 15 and the second passivation layer 16 are provided with a grooved region, the P-type silicon wafer 101 below the grooved region forms an invagination region 1011, the second electrode 17 penetrates through the grooved region, an aluminum doped layer 181 is formed on the surface of the invagination region 1011, and an aluminum silicon alloy layer 182 is filled in the invagination region 1011.
In the P-type solar cell 10 of the embodiment of the present application, since the doped polysilicon layer 12 is disposed on the first surface and the alumina layer 15 is disposed on the second surface, the P-type solar cell 10 can be made to be radiation-resistant on both sides, so as to reduce attenuation caused by radiation. Meanwhile, the cost of manufacturing the P-type solar cell 10 is low, and the photoelectric conversion efficiency is high.
Optionally, the second electrode 17 includes a fine gate, a main gate, and a pad, the fine gate being an aluminum conductor, the main gate including a first silver conductive portion, and/or the pad including a second silver conductive portion.
Optionally, the second electrode 17 is a composite fine grid, which includes an aluminum fine grid 171 and a silver fine grid 172, and the silver fine grid 172 is disposed on a side of the aluminum fine grid 171 facing away from the P-type silicon wafer 101.
Optionally, silver fine grid 172 covers the top and side surfaces of aluminum fine grid 171.
Alternatively, the difference between the width of the silver fine grid 172 and the width of the aluminum fine grid 171 is 5 μm to 20 μm.
Optionally, the silver fine grid 172 has a thickness of 5 μm to 10 μm.
Alternatively, the sum of the thicknesses of the aluminum fine gate 171 and the aluminum doped layer 181 and the aluminum silicon alloy layer 182 is 10 μm to 40 μm.
Alternatively, the aluminum fine grid 171 has a width of 30 μm to 80 μm.
Alternatively, the grooved region width is 10 μm-35 μm.
Optionally, the width of the recessed region 1011 is greater than the width of the slotted region.
Optionally, the width of the aluminum-silicon alloy layer 182 is greater than the width of the grooved region, and the aluminum-silicon alloy layer 182 is locally covered with the second passivation layer 16.
Alternatively, the ratio of the surface area of the depressed region 1011 to the projected area in the thickness direction is greater than 1.05.
Alternatively, the invagination depth of the invagination region 1011 is greater than 3 μm.
Other explanations and illustrations of this embodiment may be made with reference to other parts of this document, particularly embodiment one, and are not repeated here to avoid redundancy.
Example IV
The cell assembly of the present embodiment includes the P-type solar cell 10 of the second embodiment or the third embodiment.
In the battery assembly of the embodiment of the application, the doped polysilicon layer 12 is arranged on the first surface, and the aluminum oxide layer 15 is arranged on the second surface, so that the manufactured P-type solar cell 10 can resist radiation on both sides, and therefore attenuation caused by radiation is reduced. Meanwhile, the cost of manufacturing the P-type solar cell 10 is low, and the photoelectric conversion efficiency is high.
Other explanations and illustrations of this embodiment are made to other parts of this document, and are not repeated here to avoid redundancy.
Example five
The photovoltaic system of this embodiment includes the battery assembly of the fourth embodiment.
In the photovoltaic system of the embodiment of the present application, since the first surface is provided with the doped polysilicon layer 12 and the second surface is provided with the alumina layer 15, the manufactured P-type solar cell 10 can resist radiation on both sides, thereby reducing attenuation caused by radiation. Meanwhile, the cost of manufacturing the P-type solar cell 10 is low, and the photoelectric conversion efficiency is high.
In this embodiment, the photovoltaic system may be applied to a photovoltaic power station, such as a ground power station, a roof power station, a water power station, or the like, and may also be applied to a device or apparatus that uses solar energy to generate power, such as a user solar power source, a solar street lamp, a solar car, a solar building, or the like. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system may be applied to all fields where solar energy is required to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can comprise a photovoltaic array, a junction box and an inverter, wherein the photovoltaic array can be an array combination of a plurality of battery assemblies, for example, the plurality of battery assemblies can form a plurality of photovoltaic arrays, the photovoltaic array is connected with the junction box, the junction box can conduct junction on current generated by the photovoltaic array, and the junction box is connected with a commercial power network after the junction current flows through the inverter and is converted into alternating current required by the commercial power network so as to realize solar power supply.
Other explanations and illustrations of this embodiment are made to other parts of this document, and are not repeated here to avoid redundancy.
The foregoing description of the preferred embodiment of the present invention is not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Furthermore, the particular features, structures, materials, or characteristics described in the various embodiments or examples of the application may be combined in any suitable manner in any one or more embodiments or examples.

Claims (18)

1. The manufacturing method of the P-type solar cell is characterized by comprising the following steps of:
providing a P-type silicon wafer;
etching and cleaning the P-type silicon wafer;
preparing a tunneling oxide layer on a first surface of the P-type silicon wafer;
preparing a doped polysilicon layer on the tunneling oxide layer;
preparing an alumina layer on the second surface of the P-type silicon wafer;
preparing a first passivation layer on the doped polysilicon layer;
preparing a second passivation layer on the aluminum oxide layer;
carrying out laser grooving on the second surface of the P-type silicon wafer;
forming a first electrode on the first face using silver paste, the first electrode contacting the doped polysilicon layer through the first passivation layer;
forming an invagination area on the second surface of the P-type silicon wafer by etching;
forming a second electrode in the invagination area by using aluminum paste, wherein the second electrode forms an aluminum doped layer on the surface of the invagination area through a grooving area and fills an aluminum-silicon alloy layer in the invagination area;
the width of the slotting region is 10-35 mu m;
the width of the invagination area is larger than that of the slotting area;
the width of the aluminum-silicon alloy layer is larger than that of the grooving area, and the aluminum-silicon alloy layer is locally covered with the second passivation layer;
the ratio of the surface area of the invagination area to the projected area in the thickness direction is greater than 1.05;
the invagination depth of the invagination area is greater than 3 μm.
2. The method of claim 1, wherein after the step of preparing a doped polysilicon layer on the tunnel oxide layer, the method of preparing an aluminum oxide layer on the second side of the P-type silicon wafer comprises:
and etching the P-type silicon wafer on which the doped polysilicon layer is prepared, and removing the doped polysilicon layer on the second surface of the side surface of the P-type silicon wafer.
3. The method for manufacturing the P-type solar cell according to claim 2, wherein etching and cleaning the P-type silicon wafer comprises:
etching the P-type silicon wafer and removing the damaged layer of the P-type silicon wafer;
cleaning the P-type silicon wafer;
after the step of etching the P-type silicon wafer on which the doped polysilicon layer is prepared, the manufacturing method comprises the following steps:
and texturing the second surface of the P-type silicon wafer.
4. The method for manufacturing the P-type solar cell according to claim 1, wherein etching and cleaning the P-type silicon wafer comprises:
etching the P-type silicon wafer, removing the damaged layer of the P-type silicon wafer and forming a suede on the second surface;
and cleaning the P-type silicon wafer.
5. The method of claim 1, wherein preparing a doped polysilicon layer on the tunnel oxide layer, comprises:
and preparing the doped polysilicon layer on the tunneling oxide layer by using a PECVD device or an LPCVD device.
6. The method of claim 1, wherein the first passivation layer comprises a first silicon nitride layer, and wherein the preparing the first passivation layer on the doped polysilicon layer comprises:
and preparing the first silicon nitride layer on the doped polysilicon layer by using a PECVD device.
7. The method of claim 1, wherein the second passivation layer comprises a second silicon nitride layer, and wherein the preparing the second passivation layer on the aluminum oxide layer comprises:
and preparing the second silicon nitride layer on the aluminum oxide layer by using a PECVD device.
8. The method of manufacturing a P-type solar cell according to claim 1, wherein the second electrode includes a fine gate, a main gate, and a pad, the fine gate is an aluminum conductor, the second electrode is formed on the second surface using aluminum paste, comprising:
forming the aluminum conductor in the recessed region using an aluminum paste;
the main gate and the bonding pad are formed on the aluminum conductor, the main gate including a first silver conductive portion, and/or the bonding pad including a second silver conductive portion.
9. The method of manufacturing a P-type solar cell according to claim 1, wherein the second electrode includes an aluminum fine grid and a silver fine grid, the second electrode is formed on the second surface using an aluminum paste, comprising:
forming the aluminum fine grid in the invagination area by using aluminum slurry;
and forming the silver fine grid on the aluminum fine grid, wherein the aluminum fine grid and the silver fine grid are formed into a composite fine grid.
10. The method of claim 9, wherein forming the silver fine grid on the aluminum fine grid comprises:
and covering the top surface and the side surfaces of the aluminum fine grid with the silver fine grid.
11. The method of claim 9, wherein the aluminum thin grid is covered with a thickness less than 1/2 of the thickness of the silver thin grid.
12. The method of claim 9, wherein the difference between the width of the silver fine grid and the width of the aluminum fine grid is 5 μm to 20 μm.
13. The method of claim 9, wherein the silver fine grid has a thickness of 5 μm to 10 μm.
14. The method of claim 9, wherein the sum of the thicknesses of the aluminum fine grid, the aluminum doped layer and the aluminum silicon alloy layer is 10 μm to 40 μm.
15. The method of claim 9, wherein the aluminum thin gate has a width of 30 μm to 80 μm.
16. A P-type solar cell, characterized in that it is manufactured by the manufacturing method of the P-type solar cell according to any one of claims 1 to 15.
17. A cell assembly comprising the P-type solar cell of claim 16.
18. A photovoltaic system comprising the cell assembly of claim 17.
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Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246324A (en) * 2008-11-12 2011-11-16 矽利康有限公司 Back contact photovoltaic solar cells with grooves
JP2017033970A (en) * 2015-07-29 2017-02-09 京セラ株式会社 Solar cell element and method of manufacturing the same
WO2018157498A1 (en) * 2017-03-03 2018-09-07 广东爱康太阳能科技有限公司 P-type perc double-sided solar cell and module and system thereof, and preparation method therefor
CN108604608A (en) * 2015-12-18 2018-09-28 荷兰能源研究中心基金会 The method of series-connected solar cells and this solar cell of manufacture
CN109524480A (en) * 2018-11-26 2019-03-26 东方日升（常州）新能源有限公司 A kind of p-type crystal silicon solar battery and preparation method thereof of local contact passivation
CN109980022A (en) * 2019-04-24 2019-07-05 通威太阳能（成都）有限公司 A kind of p-type tunneling oxide passivation contact solar cell and preparation method thereof
WO2020220392A1 (en) * 2019-04-29 2020-11-05 南通天盛新能源股份有限公司 Metallization method for front electrode of n-type solar cell
CN112420855A (en) * 2020-11-16 2021-02-26 苏州腾晖光伏技术有限公司 Solar cell based on P-type silicon wafer and preparation method thereof
CN112563348A (en) * 2021-01-07 2021-03-26 南通天盛新能源股份有限公司 Metallization method for passivation contact of tunneling oxide layer on back electrode of solar cell
CN112599615A (en) * 2021-03-05 2021-04-02 浙江正泰太阳能科技有限公司 N-type Topcon battery with double-sided aluminum paste electrode and preparation method thereof
CN113345970A (en) * 2021-06-04 2021-09-03 浙江爱旭太阳能科技有限公司 P-type back contact type crystalline silicon solar cell, preparation method and cell assembly
CN113707755A (en) * 2020-05-22 2021-11-26 一道新能源科技(衢州)有限公司 IBC crystalline silicon solar cell and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI688109B (en) * 2018-10-26 2020-03-11 財團法人工業技術研究院 Solar cell

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102246324A (en) * 2008-11-12 2011-11-16 矽利康有限公司 Back contact photovoltaic solar cells with grooves
JP2017033970A (en) * 2015-07-29 2017-02-09 京セラ株式会社 Solar cell element and method of manufacturing the same
CN108604608A (en) * 2015-12-18 2018-09-28 荷兰能源研究中心基金会 The method of series-connected solar cells and this solar cell of manufacture
WO2018157498A1 (en) * 2017-03-03 2018-09-07 广东爱康太阳能科技有限公司 P-type perc double-sided solar cell and module and system thereof, and preparation method therefor
CN109524480A (en) * 2018-11-26 2019-03-26 东方日升（常州）新能源有限公司 A kind of p-type crystal silicon solar battery and preparation method thereof of local contact passivation
CN109980022A (en) * 2019-04-24 2019-07-05 通威太阳能（成都）有限公司 A kind of p-type tunneling oxide passivation contact solar cell and preparation method thereof
WO2020220392A1 (en) * 2019-04-29 2020-11-05 南通天盛新能源股份有限公司 Metallization method for front electrode of n-type solar cell
CN113707755A (en) * 2020-05-22 2021-11-26 一道新能源科技(衢州)有限公司 IBC crystalline silicon solar cell and manufacturing method thereof
CN112420855A (en) * 2020-11-16 2021-02-26 苏州腾晖光伏技术有限公司 Solar cell based on P-type silicon wafer and preparation method thereof
CN112563348A (en) * 2021-01-07 2021-03-26 南通天盛新能源股份有限公司 Metallization method for passivation contact of tunneling oxide layer on back electrode of solar cell
CN112599615A (en) * 2021-03-05 2021-04-02 浙江正泰太阳能科技有限公司 N-type Topcon battery with double-sided aluminum paste electrode and preparation method thereof
CN113345970A (en) * 2021-06-04 2021-09-03 浙江爱旭太阳能科技有限公司 P-type back contact type crystalline silicon solar cell, preparation method and cell assembly

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