CN214480657U - Edge calculation server - Google Patents
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- CN214480657U CN214480657U CN202120775368.0U CN202120775368U CN214480657U CN 214480657 U CN214480657 U CN 214480657U CN 202120775368 U CN202120775368 U CN 202120775368U CN 214480657 U CN214480657 U CN 214480657U
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Abstract
The utility model provides an edge calculation server sets up low band transmitting circuit, low band receiving circuit, high band transmitting circuit and high band receiving circuit in the server for two frequency channels of compatible 410MHz-510MHz of server and 863MHz-928MHz, when different territories use, the selection Lora frequency channel switches over, with the requirement that adapts to different region Lora frequency channels, realize different region Lora communications under the prerequisite of not changing the Lora module.
Description
Technical Field
The utility model relates to a wireless communication field especially relates to an edge calculation server.
Background
Because of the control of the Lora frequency band, most edge computing servers related to Lora are used domestically in the market, the frequency band most used domestically is CN470-510 at present, the frequency band range is 470-510MHz, the maximum transmitting power can reach 17dBm (50mW), and the transmitting time length is less than 5000 ms. The frequency band that foreign and this country used is different, and foreign because the reason of frequency band control, realizes that network communication just can change the Lora module under the prerequisite of not changing equipment to the requirement of adaptation local frequency channel. The mode of changing the Lora module is realized to be wasted time and energy and with high costs. Therefore, in order to solve the above problem, the utility model provides an edge calculation server compromises the multifrequency section, when using different territories, switches over the selection Lora frequency channel to adapt to the requirement of different region Lora frequency channels, realize different region Lora communications under the prerequisite of not changing the Lora module.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides an edge calculation server compromises two kinds of frequency channels at home and abroad, when using different territories, switches over the selection Lora frequency channel to the requirement of adaptation different regions Lora frequency channels realizes different regions Lora communication under the prerequisite of not changing the Lora module.
The technical scheme of the utility model is realized like this: the utility model provides an edge calculation server, which comprises a CPU chip, a Lora module and an antenna, wherein the Lora module comprises a Lora chip, a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a fourth radio frequency switch, a low-frequency section sending circuit, a low-frequency section receiving circuit, a high-frequency section sending circuit and a high-frequency section receiving circuit;
the Lora chip is electrically connected with the CPU chip through the SPI bus, and the control ends of the first radio frequency switch, the second radio frequency switch, the third radio frequency switch and the fourth radio frequency switch are respectively and correspondingly electrically connected with the I/O ports of the CPU chip one by one;
the radio frequency transmitting end of the Lora chip is electrically connected with the public end of the first radio frequency switch, and the RF1 end and the RF2 end of the first radio frequency switch are respectively electrically connected with the input end of the low-frequency-band transmitting circuit and the input end of the high-frequency-band transmitting circuit; the output end of the low-frequency-band transmitting circuit and the output end of the high-frequency-band transmitting circuit are electrically connected with the RF1 end and the RF2 end of the third radio frequency switch in a one-to-one correspondence manner, and the common end of the third radio frequency switch is electrically connected with the antenna;
the antenna is electrically connected with the common end of the fourth radio frequency switch, the RF1 end and the RF2 end of the fourth radio frequency switch are respectively electrically connected with the input end of the low-frequency band receiving circuit and the input end of the high-frequency band receiving circuit in a one-to-one correspondence manner, the output end of the low-frequency band receiving circuit and the output end of the high-frequency band receiving circuit are respectively electrically connected with the RF1 end and the RF2 end of the second radio frequency switch in a one-to-one correspondence manner, and the common end of the second radio frequency switch is electrically connected with the radio frequency receiving end of the Lora chip.
On the basis of the above technical solution, preferably, the frequency band covered by the low-frequency band transmitting circuit and the low-frequency band receiving circuit is 410MHz-510MHz, and the frequency band covered by the high-frequency band transmitting circuit and the high-frequency band receiving circuit is 863MHz-928 MHz.
On the basis of the above technical solution, preferably, the low-frequency band transmission circuit includes a first transmission resonant circuit and a first transmission filter circuit;
the input end of the first transmitting resonant circuit is electrically connected with the RF1 end of the first radio frequency switch, and the output end of the first transmitting resonant circuit is electrically connected with the RF1 end of the third radio frequency switch through the first transmitting filter circuit.
On the basis of the above technical solution, preferably, the high-band transmission circuit includes a second transmission resonant circuit and a second transmission filter circuit;
the input end of the second transmitting resonant circuit is electrically connected with the RF2 end of the first radio frequency switch, and the output end of the second transmitting resonant circuit is electrically connected with the RF2 end of the third radio frequency switch through the second transmitting filter circuit.
On the basis of the above technical solution, preferably, the low-band receiving circuit includes a first receiving resonant circuit and a first receiving filter circuit;
the input end of the first receiving filter circuit is electrically connected with the RF1 end of the fourth radio frequency switch, and the output end of the first receiving filter circuit is electrically connected with the RF1 end of the second radio frequency switch through the first receiving resonant circuit.
On the basis of the above technical solution, preferably, the high-band receiving circuit includes a second receiving resonant circuit and a second receiving filter circuit;
the input end of the second receiving filter circuit is electrically connected with the RF2 end of the fourth radio frequency switch, and the output end of the second receiving filter circuit is electrically connected with the RF2 end of the second radio frequency switch through the second receiving resonant circuit.
On the basis of the above technical solution, preferably, the Lora module further includes a first pi-type matching circuit, a second pi-type matching circuit, and a fifth radio frequency switch;
the common terminal of the third radio frequency switch is electrically connected with the RF1 terminal of the fifth radio frequency switch through a first pi-type matching circuit; the common terminal of the fourth radio frequency switch is electrically connected with the RF2 terminal of the fifth radio frequency switch through a second pi-type matching circuit; the common end of the fifth radio frequency switch is electrically connected with the antenna, and the control end of the fifth radio frequency switch is electrically connected with the I/O ports of the CPU chip in a one-to-one correspondence manner.
The utility model discloses an edge calculation server has following beneficial effect for prior art:
(1) the server is internally provided with a low-frequency-band transmitting circuit, a low-frequency-band receiving circuit, a high-frequency-band transmitting circuit and a high-frequency-band receiving circuit, so that the server is compatible with two frequency bands of 410MHz-510MHz and 863MHz-928MHz, and when the server is used in different regions, the Lora frequency bands are switched and selected to meet the requirements of the Lora frequency bands in different regions, and Lora communication in different regions is realized on the premise of not replacing Lora modules;
(2) the first radio frequency switch and the third radio frequency switch form an input switch and an output switch of a transmitting link, when the Lora module is in a transmitting mode, the first radio frequency switch and the third radio frequency switch can be controlled to perform an alternative operation in low-frequency-band transmission and high-frequency-band transmission, and the integrity of the transmitting link of the server is ensured;
(3) the second radio frequency switch and the fourth radio frequency switch form an input switch and an output switch of a receiving link, when the Lora module is in a receiving mode, the second radio frequency switch and the fourth radio frequency switch can be controlled to perform one of two operations in low-frequency band receiving and high-frequency band receiving, and the integrity of the receiving link of the server is ensured;
(4) the fifth radio frequency switch is arranged at the intersection of the receiving and transmitting links, so that the receiving and transmitting control can be realized, the isolation of the receiving link and the transmitting link is improved, and the receiving link and the transmitting link are ensured not to interfere with each other.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block diagram of an edge computing server according to the present invention;
fig. 2 is a circuit diagram of a first rf switch, a low band transmitting circuit, a high band transmitting circuit, a third rf switch, and a first pi-type matching circuit in an edge computing server according to the present invention;
fig. 3 is a circuit diagram of the second rf switch, the low band receiving circuit, the high band receiving circuit, the fourth rf switch and the second pi-type matching circuit in the edge computing server of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.
As shown in fig. 1, the utility model discloses an edge computing server, it includes CPU chip, Lora module and antenna.
And the CPU chip is used as a central control of the edge computing server. A Broadcom BCM2837 series chip may be used.
And the Lora module provides the Lora communication function. Because the edge calculation server related to Lora on the market can only provide the frequency channel of domestic use, when it used abroad, because there is not compatible foreign Lora frequency channel, only can change the Lora module, this kind of mode is got up and is wasted time and energy and with high costs. Therefore, in order to solve the above problems, in this embodiment, the structure of the Lora module is optimized, so that the Lora module is compatible with frequency bands at home and abroad, and when the Lora module is used in different regions, the Lora frequency bands are switched to meet the requirements of the Lora frequency bands in different regions, and communication of the Lora in different regions is realized on the premise of not replacing the Lora module. Specifically, as shown in fig. 1, the Lora module includes a Lora chip, a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a fourth radio frequency switch, a fifth radio frequency switch, a low-frequency band transmitting circuit, a low-frequency band receiving circuit, a high-frequency band transmitting circuit, a high-frequency band receiving circuit, a first pi-type matching circuit, and a second pi-type matching circuit. The first radio frequency switch, the low-frequency band transmitting circuit, the high-frequency band transmitting circuit, the third radio frequency switch, the first pi-type matching circuit, the RF1 of the fifth radio frequency switch and the antenna form a transmitting link, and the second radio frequency switch, the low-frequency band receiving circuit, the high-frequency band receiving circuit, the fourth radio frequency switch, the second pi-type matching circuit, the RF2 of the fifth radio frequency switch and the antenna form a receiving link.
Firstly, the structural part and the working principle of the transmission link are introduced, specifically as follows:
the Lora chip is electrically connected with the CPU chip through the SPI bus, and comprises a 410MHz-510MHz frequency band and an 863MHz-928MHz frequency band transceiving control algorithm, the algorithm belongs to the prior mature technology, the embodiment does not relate to the improvement of the Lora algorithm, only integrates the two prior algorithms in the same Lora chip, and executes the corresponding Lora algorithm through a simple selection rule, so that technicians in the field can obtain the corresponding algorithm without worry when knowing the content recorded in the embodiment and realize the functions of the embodiment through the prior art. Chips of the SX126x series may be selected as Lora chips. In this embodiment, an SX1262 chip is selected, and its RFO pin is a radio frequency transmitting terminal, RFI _ N pin is a radio frequency receiving terminal, and VR _ PA is its voltage-stabilizing power amplifier power supply pin.
The first radio frequency switch is used for switching and selecting the frequency band of the transmission link, namely, performing alternative operation in the low-frequency band transmission link and the high-frequency band transmission link. In this embodiment, the control terminal of the first RF switch is electrically connected to the I/O port of the CPU chip, the common terminal of the first RF switch is electrically connected to the RF transmitting terminal of the Lora chip, and the RF1 terminal and the RF2 terminal of the first RF switch are electrically connected to the input terminal of the low-band transmitting circuit and the input terminal of the high-band transmitting circuit, respectively. Preferably, the first radio frequency switch may be a PE4259 series chip, and pin 4 and pin 6 of the first radio frequency switch are control terminals, and when pin 6 is connected to VDD and pin 4 is connected to a high level, the common terminal RFC of the first radio frequency switch is communicated with the RF1 terminal thereof; when pin 6 is at VDD and pin 4 is low, the common terminal RFC of the first RF switch is connected to its RF2 terminal. As shown in fig. 2, the I/O port of the first RF switch, pin 4, connected to the CPU chip is labeled as RF _ SW 1.
And the low-frequency band transmitting circuit supports the signal transmitting function of a frequency band of 410MHz-510 MHz. Preferably, as shown in fig. 1, the low band transmission circuit includes a first transmission resonant circuit and a first transmission filter circuit; the input end of the first transmitting resonant circuit is electrically connected with the RF1 end of the first radio frequency switch, and the output end of the first transmitting resonant circuit is electrically connected with the RF1 end of the third radio frequency switch through the first transmitting filter circuit. In this embodiment, an SX1262 chip is selected as a Lora chip, and therefore, the first transmit resonant circuit matched with the SX1262 chip includes an inductor L2-L4 and a capacitor C1-C7, and the frequency band adjusting function can be realized by adjusting the capacitance value of the capacitor in the first transmit resonant circuit according to data of the SX1262 chip, and specific operation steps are not described herein. The first transmitting and filtering circuit is used for filtering the interference signal, and a conventional low-pass filter can be adopted, which will not be described in detail herein.
The high-frequency band transmitting circuit supports the signal transmitting function of the 863MHz-928MHz frequency band. Preferably, the high-band transmission circuit includes a second transmission resonant circuit and a second transmission filter circuit; the input end of the second transmitting resonant circuit is electrically connected with the RF2 end of the first radio frequency switch, and the output end of the second transmitting resonant circuit is electrically connected with the RF2 end of the third radio frequency switch through the second transmitting filter circuit. In this embodiment, the structure of the second transmitting resonant circuit may be the same as or different from that of the first transmitting resonant circuit, and in this embodiment, the structure of the second transmitting resonant circuit is set to be the same as that of the first transmitting resonant circuit, as shown in fig. 2, the second transmitting resonant circuit includes a inductor L5-L8 and a capacitor C8-C14, but the two include different capacitance parameters. The second transmitting filter circuit is used for filtering the interference signal, and a conventional low-pass filter can be adopted, which will not be described in detail herein.
And the third radio frequency switch is used for selectively outputting high-frequency band and low-frequency signals, and the third radio frequency switch and the first radio frequency switch are matched to form an input switch and an output switch of a transmitting link. In this embodiment, the output end of the first transmitting resonant circuit is electrically connected to the RF1 end of the third RF chip through the first transmitting filter circuit, the output end of the second transmitting resonant circuit is electrically connected to the RF2 end of the third RF chip through the second transmitting filter circuit, the common end of the third RF chip is electrically connected to the antenna, and the control end of the third RF switch is electrically connected to the I/O port of the CPU chip. In this embodiment, the third rf switch is a switch of the same type as the first rf switch, and the circuit diagram of the third rf switch is the same as the structure of the first rf switch. As shown in fig. 2, the I/O port of the third RF switch, which is connected to the pin 4 of the CPU chip, is denoted as RF _ SW3 in this embodiment.
The first pi-type matching circuit realizes impedance matching. In this embodiment, an SX1262 chip is selected as a Lora chip, and therefore, as shown in fig. 2, a first pi-type matching circuit matched with the SX1262 chip is shown, in this embodiment, an RF5_ RF1 represents an RF1 terminal of the fifth RF switch, and an RF5_ RF2 represents an RF2 terminal of the fifth RF switch.
And the fifth radio frequency switch is used for receiving and transmitting control. In this embodiment, as shown in fig. 1, the common terminal of the third RF switch is electrically connected to the RF1 terminal of the fifth RF switch through the first pi-type matching circuit; the common terminal of the fourth radio frequency switch is electrically connected with the RF2 terminal of the fifth radio frequency switch through a second pi-type matching circuit; the common end of the fifth radio frequency switch is electrically connected with the antenna, and the control end of the fifth radio frequency switch is electrically connected with the I/O ports of the CPU chip in a one-to-one correspondence manner. In this embodiment, the fifth rf switch is a switch of the same type as the first rf switch, and a circuit diagram of the fifth rf switch is the same as the structure of the first rf switch. When the pin 6 of the fifth radio frequency switch is connected with VDD and the pin 4 is connected with high level, the common terminal RFC of the fifth radio frequency switch is communicated with the RF1 terminal thereof, and then signal transmission is carried out; when pin 6 is connected to VDD and pin 4 is connected to low level, the common terminal RFC of the fifth RF switch is connected to its RF2 terminal, which is signal receiving.
In this embodiment, the working principle of the transmission link is as follows: when the Lora module is in a sending mode, a radio frequency sending end of the Lora chip outputs a radio frequency signal to a public end of the first radio frequency switch; when the edge computing server selects a low frequency band, the CPU chip gates an RF1 end of the first radio frequency switch, radio frequency signals are sent to a low frequency band sending circuit, tuning processing is carried out on the radio frequency signals by a first sending resonance circuit in the low frequency band sending circuit, the low frequency radio frequency signals are output after filtering processing is carried out on the first sending filter circuit, the CPU chip gates an RF1 end of the third radio frequency switch, the low frequency radio frequency signals are output to a first pi-type matching circuit through the third radio frequency switch, impedance matching processing is carried out on the low frequency radio frequency signals by the first pi-type matching circuit, at the moment, the CPU chip gates an RF1 end of the fifth radio frequency switch, and the low frequency radio frequency signals are output to an antenna from a common end of the fifth radio frequency switch and are output to a free space through the antenna;
when the edge computing server selects a high frequency band, the CPU chip gates the RF2 end of the first radio frequency switch, the radio frequency signal is sent to the high frequency band sending circuit, the second sending resonance circuit in the high frequency band sending circuit carries out tuning processing, the second sending filter circuit carries out filtering processing and then outputs the high frequency radio frequency signal, the CPU chip gates the RF2 end of the third radio frequency switch, the high frequency radio frequency signal is output to the first pi-type matching circuit through the third radio frequency switch, the impedance matching processing is carried out through the first pi-type matching circuit, at the moment, the CPU chip gates the RF2 end of the fifth radio frequency switch, and the low frequency radio frequency signal is output to the antenna from the common end of the fifth radio frequency switch and is output to the free space through the antenna.
The following describes the structural part and the operation principle of the transmission link, specifically as follows:
when the Lora module is in a receiving mode, the CPU chip gates the RF2 end of the fifth radio frequency switch, and the echo signal received by the antenna is input to the second pi-type matching circuit through the fifth radio frequency switch. The structure and function of the second pi-type matching circuit are the same as those of the first pi-type matching circuit, and the description is not repeated here.
And the fourth radio frequency switch is used for selectively sending the echo signals received by the antenna into the low-frequency band receiving circuit and the high-frequency band receiving circuit. In this embodiment, the common terminal of the fourth RF switch is electrically connected to the RF2 terminal of the fifth RF switch through the second pi-type matching circuit, and the RF1 terminal and the RF2 terminal of the fourth RF switch are electrically connected to the input terminal of the low band receiving circuit and the input terminal of the high band receiving circuit in a one-to-one correspondence manner. In this embodiment, the fifth rf switch is a switch of the same type as the first rf switch, and a circuit diagram of the fifth rf switch is the same as the structure of the first rf switch. In this embodiment, the I/O port connecting pin 4 of the fourth RF switch to the CPU chip is denoted as RF _ SW 4.
And the low-frequency band receiving circuit is used for realizing the function of receiving signals in a frequency band of 410MHz-510 MHz. Preferably, as shown in fig. 1, the low band receiving circuit includes a first receiving resonant circuit and a first receiving filter circuit; the input end of the first receiving filter circuit is electrically connected with the RF1 end of the fourth radio frequency switch, and the output end of the first receiving filter circuit is electrically connected with the RF1 end of the second radio frequency switch through the first receiving resonant circuit. In this embodiment, an SX1262 chip is selected as a Lora chip, and therefore, the first receiving resonant circuit matched with the SX1262 chip includes capacitors C27-C29 and an inductor L11 as shown in fig. 3, and the frequency band adjusting function can be realized by adjusting the capacitance value of the capacitor in the first receiving resonant circuit according to data of the SX1262 chip, and specific operation steps are not described herein again. The first receiving filter circuit is used for filtering the interference signal, and a conventional low-pass filter may be used, which will not be described in detail herein.
The high-frequency band transmitting circuit supports the signal receiving function of an 863MHz-928MHz frequency band. Preferably, the high-band transmission circuit includes a second reception resonant circuit and a second reception filter circuit; the input end of the second receiving filter circuit is electrically connected with the RF2 end of the fourth radio frequency switch, and the output end of the second receiving filter circuit is electrically connected with the RF2 end of the second radio frequency switch through the second receiving resonant circuit. In this embodiment, the structure of the second receiving resonant circuit may be the same as or different from that of the first receiving resonant circuit, but the structure of the second receiving resonant circuit is set to be the same as that of the first receiving resonant circuit, except that the two structures include different capacitance parameters, as shown in fig. 3, the second receiving resonant circuit includes capacitors C30-C32 and an inductor L12, which will not be described again. The second receiving filter circuit is used for filtering the interference signal, and a conventional low-pass filter can be adopted, which will not be described in detail herein.
And the second radio frequency switch is used for selectively outputting high-frequency band and low-frequency signals, and is matched with the fourth radio frequency switch to form an output switch and an input switch of the receiving link. In this embodiment, the control terminal of the second RF switch is electrically connected to the I/O port of the CPU chip, the output terminal of the first receiving filter circuit is electrically connected to the RF1 terminal of the second RF switch through the first receiving resonant circuit, the output terminal of the second receiving filter circuit is electrically connected to the RF2 terminal of the second RF switch through the second receiving resonant circuit, and the common terminal of the second RF switch is electrically connected to the RF receiving terminal of the Lora chip. In this embodiment, the second rf switch is a switch of the same type as the first rf switch, and the circuit diagram of the second rf switch is the same as the structure of the first rf switch, so the description thereof will not be repeated. The circuit diagram of the second RF switch is shown as U4 in fig. 3, and in this embodiment, the I/O port connecting pin 4 of the second RF switch with the CPU chip is labeled as RF _ SW 2.
In this embodiment, the working principle of the receiving link is as follows: when the Lora module is in a receiving mode, the CPU chip gates the RF2 end of the fifth radio frequency switch, echo signals received by the antenna are input to the second pi-type matching circuit through the fifth radio frequency switch, and are input to the common end of the fourth radio frequency switch after impedance matching is completed through the second pi-type matching circuit; when the edge computing server selects a low frequency band, the CPU chip gates the RF1 end of the fourth radio frequency switch, the echo signal is sent to the low frequency band receiving circuit, the first receiving filter circuit in the low frequency band receiving circuit carries out filtering processing, and the first receiving resonant circuit carries out tuning processing, the CPU chip gates the RF1 end of the second radio frequency switch, and the echo signal passes through the second radio frequency switch and is output to the radio frequency receiving end of the Lora chip;
when the edge computing server selects a high frequency band, the CPU chip gates the RF2 end of the fourth radio frequency switch, the echo signal is sent to the high frequency band receiving circuit, the second receiving filter circuit in the high frequency band receiving circuit carries out filtering processing, and after the second receiving resonant circuit carries out tuning processing, the CPU chip gates the RF2 end of the second radio frequency switch, and the echo signal is output to the radio frequency receiving end of the Lora chip through the second radio frequency switch.
The beneficial effect of this embodiment does: the server is internally provided with a low-frequency-band transmitting circuit, a low-frequency-band receiving circuit, a high-frequency-band transmitting circuit and a high-frequency-band receiving circuit, so that the server is compatible with two frequency bands of 410MHz-510MHz and 863MHz-928MHz, and when the server is used in different regions, the Lora frequency bands are switched and selected to meet the requirements of the Lora frequency bands in different regions, and Lora communication in different regions is realized on the premise of not replacing Lora modules;
the first radio frequency switch and the third radio frequency switch form an input switch and an output switch of a transmitting link, when the Lora module is in a transmitting mode, the first radio frequency switch and the third radio frequency switch can be controlled to perform an alternative operation in low-frequency-band transmission and high-frequency-band transmission, and the integrity of the transmitting link of the server is ensured;
the second radio frequency switch and the fourth radio frequency switch form an input switch and an output switch of a receiving link, when the Lora module is in a receiving mode, the second radio frequency switch and the fourth radio frequency switch can be controlled to perform one of two operations in low-frequency band receiving and high-frequency band receiving, and the integrity of the receiving link of the server is ensured;
the fifth radio frequency switch is arranged at the intersection of the receiving and transmitting links, so that the receiving and transmitting control can be realized, the isolation of the receiving link and the transmitting link is improved, and the receiving link and the transmitting link are ensured not to interfere with each other.
The above description is only a preferred embodiment of the present invention, and should not be taken as limiting the invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides an edge computing server, its includes CPU chip, Lora module and antenna, its characterized in that: the Lora module comprises a Lora chip, a first radio frequency switch, a second radio frequency switch, a third radio frequency switch, a fourth radio frequency switch, a low-frequency band transmitting circuit, a low-frequency band receiving circuit, a high-frequency band transmitting circuit and a high-frequency band receiving circuit;
the Lora chip is electrically connected with the CPU chip through the SPI bus, and the control ends of the first radio frequency switch, the second radio frequency switch, the third radio frequency switch and the fourth radio frequency switch are respectively and correspondingly electrically connected with the I/O ports of the CPU chip one by one;
the radio frequency transmitting end of the Lora chip is electrically connected with the public end of the first radio frequency switch, and the RF1 end and the RF2 end of the first radio frequency switch are respectively electrically connected with the input end of the low-frequency-band transmitting circuit and the input end of the high-frequency-band transmitting circuit; the output end of the low-frequency-band transmitting circuit and the output end of the high-frequency-band transmitting circuit are electrically connected with the RF1 end and the RF2 end of the third radio frequency switch in a one-to-one correspondence manner, and the common end of the third radio frequency switch is electrically connected with the antenna;
the antenna is electrically connected with the common end of the fourth radio frequency switch, the RF1 end and the RF2 end of the fourth radio frequency switch are electrically connected with the input end of the low-frequency band receiving circuit and the input end of the high-frequency band receiving circuit in a one-to-one correspondence mode, the output end of the low-frequency band receiving circuit and the output end of the high-frequency band receiving circuit are electrically connected with the RF1 end and the RF2 end of the second radio frequency switch in a one-to-one correspondence mode, and the common end of the second radio frequency switch is electrically connected with the radio frequency receiving end of the Lora chip.
2. The edge computing server of claim 1, wherein: the frequency band covered by the low-frequency band transmitting circuit and the low-frequency band receiving circuit is 410MHz-510MHz, and the frequency band covered by the high-frequency band transmitting circuit and the high-frequency band receiving circuit is 863MHz-928 MHz.
3. The edge computing server of claim 1, wherein: the low-frequency band transmitting circuit comprises a first transmitting resonant circuit and a first transmitting filter circuit;
the input end of the first transmitting resonant circuit is electrically connected with the RF1 end of the first radio frequency switch, and the output end of the first transmitting resonant circuit is electrically connected with the RF1 end of the third radio frequency switch through the first transmitting filter circuit.
4. An edge compute server as claimed in any one of claims 1 to 3, wherein: the high-band transmitting circuit comprises a second transmitting resonant circuit and a second transmitting filter circuit;
the input end of the second transmitting resonant circuit is electrically connected with the RF2 end of the first radio frequency switch, and the output end of the second transmitting resonant circuit is electrically connected with the RF2 end of the third radio frequency switch through the second transmitting filter circuit.
5. The edge computing server of claim 1, wherein: the low-frequency band receiving circuit comprises a first receiving resonant circuit and a first receiving filter circuit;
the input end of the first receiving filter circuit is electrically connected with the RF1 end of the fourth radio frequency switch, and the output end of the first receiving filter circuit is electrically connected with the RF1 end of the second radio frequency switch through the first receiving resonant circuit.
6. An edge compute server as claimed in claim 1 or 5, wherein: the high-band receiving circuit comprises a second receiving resonant circuit and a second receiving filter circuit;
the input end of the second receiving filter circuit is electrically connected with the RF2 end of the fourth radio frequency switch, and the output end of the second receiving filter circuit is electrically connected with the RF2 end of the second radio frequency switch through the second receiving resonant circuit.
7. The edge computing server of claim 1, wherein: the Lora module further comprises a first pi-type matching circuit, a second pi-type matching circuit and a fifth radio frequency switch;
the common end of the third radio frequency switch is electrically connected with the RF1 end of the fifth radio frequency switch through a first pi-type matching circuit; the common terminal of the fourth radio frequency switch is electrically connected with the RF2 terminal of the fifth radio frequency switch through a second pi-type matching circuit; the common end of the fifth radio frequency switch is electrically connected with the antenna, and the control end of the fifth radio frequency switch is electrically connected with the I/O ports of the CPU chip in a one-to-one correspondence manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120775368.0U CN214480657U (en) | 2021-04-15 | 2021-04-15 | Edge calculation server |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120775368.0U CN214480657U (en) | 2021-04-15 | 2021-04-15 | Edge calculation server |
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| Publication Number | Publication Date |
|---|---|
| CN214480657U true CN214480657U (en) | 2021-10-22 |
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| CN202120775368.0U Active CN214480657U (en) | 2021-04-15 | 2021-04-15 | Edge calculation server |
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2021
- 2021-04-15 CN CN202120775368.0U patent/CN214480657U/en active Active
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Effective date of registration: 20230724 Address after: Room 1, 307, college students entrepreneurship practice (incubation) base, North District, China University of Geosciences (Wuhan), 388 LUMO Road, Hongshan District, Wuhan City, Hubei Province, 430000 Patentee after: WUHAN SUOWEI TECHNOLOGY Co.,Ltd. Address before: Room 1, 307, college students entrepreneurship practice (incubation) base, North District, China University of Geosciences (Wuhan), 388 LUMO Road, Hongshan District, Wuhan City, Hubei Province, 430000 Patentee before: Cao Chunheng |
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