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CN202839599U - Chip-embedded-type three-dimensional wafer-level packaging structure - Google Patents

Chip-embedded-type three-dimensional wafer-level packaging structure Download PDF

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Publication number
CN202839599U
CN202839599U CN201220420567.0U CN201220420567U CN202839599U CN 202839599 U CN202839599 U CN 202839599U CN 201220420567 U CN201220420567 U CN 201220420567U CN 202839599 U CN202839599 U CN 202839599U
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China
Prior art keywords
chip
metal
electrode
layer
wiring
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Expired - Lifetime
Application number
CN201220420567.0U
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Chinese (zh)
Inventor
张黎
陈栋
赖志明
陈锦辉
徐虹
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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Priority to CN201220420567.0U priority Critical patent/CN202839599U/en
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Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector

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  • Wire Bonding (AREA)

Abstract

The utility model relates to a chip-embedded-type three-dimensional wafer-level packaging structure and belongs to the technical field of semiconductor chip packaging. The chip-embedded-type three-dimensional wafer-level packaging structure includes an IC chip I (1), an IC chip II (2), and metal microstructures (3), a high-density wiring layer, a resin layer (6), metal columns (7) and solder ball bumps (9). The IC chip I (1) and the IC chip II (2) are arranged at a lower surface and an upper surface of the high-density wiring layer in a face-to-face manner; a re-wiring wiring metal layer II (8) is arranged in above the IC chip II (2); and signals are transmitted to the solder ball bumps (9) through the metal columns (7). A flip-chip packaging method includes a flip-chip reflow process or a direct hot-press flip-chip process; planarization processing includes a thinning mode and/or a smoothing mode. With the chip-embedded-type three-dimensional wafer-level packaging structure of the utility model adopted, three-dimensional spatial arrangement of a plurality of chips in a packaging body can be realized, and therefore, a signal transmission path can be shortened, signal transmission speed can be accelerated, the dimension of the packaging structure can be reduced, and the promotion of thinned packaging structures can be facilitated.

Description

A kind of chip embedded three-dimensional wafer-level package structure
Technical field
The utility model relates to a kind of chip embedded three-dimensional wafer-level package structure, belongs to the semiconductor die package technical field.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.The development of the encapsulation technology of decades makes high density, undersized encapsulation requirement become the main flow direction of encapsulation.
Along with electronic product develops to thinner, lighter, higher pin density, more low-cost aspect, adopt single chips encapsulation technology can't satisfy industry demand gradually, the Packaging Industry that appears as of a kind of new encapsulation technology---Wafer-Level Packaging Technology provides opportunity to the low-cost package development.In the tradition multi-chip package technology, dialogue between chip and the chip realizes by substrate, be that the chip signal transmission must could arrive an other chip at substrate transmission one circle, even need to arrive on the printed circuit board (PCB) interchange that transmission could realize signal, the power consumption that this has greatly lost the transmission speed of signal and has increased package module is with modern society's theory contradiction of advocating green energy resource.
The multi-chip wafer-level encapsulation method, the mode that it connects up a plurality of chips by reconstruct disk and wafer level again realizes the multi-chip structure encapsulation, finally cuts into single packaging body.But present multi-chip wafer level packaging adopts the two dimensional surface arrangement model more, and number of chips and the encapsulation volume of realization are restricted.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provide a kind of and realize that a plurality of chips realize that in package interior three dimensions arranges, shortens the route of signal transmission, accelerates the chip embedded three-dimensional wafer-level package structure of signaling rate, this encapsulating structure reduces the encapsulation volume of wafer level packaging body simultaneously, is conducive to the propelling of the thin encapsulation in the wafer level packaging.
The purpose of this utility model is achieved in thatA kind of chip embedded three-dimensional wafer-level package structure, it comprises IC chip I with the chip electrode I, with IC chip II, metal micro structure, high-density wiring layer, resin bed and the solder bumps of chip electrode II, described metal micro structure comprises the metal microtrabeculae and is arranged on the metal dimpling point on metal microtrabeculae top.
Described IC chip I and IC chip II are distributed in lower surface and the upper surface of high-density wiring layer face-to-face; described high-density wiring layer comprises again interconnection metal layer I; fill again the dielectric layer and the again wiring metal electrode that is arranged on the upper surface of high-density wiring layer of interconnection metal layer I; described again wiring metal electrode comprises wiring metal electrode I and wiring metal electrode II more again; the lower end of described again interconnection metal layer I is connected with the chip electrode I of IC chip I; the chip electrode II of described IC chip II is connected with wiring metal electrode I again by metal micro structure; between described metal micro structure and the metal micro structure and the outer filler that is arranged with of metal micro structure; the upper surface of described again wiring metal electrode II arranges metal column; described resin bed coats IC chip II; metal column and wiring metal electrode II again; the upper surface of described resin bed arranges again interconnection metal layer II; the upper surface of described again interconnection metal layer II arranges the metal electrode of solder bumps end; the peripheral clad surface protective layer of the metal electrode of described again interconnection metal layer II and solder bumps end, the upper surface of the metal electrode of described solder bumps end arranges solder bumps.
The number of described IC chip II is one or more.
The material of described sealer is resin.
The height of described resin bed surpasses the height of IC chip II.
The height of described metal column surpasses the height of IC chip II.
Described metal column is arranged on the periphery of IC chip II, and becomes array arrangement.
Described again interconnection metal layer II is the single or multiple lift metal level.
[0017] the beneficial effects of the utility model are:
Characteristics of the present utility model are lower surface and upper surfaces that IC chip I and IC chip II are distributed in the high-density wiring layer face-to-face, the number of IC chip II is one or more, the interconnection metal layer II is arranged on the top of IC chip II again, by metal column the packaging body signal is transferred to the solder bumps array.A plurality of chips are arranged at package interior realization three dimensions, have shortened to greatest extent the route of signal transmission, have accelerated the speed of signal transmission, have reduced simultaneously the encapsulation volume of wafer level packaging body, are conducive to the propelling of the thin encapsulation in the wafer level packaging.
Description of drawings
Fig. 1 is the schematic diagram of a kind of chip embedded three-dimensional wafer-level package structure of the utility model.
Fig. 2～Figure 18 is the schematic diagram of a kind of chip embedded three-dimensional wafer-level encapsulation method of the utility model.
Among the figure:
IC disk T1
IC chip I 1
Chip electrode I 11
IC wafer A 202
IC chip II 2
Chip electrode II 21
Metal micro structure 3
Metal microtrabeculae 31
Metal dimpling point 32
The interconnection metal layer I 4 again
Dielectric layer 41
The wiring metal electrode 42 again
Wiring metal electrode I 421 again
Wiring metal electrode II 422 again
Filler 5
Resin bed 6
Resin blind hole 61
Metal column 7
The interconnection metal layer II 8 again
Sealer 81
Solder bumps 9
The metal electrode 91 of solder bumps end.
Embodiment
Referring to Fig. 1, a kind of chip embedded three-dimensional wafer-level package structure of the utility model, comprise IC chip I 1 with chip electrode I 11, with IC chip II 2, metal micro structure 3, high-density wiring layer, resin bed 6 and the solder bumps 9 of chip electrode II 21, described metal micro structure 3 comprises metal microtrabeculae 31 and is arranged on the metal dimpling point 32 on metal microtrabeculae 31 tops.
Described IC chip I 1 and IC chip II 2 are distributed in lower surface and the upper surface of high-density wiring layer face-to-face, and the number of described IC chip II 2 is one or more.
Described high-density wiring layer comprises interconnection metal layer I 4 again, fill the dielectric layer 41 of interconnection metal layer I 4 and be arranged on the again wiring metal electrode 42 of the upper surface of high-density wiring layer again, and described again wiring metal electrode 42 comprises wiring metal electrode I 421 and wiring metal electrode II 422 more again.The lower end of described again interconnection metal layer I 4 is connected with the chip electrode I 11 of IC chip I 1, the chip electrode II 21 of described IC chip II 2 is connected with wiring metal electrode I 421 again by metal micro structure 3, between described metal micro structure 3 and the metal micro structure 3 and the outer filler 5 that is arranged with of metal micro structure 3.The upper surface of described again wiring metal electrode II 422 arranges metal column 7, and the material of described metal column 7 is copper.The height of described metal column 7 surpasses the height of IC chip II 2.Described metal column 7 is arranged on the periphery of IC chip II 2, and becomes array arrangement.
Described resin bed 6 coats IC chip II 2, metal column 7 and wiring metal electrode II 422 again, and the upper surface of described resin bed 6 arranges again interconnection metal layer II 8, and described again interconnection metal layer II 8 is the single or multiple lift metal level.
The upper surface of described again interconnection metal layer II 8 arranges the metal electrode 91 of solder bumps end, the peripheral clad surface protective layer 81 of the metal electrode 91 of described again interconnection metal layer II 8 and solder bumps end, and the material of described sealer 81 is resin.
The upper surface of the metal electrode 91 of described solder bumps end arranges solder bumps 9.
A kind of chip embedded three-dimensional wafer-level encapsulation method comprises following technical process:
Step 1, get the IC disk I T1 with chip electrode I 11.As shown in Figure 2.
Step 2, the mode of utilizing plating, chemical plating or sputter realize again wiring metal cabling I 4 of dielectric layer 41 and inner single or multiple lift thereof at IC disk I T1, and at dielectric layer 41 upper surfaces several again wiring metal electrode I 421 and several wiring metal electrode II 422 again are set, form the high-density wiring layer, the closeness of described again wiring metal electrode I 421 is greater than the closeness of wiring metal electrode II 422 again, and wiring metal electrode II 422 is arranged on the again periphery of wiring metal electrode I 421 again.As shown in Figure 3.
Step 3, get the IC wafer A 202 with chip electrode 21.As shown in Figure 4.
Step 4, realize the metal dimpling point 32 on metal microtrabeculae 31 and metal microtrabeculae 31 tops at chip electrode 21 by techniques such as sputter, photoetching, plating, and formation metal micro structure 3 arrays.Such as Fig. 5, shown in Figure 6.
Step 5, with above-mentioned IC wafer A 202 attenuates and cut into single IC chip II 2.Such as Fig. 7, shown in Figure 8.
Step 6, with above-mentioned IC chip II 2 by metal micro structure 3 upside-down mountings on the again wiring metal electrode I 421 of step 2, described upside-down mounting method comprises that upside-down mounting reflux technique or direct heat overwhelm dress technique.As shown in Figure 9.
Step 7, fill with between the metal micro structure 3 of 5 pairs of above-mentioned encapsulating structures of filler and the metal micro structure 3 and periphery of metal micro structure 3.As shown in figure 10.
Step 8, by sealing or mode of printing forms resin bed 6 at the high-density wiring layer of above-mentioned packaging body, described resin bed 6 coats IC chip II 2 and wiring metal electrode II 422 again, the height of resin bed 6 surpasses the height of IC chip II 2, and resin bed 6 carried out planarization, described planarization comprises attenuate mode and/or leveling mode.As shown in figure 11.
Resin blind hole 61 is offered at step 9, the method corresponding again position of wiring metal electrode II 422 on resin bed 6 that utilizes laser, and described resin blind hole 61 penetrates the resin bed 6 through again upper surfaces of wiring metal electrode II 422.As shown in figure 12.
Step 10, to utilize the mode of sputter, plating, etching that resin blind hole 61 is carried out metal filled, forms metal column 7, and carry out planarization, and described planarization comprises attenuate mode and/or leveling mode.Shown in 13.
Step 11, utilize again Wiring technique to realize the again interconnection metal layer II 8 of above-mentioned resin bed 6 upper surfaces.As shown in figure 14.
Step 12, the mode of utilizing plating, chemical plating or sputter form the array arrangement of the metal electrode 91 of solder bumps end at the upper surface of above-mentioned again interconnection metal layer II 8.As shown in figure 15.
Step 13, form sealers 81 at the metal electrode 91 of the again interconnection metal layer II 8 of above-mentioned packaging body and solder bumps end, expose the metal electrode 91 of solder bumps end.As shown in figure 16.
Step 14, plant ball at the metal electrode 91 of the solder bumps end of above-mentioned packaging body and reflux, form solder bumps 9 arrays.As shown in figure 17.
Step 15, the disk of above-mentioned reconstruct is carried out attenuate, cutting, form single chip embedded three-dimensional wafer-level package structure.As shown in figure 18.

Claims (7)

1. chip embedded three-dimensional wafer-level package structure, described encapsulating structure comprises IC chip I (1), the IC chip II (2) with chip electrode II (21), metal micro structure (3), high-density wiring layer, resin bed (6) and the solder bumps (9) with chip electrode I (11), described metal micro structure (3) comprises metal microtrabeculae (31) and is arranged on the metal dimpling point (32) on metal microtrabeculae (31) top
It is characterized in that: described IC chip I (1) and IC chip II (2) are distributed in lower surface and the upper surface of high-density wiring layer face-to-face; described high-density wiring layer comprises interconnection metal layer I (4) again; fill again the dielectric layer (41) of interconnection metal layer I (4) and be arranged on the again wiring metal electrode (42) of the upper surface of high-density wiring layer; described again wiring metal electrode (42) comprises wiring metal electrode I (421) and wiring metal electrode II (422) more again; the lower end of described again interconnection metal layer I (4) is connected with the chip electrode I (11) of IC chip I (1); the chip electrode II (21) of described IC chip II (2) is connected with wiring metal electrode I (421) again by metal micro structure (3); between described metal micro structure (3) and the metal micro structure (3) and the outer filler (5) that is arranged with of metal micro structure (3); the upper surface of described again wiring metal electrode II (422) arranges metal column (7); described resin bed (6) coats IC chip II (2); metal column (7) and wiring metal electrode II (422) again; the upper surface of described resin bed (6) arranges interconnection metal layer II (8) again; the upper surface of described again interconnection metal layer II (8) arranges the metal electrode (91) of solder bumps end; the peripheral clad surface protective layer (81) of the metal electrode (91) of described again interconnection metal layer II (8) and solder bumps end, the upper surface of the metal electrode of described solder bumps end (91) arranges solder bumps (9).
2. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1 is characterized in that: the number of described IC chip II (2) is one or more.
3. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1, it is characterized in that: the material of described sealer (81) is resin.
4. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1 is characterized in that: the height of described resin bed (6) surpasses the height of IC chip II (2).
5. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1 is characterized in that: the height of described metal column (7) surpasses the height of IC chip II (2).
6. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1 or 5, it is characterized in that: described metal column (7) is arranged on the periphery of IC chip II (2), and becomes array arrangement.
7. a kind of chip embedded three-dimensional wafer-level package structure according to claim 1 is characterized in that: described again interconnection metal layer II (8) is the single or multiple lift metal level.
CN201220420567.0U 2012-08-23 2012-08-23 Chip-embedded-type three-dimensional wafer-level packaging structure Expired - Lifetime CN202839599U (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441085A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating method
CN103762185A (en) * 2013-12-20 2014-04-30 南通富士通微电子股份有限公司 Laminated packaging method for semiconductor
CN104851868A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN104851847A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN104851869A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN105448856A (en) * 2014-09-01 2016-03-30 宏启胜精密电子(秦皇岛)有限公司 Chip package structure, method of making same and chip package substrate
CN109037181A (en) * 2018-07-23 2018-12-18 华进半导体封装先导技术研发中心有限公司 A kind of fan-out packaging structure and its manufacturing method improving warpage
CN110164839A (en) * 2019-05-27 2019-08-23 广东工业大学 A kind of the fan-out package structure and method of high-density line insertion transfer
CN112827516A (en) * 2019-11-22 2021-05-25 富泰华工业（深圳）有限公司 Biological chip packaging structure

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103441085B (en) * 2013-08-28 2015-12-23 江苏长电科技股份有限公司 A kind of flip-chip BGA package method
CN103441085A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating method
CN103762185A (en) * 2013-12-20 2014-04-30 南通富士通微电子股份有限公司 Laminated packaging method for semiconductor
CN104851869B (en) * 2014-02-14 2017-09-22 恒劲科技股份有限公司 Packaging system and preparation method thereof
CN104851869A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN104851847A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN104851868B (en) * 2014-02-14 2017-08-11 恒劲科技股份有限公司 Packaging system and preparation method thereof
CN104851847B (en) * 2014-02-14 2017-09-08 恒劲科技股份有限公司 Packaging system and preparation method thereof
CN104851868A (en) * 2014-02-14 2015-08-19 恒劲科技股份有限公司 Packaging device and manufacturing method therefor
CN105448856A (en) * 2014-09-01 2016-03-30 宏启胜精密电子(秦皇岛)有限公司 Chip package structure, method of making same and chip package substrate
CN105448856B (en) * 2014-09-01 2018-04-06 碁鼎科技秦皇岛有限公司 Chip-packaging structure, preparation method and chip package base plate
CN109037181A (en) * 2018-07-23 2018-12-18 华进半导体封装先导技术研发中心有限公司 A kind of fan-out packaging structure and its manufacturing method improving warpage
CN110164839A (en) * 2019-05-27 2019-08-23 广东工业大学 A kind of the fan-out package structure and method of high-density line insertion transfer
CN112827516A (en) * 2019-11-22 2021-05-25 富泰华工业（深圳）有限公司 Biological chip packaging structure
CN112827516B (en) * 2019-11-22 2023-03-07 富泰华工业（深圳）有限公司 Biological chip packaging structure

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Granted publication date: 20130327