CN202678302U - Fanout-type wafer level chip packaging structure - Google Patents
Fanout-type wafer level chip packaging structure Download PDFInfo
- Publication number
- CN202678302U CN202678302U CN 201220341032 CN201220341032U CN202678302U CN 202678302 U CN202678302 U CN 202678302U CN 201220341032 CN201220341032 CN 201220341032 CN 201220341032 U CN201220341032 U CN 201220341032U CN 202678302 U CN202678302 U CN 202678302U
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- Prior art keywords
- chip
- metal
- wafer level
- type wafer
- silicon
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Micromachines (AREA)
Abstract
The utility model relates to a fanout-type wafer level chip packaging structure, which belongs to the technical field of semiconductor chip package. The fanout-type wafer level chip packaging structure comprises a chip (1), metal microstructures (2), filling material (3), a high-density wiring layer (4), a silicon cavity body (5), a bonding layer (6) and solder ball bumps (7), wherein the chip (1) is inversely mounted on metal electrodes I (421) of the high-density wiring layer (4) through the metal microstructures (2); the silicon cavity body (5) comprises a silicon body (51) and a packaging material layer (52); the silicon cavity body (5) buckles the chip (1) in a silicon cavity (511); the high-density wiring layer (4) is bonded with the silicon cavity body (5) through the bonding layer (6); and the packaging material layer (52) is arranged between the chip (1) and the silicon cavity (511). The fanout-type wafer level chip packaging structure of the utility model is low in packaging cost, the supporting strength of the fanout structure is high, the packaging yield is high, and the fanout-type wafer level chip packaging structure is applicable to the fanout-type wafer level packaging of thin plate structures.
Description
Technical field
The utility model relates to a kind of wafer level chip-packaging structure, belongs to the semiconductor die package technical field.
Background technology
In current semicon industry, Electronic Packaging has become an importance of industry development.The development of the encapsulation technology of decades makes high density, undersized encapsulation requirement become the main flow direction of encapsulation.
Along with electronic product develops to thinner, lighter, higher pin density, more low-cost aspect, adopt single chips encapsulation technology can't satisfy industry demand gradually, the Packaging Industry that appears as of a kind of new encapsulation technology---Wafer-Level Packaging Technology provides opportunity to the low-cost package development.Simultaneously, restricting encapsulation technology is this working ability in tiny electrode pitch aspect of substrate technology to the another one major reason of high density future development, must pass through carrier, such as the ceramic monolith in the organic substrate carrier in the plastic base array package (PBGA) and the ceramic tape ball grid array (CBGA), encapsulation process is finished in the amplification of pair array pitch.
Wafer level fan-out (Fanout) structure, the mode that it connects up by reconstruct disk and wafer level again, the plastic packaging of realization chip fan-out structure finally cuts into single packaging body.But still there is following deficiency in it:
1), chip outside overmolded plastic package material, plastic packaging material is the epoxylite material, its low strength makes the support strength of fan-out (Fanout) structure inadequate, is difficult to use in thin encapsulation;
2), fan-out (Fanout) structure in packaging technology since reconstruct wafer thermal coefficient of expansion much larger than silicon chip, the technical process warpage is larger, but the equipment working ability is lower, yield loss is larger;
3), existing technique is to satisfy low thermal coefficient of expansion, encapsulating resin is comparatively expensive, is unfavorable for the cost degradation of product.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and the fan-out-type wafer level chip package that a kind of packaging cost is low, the support strength of fan-out (Fanout) structure firm, the encapsulation yield is high, be applicable to thin encapsulation is provided.
The purpose of this utility model is achieved in that a kind of fan-out-type wafer level chip-packaging structure, comprise chip, high-density wiring layer and solder bumps, described chip comprises the chip body, the upper surface of described chip body arranges several chip electrodes, described high-density wiring layer comprises dielectric layer and is arranged on the again wiring metal cabling of dielectric layer inside, the two ends of described again wiring metal cabling arrange respectively metal electrode I and metal electrode II, described encapsulating structure also comprises metal micro structure, silicon cavity and bonded layer, described metal micro structure comprises metal column and is arranged on the metal dimpling point of metal column one end, the described metal column other end is connected with chip electrode, the upper surface of described metal electrode I is connected with metal dimpling point, the lower surface of described metal electrode II is connected with solder bumps, and described chip passes through the metal micro structure upside-down mounting on the metal electrode I of high-density wiring layer upper surface;
Described silicon cavity comprises silicon body, and described silicon body is provided with the silicon chamber, and described silicon cavity buckles chip in the silicon chamber, and described high-density wiring layer and silicon cavity arrange between described chip and the silicon chamber and seal the bed of material by the bonded layer bonding.
The vertical section in described silicon chamber is trapezoidal, rectangle or square.
Described encapsulating structure also comprises inserts.
Described inserts is arranged between metal micro structure and the metal micro structure and the peripheral space of metal micro structure.
Described inserts is arranged on the space between chip and the high-density wiring layer.
The described encapsulating material of sealing the bed of material is epoxy resin.
The material of described metal column is copper or copper/nickel clad.
The material of described metal dimpling point is tin or ashbury metal.
Described bonded layer is bonding glue.
The beneficial effects of the utility model are:
Characteristics of the present utility model are that the skin at chip not only is coated with encapsulating resin, and also has a silicon body with the silicon chamber, chip buckles in the silicon chamber with encapsulating resin, scleroid silicon body firmly supports to fan-out (Fanout) structure one, is conducive to the propelling of the thin encapsulation in the wafer level packaging.
Silicon body replaces most of encapsulating resin of original structure, only stays sub-fraction to be filled between chip and the silicon body, has overcome the bad warpage that fan-out (Fanout) structure produces owing to the reconstruct wafer in packaging technology, has improved the yield of product.
Simultaneously, the silicon of low thermal coefficient of expansion replaces the major part of comparatively expensive encapsulating resin, is conducive to reduce the production cost, is fit to the growth requirement of modern industry.
Description of drawings
Fig. 1 is a kind of fan-out-type wafer level of the utility model chip-packaging structure schematic diagram.
Among the figure:
Metal micro structure 2
Metal dimpling point 22
Inserts 3
High-density wiring layer 4
The wiring metal cabling 42 again
Metal electrode I 421
Metal electrode II 422
Seal the bed of material 52
Bonded layer 6
Embodiment
Referring to Fig. 1, a kind of fan-out-type wafer level of the utility model chip-packaging structure, it comprises chip 1, metal micro structure 2, inserts 3, high-density wiring layer 4, silicon cavity 5, bonded layer 6 and solder bumps 7.Described chip 1 comprises chip body 11, and the upper surface of described chip body 11 arranges several chip electrodes 111.Described high-density wiring layer 4 comprises dielectric layer 41 and the again wiring metal cabling 42 that is arranged on dielectric layer 41 inside, and the two ends of described again wiring metal cabling 42 arrange respectively metal electrode I 421 and metal electrode II 422.Described metal micro structure 2 comprises metal column 21 and the metal dimpling point 22 that is arranged on metal column 21 1 ends, and described metal column 21 other ends are connected with chip electrode 111.2 one-tenth array arrangements of described metal micro structure.The material of described metal column 21 is copper or copper/nickel clad, and the material of described metal dimpling point 22 is tin or ashbury metal.
The upper surface of described metal electrode I 421 is connected with metal dimpling point 22, and the lower surface of described metal electrode II 422 is connected with solder bumps 7, and described chip 1 passes through metal micro structure 2 upside-down mountings on the metal electrode I 421 of high-density wiring layer 4 upper surface.Described inserts 3 is arranged between metal micro structure 2 and the metal micro structure 2 and the peripheral space of metal micro structure 2, is full of the space that is arranged between chip 1 and the high-density wiring layer 4.
Described silicon cavity 5 comprises silicon body 51, and described silicon body 51 is provided with silicon chamber 511, and the vertical section in described silicon chamber 511 is trapezoidal, rectangle or square.Described silicon cavity 5 buckles chip 1 in silicon chamber 511, and described high-density wiring layer 4 passes through bonded layer 6 bondings with silicon cavity 5, and described bonded layer 6 is bonding glue.
Arrange between described chip 1 and the silicon chamber 511 and seal the bed of material 52, the described encapsulating material of sealing the bed of material 52 is epoxy resin.
Claims (9)
1. fan-out-type wafer level chip-packaging structure, comprise chip (1), high-density wiring layer (4) and solder bumps (7), described chip (1) comprises chip body (11), the upper surface of described chip body (11) arranges several chip electrodes (111), described high-density wiring layer (4) comprises dielectric layer (41) and is arranged on the inner again wiring metal cabling (42) of dielectric layer (41), the two ends of described again wiring metal cabling (42) arrange respectively metal electrode I (421) and metal electrode II (422), it is characterized in that: described encapsulating structure also comprises metal micro structure (2), silicon cavity (5) and bonded layer (6), described metal micro structure (2) comprises metal column (21) and is arranged on the metal dimpling point (22) of metal column (21) one ends, described metal column (21) other end is connected with chip electrode (111), the upper surface of described metal electrode I (421) is connected with metal dimpling point (22), the lower surface of described metal electrode II (422) is connected with solder bumps (7), and described chip (1) passes through metal micro structure (2) upside-down mounting on the metal electrode I (421) of high-density wiring layer (4) upper surface;
Described silicon cavity (5) comprises silicon body (51), described silicon body (51) is provided with silicon chamber (511), described silicon cavity (5) buckles chip (1) in silicon chamber (511), described high-density wiring layer (4) passes through bonded layer (6) bonding with silicon cavity (5), arranges between described chip (1) and silicon chamber (511) and seals the bed of material (52).
2. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: the vertical section in described silicon chamber (511) is trapezoidal, rectangle or square.
3. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: described encapsulating structure also comprises inserts (3).
4. a kind of fan-out-type wafer level chip-packaging structure according to claim 3, it is characterized in that: described inserts (3) is arranged between metal micro structure (2) and the metal micro structure (2) and the peripheral space of metal micro structure (2).
5. a kind of fan-out-type wafer level chip-packaging structure according to claim 3, it is characterized in that: described inserts (3) is arranged on the space between chip (1) and the high-density wiring layer (4).
6. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: the described encapsulating material of sealing the bed of material (52) is epoxy resin.
7. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: the material of described metal column (21) is copper or copper/nickel clad.
8. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: the material of described metal dimpling point (22) is tin or ashbury metal.
9. a kind of fan-out-type wafer level chip-packaging structure according to claim 1, it is characterized in that: described bonded layer (6) is bonding glue.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220341032 CN202678302U (en) | 2012-07-16 | 2012-07-16 | Fanout-type wafer level chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220341032 CN202678302U (en) | 2012-07-16 | 2012-07-16 | Fanout-type wafer level chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202678302U true CN202678302U (en) | 2013-01-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220341032 Expired - Lifetime CN202678302U (en) | 2012-07-16 | 2012-07-16 | Fanout-type wafer level chip packaging structure |
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| Country | Link |
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| CN (1) | CN202678302U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105874606A (en) * | 2014-01-06 | 2016-08-17 | Mc10股份有限公司 | Encapsulated conformal electronic systems and devices, and methods of making and using the same |
| TWI706478B (en) * | 2018-05-08 | 2020-10-01 | 黃順斌 | Semiconductor package and method of forming the same |
-
2012
- 2012-07-16 CN CN 201220341032 patent/CN202678302U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105874606A (en) * | 2014-01-06 | 2016-08-17 | Mc10股份有限公司 | Encapsulated conformal electronic systems and devices, and methods of making and using the same |
| TWI706478B (en) * | 2018-05-08 | 2020-10-01 | 黃順斌 | Semiconductor package and method of forming the same |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130116 |
|
| CX01 | Expiry of patent term |