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CN209692763U - A kind of OC command communication board based on PXI bus - Google Patents

A kind of OC command communication board based on PXI bus Download PDF

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Publication number
CN209692763U
CN209692763U CN201920717873.2U CN201920717873U CN209692763U CN 209692763 U CN209692763 U CN 209692763U CN 201920717873 U CN201920717873 U CN 201920717873U CN 209692763 U CN209692763 U CN 209692763U
Authority
CN
China
Prior art keywords
interface
processing unit
board based
communication board
pxi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201920717873.2U
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Chinese (zh)
Inventor
祖凌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Junying Electronic Technology Co Ltd
Original Assignee
Shanghai Junying Electronic Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Junying Electronic Technology Co Ltd filed Critical Shanghai Junying Electronic Technology Co Ltd
Priority to CN201920717873.2U priority Critical patent/CN209692763U/en
Application granted granted Critical
Publication of CN209692763U publication Critical patent/CN209692763U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a kind of OC command communication board based on PXI bus, including onboard storage system, timer manager, embedded central processing unit CPU, programmable logic array FPGA and OC interface, the embedded central processing unit CPU is separately connected onboard storage system, timer manager, programmable logic array FPGA and OC interface, OC interface is also connected with external OC input, the beneficial effects of the utility model are: (1) Highgrade integration.Integration degree is high for communication card, small in size, can integral installation inside portable industrial pc, occupy little space;(2) standard interface is used.Communication card is powered using external 12V DC, can be directly connected to PXI case back plate and be taken electricity, and without being individually equipped with AC-DC power module, compatible computer motherboard most of on the market is extremely easy to use.

Description

A kind of OC command communication board based on PXI bus
Technical field
The utility model relates to field of communication technology, specifically a kind of OC command communication board based on PXI bus.
Background technique
In recent years, with the fast development of space technology, the integration degree of satellite single machine is higher and higher, and volume is also more next It is smaller, the growth of the throughput of function and communication data that each single machine in satellite subsystem undertakes also exponentially type.Wherein Communication port based on OC interface is one of the main thoroughfare of sending and receiving data inside satellite single machine, and each single machine is due to function Difference, internal timing and logic state do not form unified standard, generally require to be equipped with different surveys for different single machines Test plate (panel) card.And have the development cycle long, the disadvantages of hardware cost is high, and volume is big, and integration is bad.
Utility model content
The purpose of this utility model is to provide a kind of OC command communication board based on PXI bus, to solve the back The problem of being proposed in scape technology.
In order to achieve the object, the utility model provides the following technical solutions:
A kind of OC command communication board based on PXI bus, including onboard storage system, timer manager, it is embedded in Central Processing Unit CPU, programmable logic array FPGA and OC interface, the embedded central processing unit CPU are separately connected plate Storage system, timer manager, programmable logic array FPGA and OC interface are carried, OC interface is also connected with external OC input.
It as a further solution of the present invention, further include RS432 communication module, the connection of RS432 communication module is embedding Enter formula central processing unit CPU.
The embedded central processing unit CPU communicates mould by RS432 as a further solution of the present invention, Block connects computer.
PXI agreement is also connected on the programmable logic array FPGA as a further solution of the present invention, Bus.
It as a further solution of the present invention, further include on-line debugging interface, interface form MINI_USB.
Compared with prior art, the utility model has the beneficial effects that (1) Highgrade integration.The integrated journey of communication card Degree is high, small in size, can integral installation inside portable industrial pc, occupy little space;(2) standard interface is used.Communication board Card is powered using external 12V DC, can be directly connected to PXI case back plate and be taken electricity, simultaneous without being individually equipped with AC-DC power module Hold most of computer motherboard on the market, it is extremely easy to use;(3) accurate monitoring.Communication card supports RS232 communication interface, It controls computer and passes through matched monitoring programme, the current power supply system working condition of energy accurate perception, onboard temperature, logic mistake Accidentally, interface voltage, which transfinites, waits safety protection functions;(4) online change.Communication card has remote debugging interface, in inconvenience The test site of mobile product can remotely carry out online programming and again programming configuration item.
Detailed description of the invention
A kind of OC command communication board block diagram based on PXI bus of Fig. 1.
Specific embodiment
The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.
Embodiment 1: referring to Fig. 1, a kind of OC command communication board based on PXI bus, including onboard storage system, when Clock manager, embedded central processing unit (CPU), the simulation of programmable logic array (FPGA) and embedded OS are defended Star communication card (OC interface);Board can simulate related satellite single machine in the interface and logic of subsystem internal communication completely Sequence;Have self-checking function and failure protection function, can sufficiently ensure the safety of equipment under test.
The OC command communication board of OC command communication board based on PXI bus can be convenient insertion standard testing cabinet, And by way of in line writing hardware program, the various customized parameters of analog satellite single machine and the program of logic, thus quickly Build satellite single machine test and fault simulation system.
Board is based on 32 PXI buses, and dominant frequency clock 33MHz can be carried out at high speed the human-computer interaction of data.Communication board cartoon It crosses onboard CPU and FPGA and logical process and Interface Expanding is carried out to data, when the corresponding command signal of satellite or data-signal are logical When crossing OC interface and being received by board.FPGA will pre-process data, and pulse-width or logical sequence are adjusted, then It is sent into CPU and carries out encoding and decoding.CPU is compared after reading the real time clock data in Clock management system with system clock, Then the data handled well are stamped into timing code, and host computer procedure is passed to by PXI bus and is recorded.Host computer receives It carries out analyzing and being communicated with the board of remaining type after to the data of communication card, forms the joint test system of satellite single machine System.
Communication card there are mainly two types of function, first is that the OC interface instruction signal of satellite single machine output is received, to arteries and veins Width detect and record to command adapted thereto number and pulse number, to accidentally instructing, emits instruction and carries out implementation monitoring;Second is that right Communication function carries out logic function simulation and sequential coupling.
Product function:
1) pulse width detection function:
Pulse width detection range: 1us-1s;
Pulsewidth precision: 1us;
Filtering setting: 1us-1ms;
Upper pull-up voltage: 5V;
2) bus communication function:
3 kinds of communication patterns: the transmitting-receiving of three signal PCM datas, the transmitting-receiving of two signal datas, asynchronous data transmitting-receiving;
Port number 32, mode can freely be set;
Each road timing is adjustable, phase shift stepping: 1ms;
Signal rate: 1K--2Mbps;
Isolation voltage: 1500VDC;
Included short-circuit protection;
Meet PCI2.2 specification, compatible 5V and 3.3V PCI bus protocol;
False alarm, type of error can be defined by the user, such as CRC check mistake, frame length mistake.
It is in place of embodiment 2, with the difference of embodiment 1, further includes RS432 communication module, the connection of RS432 communication module Embedded central processing unit CPU.Embedded central processing unit CPU connects computer by RS432 communication module.It can be accurate Current power supply system working condition, onboard temperature, logic error are grasped, interface voltage, which transfinites, waits safety protection functions.
It is obvious to a person skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and And without departing substantially from the spirit or essential attributes of the utility model, it can realize that this is practical new in other specific forms Type.Therefore, in all respects, the present embodiments are to be considered as illustrative and not restrictive, this is practical new The range of type is indicated by the appended claims rather than the foregoing description, it is intended that containing for the equivalent requirements of the claims will be fallen in All changes in justice and range are embraced therein.It should not treat any reference in the claims as limiting Related claim.
In addition, it should be understood that although this specification is described in terms of embodiments, but not each embodiment is only wrapped Containing an independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should It considers the specification as a whole, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art The other embodiments being understood that.

Claims (5)

1. a kind of OC command communication board based on PXI bus, including onboard storage system, timer manager, embedded center Processing unit CPU, programmable logic array FPGA and OC interface, which is characterized in that the embedded central processing unit CPU point Onboard storage system, timer manager, programmable logic array FPGA and OC interface are not connected, and it is defeated that OC interface is also connected with external OC Enter.
2. a kind of OC command communication board based on PXI bus according to claim 1, which is characterized in that further include RS432 communication module, RS432 communication module connect embedded central processing unit CPU.
3. a kind of OC command communication board based on PXI bus according to claim 2, which is characterized in that the insertion Formula central processing unit CPU connects computer by RS432 communication module.
4. a kind of OC command communication board based on PXI bus according to claim 1, which is characterized in that described to compile PXI protocol bus is also connected on journey logic array FPGA.
5. a kind of OC command communication board based on PXI bus according to claim 1 to 4, which is characterized in that also Including online debugging interface, interface form MINI_USB.
CN201920717873.2U 2019-05-20 2019-05-20 A kind of OC command communication board based on PXI bus Expired - Fee Related CN209692763U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201920717873.2U CN209692763U (en) 2019-05-20 2019-05-20 A kind of OC command communication board based on PXI bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201920717873.2U CN209692763U (en) 2019-05-20 2019-05-20 A kind of OC command communication board based on PXI bus

Publications (1)

Publication Number Publication Date
CN209692763U true CN209692763U (en) 2019-11-26

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Application Number Title Priority Date Filing Date
CN201920717873.2U Expired - Fee Related CN209692763U (en) 2019-05-20 2019-05-20 A kind of OC command communication board based on PXI bus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113885368A (en) * 2021-08-26 2022-01-04 航天东方红卫星有限公司 Integrated testing shelter for pico-nano satellite

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113885368A (en) * 2021-08-26 2022-01-04 航天东方红卫星有限公司 Integrated testing shelter for pico-nano satellite
CN113885368B (en) * 2021-08-26 2023-07-28 航天东方红卫星有限公司 Integrated test shelter for pico-nano satellite

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20191126

Termination date: 20200520

CF01 Termination of patent right due to non-payment of annual fee