CN209104143U - Encapsulating structure - Google Patents
Encapsulating structure Download PDFInfo
- Publication number
- CN209104143U CN209104143U CN201822232712.2U CN201822232712U CN209104143U CN 209104143 U CN209104143 U CN 209104143U CN 201822232712 U CN201822232712 U CN 201822232712U CN 209104143 U CN209104143 U CN 209104143U
- Authority
- CN
- China
- Prior art keywords
- layer
- interlayer
- antenna stack
- connection structure
- encapsulated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Details Of Aerials (AREA)
Abstract
The utility model provides a kind of encapsulating structure, comprising: re-wiring layer；Bottom connection structure is formed in the upper surface of re-wiring layer；Bottom encapsulated layer covers re-wiring layer and bottom connection structure；Interlayer antenna stack is formed in the upper surface of bottom encapsulated layer and part and covers bottom encapsulated layer；Buffer layer is formed in the upper surface of interlayer antenna stack, coats interlayer antenna stack；Top layer connection structure is formed in the upper surface of buffer layer；Top layer encapsulated layer covers buffer layer and top layer connection structure；Top layer antenna stack is formed in the upper surface of top layer encapsulated layer.The utility model improves the binding performance between each encapsulated layer, reduces the risk of encapsulated layer delamination, improve product yield by introducing the buffer layer being set between encapsulated layer.In addition, the stress encapsulated in layer formation process to interlayer antenna stack can also be reduced by being introduced into buffer layer, the integrality of interlayer antenna stack is ensured that.
Description
Technical field
The utility model relates to technical field of semiconductor encapsulation, more particularly to a kind of encapsulating structure.
Background technique
Fan-out package is a kind of embedded chip packaging method of wafer level processing, is had input/output end port (I/O)
The preferable feature of more, integrated flexibility.Fan-out-type wafer-level packaging has the advantage that compared to conventional wafer-level packaging
1, I/O spacing is flexible, independent of chip size；2, it only uses effective bare die (die), product yield improves；3, have flexible
3D package path, it can top formed General Cell figure；4, there is preferable electrical property and hot property；5, it can be used
In frequency applications；6, high-density wiring is realized by re-wiring layer (RDL).
Currently, in the stacked antenna construction packages technical process of fan-out package, after forming one layer of antenna wiring layer,
It generally requires and forms encapsulated layer using packing material, be then further continued for forming the antenna wiring layer on upper layer on encapsulated layer, so
Repeatedly, to form multi-ply linear construction packages layer.However, under the conditions of existing packaging technology, the encapsulation of each layer antenna structure
It is easy to lead to the problem of delamination occur because binding performance is bad between layer.In addition, being adopted during forming encapsulated layer
It is also easy to make packed antenna wiring layer that deformation occurs under the action of stress with the moulding process such as injection molding or lamination, Jin Erying
Ring product yield.
Therefore, it is necessary to propose a kind of new encapsulating structure, solve the above problems.
Utility model content
In view of the foregoing deficiencies of prior art, it the purpose of this utility model is to provide a kind of encapsulating structure, is used for
Solve the problems, such as that the encapsulated layer of each layer antenna structure in the prior art is easy to appear delamination.
To achieve the above object and other related purposes, the utility model provide a kind of encapsulating structure, which is characterized in that
Include:
Re-wiring layer, including opposite the upper surface and the lower surface；
Bottom connection structure is formed in the upper surface of the re-wiring layer, is electrically connected with the re-wiring layer；
Bottom encapsulated layer, covers the re-wiring layer and the bottom connection structure and exposes the bottom and connect knot
The top of structure；
Interlayer antenna stack is formed in the upper surface of the bottom encapsulated layer and partially covers the bottom encapsulated layer, described
Interlayer antenna stack and the bottom connection structure are electrically connected；
Buffer layer is formed in the upper surface of the interlayer antenna stack, coats the interlayer antenna stack；
Top layer connection structure is formed in the upper surface of the buffer layer, and passes through the buffer layer and the interlayer antenna
Layer is electrically connected；
Top layer encapsulated layer covers the buffer layer and the top layer connection structure and exposes the top layer connection structure
Top；
Top layer antenna stack, is formed in the upper surface of the top layer encapsulated layer, and the top layer antenna stack is connect with the top layer
Structure is electrically connected.
As a kind of optinal plan of the utility model, the buffer layer includes polyimide layer, layer of silica gel or asphalt mixtures modified by epoxy resin
One of rouge layer.
As a kind of optinal plan of the utility model, the encapsulating structure further includes being located under the re-wiring layer
Surface, and the metal coupling and semiconductor chip being electrically connected with the re-wiring layer.
As a kind of optinal plan of the utility model, the re-wiring layer includes at least one layer of metal wiring layer and packet
Wrap up in the dielectric layer of the metal wiring layer.
As a kind of optinal plan of the utility model, exposure is formed on the dielectric layer of the re-wiring layer
The dielectric layer openings region of the metal wiring layer out, the bottom connection structure are described comprising being welded in using bonding wire craft
Metal contact wires on metal wiring layer.
As a kind of optinal plan of the utility model, it is formed on the buffer layer and exposes the interlayer antenna stack
Buffer layer open area, the top layer connection structure include to be welded in the company of the metal on the interlayer antenna stack using bonding wire craft
Wiring.
As a kind of optinal plan of the utility model, the interlayer antenna stack is N layers, on the N layers of interlayer antenna stack
Under be intervally arranged；The buffer layer is N layers, and the buffer layer being located on the same floor coats the interlayer antenna stack；The encapsulation
Structure further include:
N layer by layer between encapsulated layer, the interlayer encapsulated layer coats the buffer layer being located on the same floor；Wherein, N be greater than etc.
In 2 integer；
N layer by layer between connection structure, be located in the interlayer encapsulated layer, and be electrically connected interlayer antenna described in adjacent two layers
Layer；
The one end of the bottom connection structure far from the re-wiring layer and the interlayer antenna stack electricity for being located at bottom
Property connection；The one end of the top layer connection structure far from the top layer antenna stack and the interlayer antenna stack for being located at top layer are electrical
Connection.
As a kind of optinal plan of the utility model, it is formed on the buffer layer and exposes the interlayer antenna stack
Open area, the interlayer connection structure include to be welded in the metal contact wires on the interlayer antenna stack using bonding wire craft.
As described above, the utility model provides a kind of encapsulating structure, by introducing the buffering being set between encapsulated layer
Layer, improves the binding performance between each encapsulated layer, reduces the risk of encapsulated layer delamination, improve product yield.This
Outside, the stress encapsulated in layer formation process to interlayer antenna stack can also be reduced by being introduced into the buffer layer, ensured that
The integrality of interlayer antenna stack.
Detailed description of the invention
Each step that Fig. 1 to Figure 13 is shown as the preparation method of the encapsulating structure provided in the utility model embodiment one is shown
It is intended to.
Figure 14 is shown as the schematic diagram of the encapsulating structure with metal connecting column provided in the utility model embodiment one.
Figure 15 is shown as showing for the encapsulating structure with three layers of antenna metal layer provided in the utility model embodiment one
It is intended to.
Component label instructions
001 support substrate
001a releasing layer
101 re-wiring layers
101a metal wiring layer
101b dielectric layer
102 bottom connection structures
103 bottom encapsulated layers
104 interlayer antenna stacks
105 buffer layers
106 top layer connection structures
107 top layer encapsulated layers
108 top layer antenna stacks
109 interlayer connection structures
110 interlayer encapsulated layers
111 metal couplings
111a metal connecting column
112 semiconductor chips
112a chip filled layer
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands the further advantage and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 1 is please referred to Figure 15.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model, though it is only shown with related component in the utility model rather than when according to actual implementation in diagram
Component count, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout form may also be increasingly complex.
Embodiment one
Fig. 1 to Figure 15 is please referred to, the utility model provides a kind of preparation method of encapsulating structure, which is characterized in that packet
Include following steps:
As shown in Figure 1, providing a support substrate 001；
As shown in Fig. 2, forming re-wiring layer 101 in the support substrate 001；
As shown in figure 5, forming bottom connection structure 102 and bottom encapsulated layer in the upper surface of the re-wiring layer 101
103, the bottom connection structure 102 is electrically connected with the re-wiring layer 101, and the bottom encapsulated layer 103 covers described
Re-wiring layer 101 and the bottom connection structure 102 and the top for exposing the bottom connection structure 102；
As shown in fig. 6, forming part in the upper surface of the bottom encapsulated layer 103 covers the bottom encapsulated layer 103
Interlayer antenna stack 104, the interlayer antenna stack 104 are electrically connected with the bottom connection structure 102；
As shown in fig. 6, forming buffer layer in the upper surface of the bottom encapsulated layer 103 and the interlayer antenna stack 104
105, the buffer layer 105 coats the interlayer antenna stack 104；
As shown in figure 9, top layer connection structure 106 and top layer encapsulated layer 107 are formed in the upper surface of the buffer layer 105,
The top layer connection structure 106 passes through the buffer layer 105 and is electrically connected with the interlayer antenna stack 104, the top layer encapsulation
Layer 107 covers the buffer layer 105 and the top layer connection structure 106 and the top for exposing the top layer connection structure 106；
As shown in Figure 10, top layer antenna stack 108, the top layer antenna are formed in the upper surface of the top layer encapsulated layer 107
Layer 108 is electrically connected with the top layer connection structure 106.
As an example, as shown in figure 9, the material for constituting the buffer layer 105 includes polyimides, silica gel or epoxy resin
One of, formed the buffer layer 105 technique include compression forming, Transfer molding, fluid-tight molding, vacuum lamination or
One of spin coating.Optionally, in the present embodiment, material of the polyimide material as the buffer layer 105 is selected, is passed through
Spin coating proceeding makes the polyimide material be evenly covered on the bottom encapsulated layer 103 and the interlayer antenna stack 104
Upper surface, and coat the interlayer antenna stack 104.As shown in figure 9, improving the bottom by introducing the buffer layer 105
Binding performance between encapsulated layer 103 and the top layer encapsulated layer 107, prevents delamination.In addition, coating the interlayer
The buffer layer 105 of antenna stack 104 can also be reduced when forming the top layer encapsulated layer 107, to the interlayer antenna stack
Stress caused by 104, it is therefore prevented that deformation caused by stress, it is ensured that the integrality of the interlayer antenna stack 104.
As an example, the material for constituting the bottom encapsulated layer 103 and the top layer encapsulated layer 107 include polyimides,
One of silica gel or epoxy resin, the technique for forming the bottom encapsulated layer 103 and the top layer encapsulated layer 107 includes compression
One of molding, Transfer molding, fluid-tight molding, vacuum lamination or spin coating.Optionally, the bottom encapsulated layer is being chosen
103 and the top layer encapsulated layer 107 material and moulding process when, can be integrated in conjunction with the material of the buffer layer 105
It considers, to ensure that the Coating combination performance of encapsulated layer can be improved in the introduced buffer layer 105, prevents interlayer and open
It splits.For example, the bottom encapsulated layer 103 and the top layer encapsulated layer 107 select epoxide resin material to be pressed in the present embodiment
Contracting moulding process, the buffer layer 105 selects polyimide material to carry out spin coating proceeding, to ensure that encapsulated layer Coating combination is good
Without cracking, and production cycle and production cost are combined.
As an example, the encapsulating structure includes fan-out-type antenna packages structure；The interlayer antenna stack 104 and the top
Layer antenna stack 108 includes antenna metal layer.In the present embodiment, the preparation method of the encapsulating structure is sealed applied to fan-out-type antenna
Assembling structure, the interlayer antenna stack 104 and the top layer antenna stack 108 include antenna metal layer.In fan-out-type antenna packages work
In skill, in order to improve antenna efficiency and reduce antenna occupied space, is had become and had much using the technique of stacked antenna encapsulating structure
The solution of prospect.However, between each antenna packages layer again be easy to appear because binding performance is bad crack the phenomenon that.
The utility model is directed to the stacked antenna encapsulating structure of fan-out-type antenna packages structure, introduces the buffer layer 105, improves
The Coating combination performance of encapsulated layer, the phenomenon that so as to improve delamination.Optionally, formed the interlayer antenna stack 104 or
The material of the shown antenna metal layer of the top layer antenna stack 108 include one or both of copper, aluminium, nickel, gold, silver, titanium with
Upper combination；The technique for depositing the interlayer antenna stack 104 or the top layer antenna stack 108 includes chemical vapor deposition and physics gas
It mutually deposits, the patterned interlayer antenna stack 104 or the top layer antenna is formed by lithography and etching technique after deposit
Layer 108；Or can also first pass through and be lithographically formed patterned photoetching offset plate figure, then carry out chemical vapor deposition or physics gas
It mutually deposits, the region for covering photoresist will not deposit the interlayer antenna stack 104 or the top layer antenna stack 108, with reality
It is now graphical.
As an example, as shown in Fig. 2, the re-wiring layer 101 includes at least one layer metal wiring layer 101a and package
The dielectric layer 101b of the metal wiring layer 101a.Optionally, formed the metal wiring layer 101a material include copper,
The combination of one or more of aluminium, nickel, gold, silver, titanium；Formed the dielectric layer 101b material include epoxy resin,
Silica gel, polyimides, PBO, BCB, silica, phosphorosilicate glass, the combination of one or more of fluorine-containing glass.Described in deposition
The technique of metal wiring layer 101a includes chemical vapor deposition process, evaporation process, sputtering technology, electroplating technology or chemical plating work
Skill forms the patterned metal wiring layer 101a by lithography and etching technique after deposit；Form the dielectric layer
The technique of 101b includes chemical vapor deposition process or physical gas-phase deposition.By being repeatedly formed the metal wiring layer
The re-wiring layer 101 of 101a and the available multilayered structure of dielectric layer 101b.
As an example, as shown in Fig. 2, the re-wiring layer 101 is formed in a support substrate 001.In the present embodiment
In, the re-wiring layer 101 is formed in a support substrate 001, and each layer day is then formed on the re-wiring layer 101
Line layer structure.It is the re-wiring layer 101 and each layer antenna stack formed thereon by introducing the support substrate 001
Provide the support with stabilizing mechanical intensity, it is therefore prevented that the deformation and break that encapsulating structure is likely to occur due to not having and stablizing and support
Damage.Optionally, the support substrate 001 includes glass substrate, metal substrate, semiconductor substrate, polymer substrate and ceramic liner
One of bottom.In the present embodiment, it is glass substrate that the support substrate 001, which is selected, and cost is relatively low for the glass substrate, holds
It easily is formed on its surface releasing layer 001a, and reduces the difficulty of subsequent separating technology.
As an example, further including removing the branch after forming the top layer antenna stack 108 as shown in Figure 10 to Figure 13
Substrate 001 is supportted, it is convex to form the metal that is electrically connected with the re-wiring layer 101 in the lower surface of the re-wiring layer 101
Block 111, and the step of the lower surface of the re-wiring layer 101 is electrically connected semiconductor chip 112.In the present embodiment,
After obtaining the re-wiring layer 101 and each layer antenna stack formed thereon, by the way that it is divided with the support substrate 001
From to expose the lower surface of the re-wiring layer 101, and in lower surface formation and the re-wiring layer 101
The metal coupling 111 of electric connection, and semiconductor chip 112 is electrically connected in the lower surface of the re-wiring layer 101.Specifically
Ground, as shown in Figure 10, the re-wiring layer 101 and each layer antenna stack formed thereon are located in the support substrate 001；
As shown in figure 11, the support substrate 001 and the re-wiring layer 101 are separated；As shown in figure 12, it is described again
Open area is formed on the dielectric layer 101b of the lower surface of wiring layer 101, exposes the metal wiring layer 101a；Such as
Shown in Figure 13, the metal coupling 111 and the semiconductor core are electrically connected on the metal wiring layer 101a exposed
Piece 112.Optionally, the method for forming the open area includes carrying out photoetching and quarter to the dielectric layer 101b of lower surface
Etching technique；The metal coupling 111 includes one of tin solder, silver solder and gold-tin eutectic solder；The semiconductor chip
112 include antenna circuit chip.As shown in figure 14, in the other embodiments of the utility model, the metal coupling is being formed
Before 111, metal connecting column 111a can also be first formed on the metal wiring layer 101a, then in the metal connecting column
The metal coupling 111 is formed on 111a.By forming the metal connecting column 111a, the metal coupling is effectively reduced
111 occupied space increases wiring density, and reduces the risk that short circuit occurs between each metal coupling 111, described
Metal connecting column 111a includes the metal columns connection structure such as copper post or nickel column.Optionally, as shown in figure 13, by the semiconductor
It further include in the semiconductor chip 112 and the rewiring after chip 112 and the re-wiring layer 101 are electrically connected
The step of chip filled layer 112a is filled in gap between layer 101, to improve the semiconductor chip 112 and the cloth again
The bond strength of line layer 101, and protect the engaging portion of the semiconductor chip 112 and the re-wiring layer 101.The chip
The material of filled layer 112a includes polyimides, silica gel or epoxy resin etc..
As an example, forming the rewiring in the support substrate 001 shown in as shown in Figure 1, Figure 2, Figure 10 and Figure 11
Before layer 101, further include the steps that first forming releasing layer 001a in the support substrate 001, the re-wiring layer 101 is logical
It crosses the releasing layer 001a and is adhered to the support substrate 001；When removing the support substrate 001, by being released described in reduction
The viscosity for putting layer 001a separates the support substrate 001 with the re-wiring layer 101.As shown in Figure 1, providing the support
Substrate 001, and releasing layer 001a is formed in the support substrate 001.Optionally, the releasing layer 001a uses spin coating first
Technique is coated on 101 surface of support substrate, then makes its curing molding using ultra-violet curing or heat curing process.It is described to release
Putting a layer 001a includes LTHC optical-thermal conversion material layer (LTHC, light to heat conversion).As shown in Fig. 2, institute
It states and continuously forms the structures such as the re-wiring layer 101 on upper layer on releasing layer 001a.As shown in Figure 10 to Figure 11, it is based on laser
The LTHC optical-thermal conversion material layer is heated, the LTHC optical-thermal conversion material layer is made to lose viscosity, so that described heavy
New route layer 101 and the support substrate 001 are separated from each other from the LTHC optical-thermal conversion material layer.In the utility model
In other embodiments, the releasing layer 001a can also select other that can lose the material of viscosity under the process conditions such as photo-thermal
Material.
As an example, as shown in Figures 2 to 5, the bottom connection structure 102 includes metal contact wires, the bottom is formed
The technique of layer connection structure 102 includes bonding wire craft, forms the bottom connection structure 102 and the bottom encapsulated layer 103
Step includes:
As shown in Fig. 2, forming open region in the partial region of the dielectric layer 101b of the re-wiring layer 101
Domain, and expose the metal wiring layer 101a below the open area；Optionally, the open area is formed
Method includes the lithography and etching technique to the dielectric layer 101b；
As shown in figure 3, one end of the metal contact wires is welded in described in the open area using bonding wire craft
On metal wiring layer 101a, the other end extends upwards；Optionally, the bonding wire craft includes hot pressing bonding wire craft, ultrasonic wave
One of bonding wire craft and thermosonic bonding wire craft；The material of the metal contact wires includes in gold, silver, copper or aluminium
It is a kind of；It is after one end of the metal contact wires is welded on the metal wiring layer 101a, the metal contact wires are upward
Fang Yanshen, and cut off in the other end, and the top that the more metal contact wires are cut off is maintained at the same horizontal plane；
As shown in figure 4, forming bottom encapsulated layer 103 on the re-wiring layer 101, the bottom encapsulated layer 103 is wrapped
Cover the metal contact wires；The method for forming the bottom encapsulated layer 103 include compression forming, Transfer molding, fluid-tight at
One of type, vacuum lamination and spin coating, the material for forming the bottom encapsulated layer 103 includes polyimides, silica gel and ring
One of oxygen resin；
As shown in figure 5, grinding to the bottom encapsulated layer 103, and expose the top of the metal contact wires.
As an example, as shown in Figures 6 to 9, the top layer connection structure 106 includes metal contact wires, the top is formed
The technique of layer connection structure 106 includes bonding wire craft, forms the top layer connection structure 106 and the top layer encapsulated layer 107
Step includes:
As shown in fig. 6, forming buffer layer 105 in the upper surface of the bottom encapsulated layer 103 and the interlayer antenna stack 104
Afterwards, open area is formed in the partial region of the buffer layer 105, and exposes the layer below the open area
Between antenna stack 104；Optionally, the method for forming the open area includes the lithography and etching technique to the buffer layer 105；
As shown in fig. 7, one end of the metal contact wires is welded in described in the open area using bonding wire craft
On interlayer antenna stack 104, the other end extends upwards；Optionally, the bonding wire craft includes hot pressing bonding wire craft, supersonic welding
One of Wiring technology and thermosonic bonding wire craft；The material of the metal contact wires includes one in gold, silver, copper or aluminium
Kind；After one end of the metal contact wires is welded on the interlayer antenna stack 104, the metal contact wires are prolonged upwards
It stretches, and is cut off in the other end, and the top that the more metal contact wires are cut off is maintained at the same horizontal plane；
As shown in figure 8, forming top layer encapsulated layer 107 on the buffer layer 105, the top layer encapsulated layer 107 coats institute
State metal contact wires；The method for forming the top layer encapsulated layer 107 includes compression forming, Transfer molding, fluid-tight molding, true
One of dead level pressure and spin coating, the material for forming the top layer encapsulated layer 107 includes polyimides, silica gel and epoxy resin
One of；
As shown in figure 9, grinding to the top layer encapsulated layer 107, and expose the top of the metal contact wires.
It should be pointed out that being to introduce the bonding wire craft of the metal contact wires as metal used by the utility model
Connection structure then forms the process flow that encapsulated layer coats the metal contact wires.Compared to being initially formed encapsulated layer then aperture
And the process flow of metal is filled, the side wall of the obtained metal connecting structure of the utility model is more smooth, will not be because of opening
Hole leads to sidewall roughness.For antenna structure, would not occur causing because of the coarse burr of metal connecting structure side wall
Aerial signal interference and decaying, to improve product yield.
As an example, as shown in figure 15, as the optinal plan of the utility model, the interlayer antenna stack 104 can be with
Interval setting multilayer repeatedly, to form stacked antenna encapsulating structure.N layers of institute are formed in the upper surface of the bottom encapsulated layer 103
State interlayer antenna stack 104, wherein N is the integer more than or equal to 2；N layers of institute are formed in the upper surface of the bottom encapsulated layer 103
The step of stating interlayer antenna stack 104 the following steps are included:
A) the interlayer antenna that part covers the bottom encapsulated layer 103 is formed in the upper surface of the bottom encapsulated layer 103
Layer 104, the interlayer antenna stack 104 are electrically connected with the bottom connection structure 102；
B) upper surface of the interlayer antenna stack 104 formed in the previous step forms buffer layer 105, the buffer layer
The interlayer antenna stack 104 formed in 105 cladding previous steps；
C) upper surface of the buffer layer 105 formed in the previous step forms interlayer connection structure 109 and interlayer envelope
Fill layer 110, the interlayer connection structure 109 through the interlayer encapsulated layer 110 and be located at previous step in formed described in
The interlayer antenna stack 104 in buffer layer 105 is electrically connected, and the interlayer encapsulated layer 110 covers the buffer layer 105 and institute
It states interlayer connection structure 109 and exposes the top of the interlayer connection structure 109；
D) upper surface of the interlayer encapsulated layer 110 formed in the previous step formed it is another layer by layer between antenna stack 104；
E) step b)~d is repeated) N-1 times.
For example, shown in fig.15 is that constituted stacked antenna is arranged by two layers of interval of interlayer antenna stack 104
Encapsulating structure introduces three layers of antenna metal layer altogether in the stacked antenna encapsulating structure in addition the top layer antenna stack 108,
Board area shared by antenna will be greatly decreased in this, effectively promotion antenna efficiency.Certainly, in other embodiment party of the utility model
In case, by further increasing the quantity of the interlayer antenna stack 104, it can also obtain with four layers or four layers or more antenna gold
Belong to the stacked antenna encapsulating structure of layer.
As an example, the interlayer connection identical as the bottom connection structure 102 and the top layer connection structure 106
Structure 109 includes metal contact wires, and the technique for forming the interlayer connection structure 109 includes bonding wire craft, forms the interlayer
The step of connection structure 109 and interlayer encapsulated layer 110 includes:
After the upper surface of the interlayer antenna stack 104 forms buffer layer 105, in the partial region of the buffer layer 105
Buffer layer open area is formed, and exposes the interlayer antenna stack 104 below the buffer layer open area；
Described in one end of the metal contact wires is welded in below the buffer layer open area using bonding wire craft
On interlayer antenna stack 104, the other end extends upwards；
Interlayer encapsulated layer 110 is formed on the buffer layer 105, the interlayer encapsulated layer 110 coats the metal connection
Line；
The interlayer encapsulated layer 110 is ground, and exposes the top of the metal contact wires.
Optionally, the bonding wire craft includes hot pressing bonding wire craft, supersonic welding Wiring technology and thermosonic bonding wire work
One of skill；The material of the metal contact wires includes one of gold, silver, copper or aluminium.
Embodiment two
A kind of encapsulating structure is present embodiments provided, as shown in figure 13, comprising:
Re-wiring layer 101, including opposite the upper surface and the lower surface；
Bottom connection structure 102 is formed in the upper surface of the re-wiring layer 101, with 101 electricity of re-wiring layer
Property connection；
Bottom encapsulated layer 103 covers the re-wiring layer 101 and the bottom connection structure 102 and exposes described
The top of bottom connection structure 102；
Interlayer antenna stack 104 is formed in the upper surface of the bottom encapsulated layer 103 and partially covers the bottom encapsulated layer
103, the interlayer antenna stack 104 is electrically connected with the bottom connection structure 102；
Buffer layer 105 is formed in the upper surface of the interlayer antenna stack 104, coats the interlayer antenna stack 104；
Top layer connection structure 106, is formed in the upper surface of the buffer layer 105, and pass through the buffer layer 105 with it is described
Interlayer antenna stack 104 is electrically connected；
Top layer encapsulated layer 107 covers the buffer layer 105 and the top layer connection structure 106 and exposes the top layer
The top of connection structure 106；
Top layer antenna stack 108, is formed in the upper surface of the top layer encapsulated layer 107, the top layer antenna stack 108 with it is described
Top layer connection structure 106 is electrically connected.
As an example, the buffer layer 105 includes one of polyimide layer, layer of silica gel or epoxy resin layer.At this
In encapsulating structure provided by embodiment, by introducing the buffer layer 105, improve the bottom encapsulated layer 103 with it is described
Binding performance between top layer encapsulated layer 107, prevents delamination.In addition, coating the described of the interlayer antenna stack 104
Buffer layer 105 can also be reduced when forming the top layer encapsulated layer 107, to stress caused by the interlayer antenna stack 104, be prevented
Deformation caused by stress is stopped, it is ensured that the integrality of the interlayer antenna stack 104.
As an example, the bottom encapsulated layer 103 and the top layer encapsulated layer 107 include polyimide layer, layer of silica gel or
One of epoxy resin layer.In the present embodiment, the bottom encapsulated layer 103 and the top layer encapsulated layer 107 select asphalt mixtures modified by epoxy resin
Rouge material carries out compressing and forming process, and the buffer layer 105 selects polyimide material to carry out spin coating proceeding, to ensure encapsulated layer
Coating combination has combined production cycle and production cost well without cracking.
As an example, the encapsulating structure includes fan-out-type antenna packages structure；The interlayer antenna stack 104 and the top
Layer antenna stack 108 includes antenna metal layer.In the present embodiment, the encapsulating structure is applied to fan-out-type antenna packages structure, leads to
It crosses and introduces the buffer layer 105, improve the Coating combination performance of encapsulated layer, the phenomenon that so as to improve delamination.It can
Selection of land, formed the interlayer antenna stack 104 or the top layer antenna stack 108 material include copper, aluminium, nickel, gold, silver, in titanium
One or more combination.
As an example, the re-wiring layer 101 includes at least one layer metal wiring layer 101a and the package hardware cloth
The dielectric layer 101b of line layer 101a.Optionally, formed the metal wiring layer 101a material include copper, aluminium, nickel, gold, silver,
The combination of one or more of titanium；The material for forming the dielectric layer 101b includes epoxy resin, silica gel, polyamides Asia
Amine, PBO, BCB, silica, phosphorosilicate glass, the combination of one or more of fluorine-containing glass.
As an example, the encapsulating structure further includes the lower surface positioned at the re-wiring layer 101, and with it is described again
The metal coupling 111 and semiconductor chip 112 that wiring layer 101 is electrically connected.Optionally, the metal coupling 111 includes soldering
One of material, silver solder and gold-tin eutectic solder；The semiconductor chip 112 includes antenna circuit chip.As shown in figure 14,
In the other embodiments of the utility model, it is also formed with metal connecting column 111a on the metal wiring layer 101a, passes through
The metal connecting column 111a is connected to the metal coupling 111.By introducing the metal connecting column 111a, efficiently reduce
The occupied space of the metal coupling 111, increases wiring density, and reduce and occur between each metal coupling 111
The risk of short circuit, the metal connecting column 111a includes the metal columns connection structure such as copper post or nickel column.Optionally, such as Figure 13 institute
Show, chip filled layer 112a is also filled in the gap between the semiconductor chip 112 and the re-wiring layer 101.Institute
Stating chip filled layer 112a can be improved the bond strength of the semiconductor chip 112 and the re-wiring layer 101, and protect
The engaging portion of the semiconductor chip 112 and the re-wiring layer 101.The material of the chip filled layer 112a includes polyamides
Imines, silica gel or epoxy resin etc..
The hardware cloth is exposed as an example, being formed on the dielectric layer 101b of the re-wiring layer 101
The open area of line layer 101a, the bottom connection structure 102 include that the institute of the open area is welded in using bonding wire craft
State the metal contact wires on metal wiring layer 101a.Optionally, the material of the metal contact wires includes in gold, silver, copper or aluminium
One kind；After one end of the metal contact wires is welded on the metal wiring layer 101a, by the metal contact wires to
Top extends, and cuts off in the other end, and the top that the more metal contact wires are cut off is maintained at the same horizontal plane.
As an example, the open area for exposing the interlayer antenna stack 104 is formed on the buffer layer 101b, it is described
Top layer connection structure 104a includes to be welded in the metal contact wires on the interlayer antenna stack 104 using bonding wire craft.Optionally,
The material of the metal contact wires includes one of gold, silver, copper or aluminium；One end of the metal contact wires is welded in described
After on interlayer antenna stack 104, the metal contact wires are extended upwards, and cut off in the other end, and the more metals connect
The top that wiring is cut off is maintained at the same horizontal plane.
As an example, as shown in figure 15, the interlayer antenna stack 104 is N layers, and the N layers of interlayer antenna stack 104 are between the upper and lower
Every arrangement；The buffer layer 105 is N layers, and the buffer layer 105 being located on the same floor coats the interlayer antenna stack 104；It is described
Encapsulating structure further include:
N layer by layer between encapsulated layer 110, the interlayer encapsulated layer 110 coats the buffer layer 105 being located on the same floor；Wherein,
N is the integer more than or equal to 2；
N layer by layer between connection structure 109, be located in the interlayer encapsulated layer 110, and be electrically connected interlayer described in adjacent two layers
Antenna stack 104；
The one end of the bottom connection structure 102 far from the re-wiring layer 101 and the interlayer day for being located at bottom
Line layer 104 is electrically connected；The one end of the top layer connection structure 106 far from the top layer antenna stack 108 and the institute for being located at top layer
State the electric connection of interlayer antenna stack 104.As the optinal plan of the utility model, the interlayer antenna stack 104 can also be repeatedly
Multilayer is formed, to constitute stacked antenna encapsulating structure.Shown in fig.15 be made of two layers of interlayer antenna stack 104
Stacked antenna encapsulating structure three layers of day are introduced in the stacked antenna encapsulating structure altogether in addition the top layer antenna stack 108
Line metal layer, board area shared by antenna will be greatly decreased in this, effectively promotion antenna efficiency.
As an example, as shown in figure 15, being formed on the buffer layer 105 and exposing opening for the interlayer antenna stack 104
Mouth region domain, the interlayer connection structure 109 include to be welded in the connection of the metal on the interlayer antenna stack 104 using bonding wire craft
Line.
In conclusion the utility model provides a kind of encapsulating structure, the encapsulating structure includes: re-wiring layer, packet
Include opposite the upper surface and the lower surface；Bottom connection structure is formed in the upper surface of the re-wiring layer, with the cloth again
Line layer is electrically connected；Bottom encapsulated layer covers the re-wiring layer and the bottom connection structure and exposes the bottom
The top of connection structure；Interlayer antenna stack is formed in the upper surface of the bottom encapsulated layer and partially covers the bottom encapsulation
Layer, the interlayer antenna stack and the bottom connection structure are electrically connected；Buffer layer is formed in the upper table of the interlayer antenna stack
Face coats the interlayer antenna stack；Top layer connection structure is formed in the upper surface of the buffer layer, and passes through the buffer layer
It is electrically connected with the interlayer antenna stack；Top layer encapsulated layer covers the buffer layer and the top layer connection structure and exposes
The top of the top layer connection structure；Top layer antenna stack is formed in the upper surface of the top layer encapsulated layer, the top layer antenna stack
It is electrically connected with the top layer connection structure.The utility model is improved by introducing the buffer layer being set between encapsulated layer
Binding performance between each encapsulated layer reduces the risk of encapsulated layer delamination, improves product yield.In addition, by drawing
The stress encapsulated in layer formation process to interlayer antenna stack can also be reduced by entering the buffer layer, ensure that interlayer antenna stack
Integrality.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (8)
1. a kind of encapsulating structure characterized by comprising
Re-wiring layer, including opposite the upper surface and the lower surface；
Bottom connection structure is formed in the upper surface of the re-wiring layer, is electrically connected with the re-wiring layer；
Bottom encapsulated layer covers the re-wiring layer and the bottom connection structure and exposes the bottom connection structure
Top；
Interlayer antenna stack is formed in the upper surface of the bottom encapsulated layer and partially covers the bottom encapsulated layer, the interlayer
Antenna stack and the bottom connection structure are electrically connected；
Buffer layer is formed in the upper surface of the interlayer antenna stack, coats the interlayer antenna stack；
Top layer connection structure is formed in the upper surface of the buffer layer, and passes through the buffer layer and interlayer antenna stack electricity
Property connection；
Top layer encapsulated layer covers the buffer layer and the top layer connection structure and the top for exposing the top layer connection structure
Portion；
Top layer antenna stack is formed in the upper surface of the top layer encapsulated layer, the top layer antenna stack and the top layer connection structure
It is electrically connected.
2. encapsulating structure according to claim 1, it is characterised in that: the buffer layer includes polyimide layer, layer of silica gel
Or one of epoxy resin layer.
3. encapsulating structure according to claim 1, it is characterised in that: the encapsulating structure further includes being located at the cloth again
The lower surface of line layer, and the metal coupling and semiconductor chip being electrically connected with the re-wiring layer.
4. encapsulating structure according to claim 1, it is characterised in that: the re-wiring layer includes at least one layer of hardware cloth
Line layer and the dielectric layer for wrapping up the metal wiring layer.
5. encapsulating structure according to claim 4, it is characterised in that: shape on the dielectric layer of the re-wiring layer
At there is the dielectric layer openings region for exposing the metal wiring layer, the bottom connection structure includes to be welded using bonding wire craft
The metal contact wires being connected on the metal wiring layer.
6. encapsulating structure according to claim 1, it is characterised in that: be formed on the buffer layer and expose the interlayer
The buffer layer open area of antenna stack, the top layer connection structure include to be welded on the interlayer antenna stack using bonding wire craft
Metal contact wires.
7. encapsulating structure according to claim 1, it is characterised in that: the interlayer antenna stack is N layers, the N layers of interlayer
Antenna stack is intervally arranged up and down；The buffer layer is N layers, and the buffer layer being located on the same floor coats the interlayer antenna stack；
The encapsulating structure further include:
N layer by layer between encapsulated layer, the interlayer encapsulated layer coats the buffer layer being located on the same floor；Wherein, N is more than or equal to 2
Integer；
N layer by layer between connection structure, be located in the interlayer encapsulated layer, and be electrically connected interlayer antenna stack described in adjacent two layers；
The one end of the bottom connection structure far from the re-wiring layer electrically connects with the interlayer antenna stack for being located at bottom
It connects；The one end of the top layer connection structure far from the top layer antenna stack electrically connects with the interlayer antenna stack for being located at top layer
It connects.
8. encapsulating structure according to claim 7, it is characterised in that: be formed on the buffer layer and expose the interlayer
The open area of antenna stack, the interlayer connection structure include to be welded in the metal on the interlayer antenna stack using bonding wire craft
Connecting line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822232712.2U CN209104143U (en) | 2018-12-28 | 2018-12-28 | Encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822232712.2U CN209104143U (en) | 2018-12-28 | 2018-12-28 | Encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209104143U true CN209104143U (en) | 2019-07-12 |
Family
ID=67163523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822232712.2U Active CN209104143U (en) | 2018-12-28 | 2018-12-28 | Encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209104143U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727934A (en) * | 2018-12-28 | 2019-05-07 | 中芯长电半导体（江阴）有限公司 | Encapsulating structure and preparation method thereof |
-
2018
- 2018-12-28 CN CN201822232712.2U patent/CN209104143U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727934A (en) * | 2018-12-28 | 2019-05-07 | 中芯长电半导体（江阴）有限公司 | Encapsulating structure and preparation method thereof |
| CN109727934B (en) * | 2018-12-28 | 2024-05-31 | 盛合晶微半导体(江阴)有限公司 | Packaging structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10784232B2 (en) | Semiconductor package and fabricating method thereof | |
| CN206992089U (en) | Semiconductor device | |
| CN105225965B (en) | A kind of fan-out package structure and preparation method thereof | |
| CN105140213B (en) | A kind of chip-packaging structure and packaging method | |
| CN109860136A (en) | It is integrated to be fanned out to packaging part and forming method thereof | |
| CN105118823A (en) | Stacked type chip packaging structure and packaging method | |
| CN105070671A (en) | Chip encapsulation method | |
| CN109285828A (en) | Fan-out-type antenna packages structure with air chamber and preparation method thereof | |
| CN107248509A (en) | The chip-packaging structure and method for packing of EMI protection | |
| CN107452702A (en) | The encapsulating structure and method for packing of semiconductor chip | |
| CN107611045A (en) | A kind of three-dimensional chip encapsulating structure and its method for packing | |
| KR102373804B1 (en) | Semiconductor package and fabricating method thereof | |
| CN107195551A (en) | Fan-out-type laminated packaging structure and preparation method thereof | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN208986176U (en) | Antenna packages structure | |
| CN109727934A (en) | Encapsulating structure and preparation method thereof | |
| CN109755227A (en) | Encapsulating structure and preparation method thereof | |
| CN209104143U (en) | Encapsulating structure | |
| US20230065844A1 (en) | Semiconductor package and method of manufacturing the same | |
| CN110137157A (en) | Semiconductor package and preparation method thereof | |
| CN110957284A (en) | Three-dimensional packaging structure of chip and packaging method thereof | |
| TWI441312B (en) | A three dimensional chip stacking electronic package with bonding wires | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN207250493U (en) | A kind of three-dimensional chip encapsulating structure | |
| CN207852667U (en) | Fan-out-type antenna packages structure with electromagnetic protection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
|
| CP03 | Change of name, title or address |