CN110137157A - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
- Publication number
- CN110137157A CN110137157A CN201910476812.6A CN201910476812A CN110137157A CN 110137157 A CN110137157 A CN 110137157A CN 201910476812 A CN201910476812 A CN 201910476812A CN 110137157 A CN110137157 A CN 110137157A
- Authority
- CN
- China
- Prior art keywords
- layer
- antenna
- wiring
- semiconductor package
- plastic packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000004033 plastic Substances 0.000 claims abstract description 71
- 229920003023 plastic Polymers 0.000 claims abstract description 71
- 238000004806 packaging method and process Methods 0.000 claims abstract description 70
- 239000000463 material Substances 0.000 claims description 77
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 23
- 239000011521 glass Substances 0.000 claims description 19
- 239000000919 ceramic Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 7
- 230000005611 electricity Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000004744 fabric Substances 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 8
- 239000010410 layer Substances 0.000 description 330
- 238000000034 method Methods 0.000 description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 239000010949 copper Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 239000004642 Polyimide Substances 0.000 description 12
- 229920001721 polyimide Polymers 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- 239000003822 epoxy resin Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 208000037998 chronic venous disease Diseases 0.000 description 10
- 239000000741 silica gel Substances 0.000 description 10
- 229910002027 silica gel Inorganic materials 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000004528 spin coating Methods 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 7
- 229920002577 polybenzoxazole Polymers 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 239000004411 aluminium Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 5
- 229910052731 fluorine Inorganic materials 0.000 description 5
- 239000011737 fluorine Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000013047 polymeric layer Substances 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The present invention provides a kind of semiconductor package and preparation method thereof, and semiconductor package includes: re-wiring layer；Chip, back bonding is in the lower surface of re-wiring layer；Electric connection structure, positioned at the upper surface of re-wiring layer；Plastic packaging layer, positioned at the upper surface of re-wiring layer, and by electric connection structure plastic packaging；First antenna layer, positioned at the upper surface of plastic packaging layer；Frame structure positioned at the upper surface of plastic packaging layer, and is located at the periphery of first antenna layer；Cover board, positioned at the top of frame structure；Second antenna stack, positioned at the lower surface of cover board；Soldered ball convex block, positioned at the lower surface of re-wiring layer.Semiconductor package of the invention can effectively reduce the volume of encapsulating structure, improve the integrated level of device；And transmission signal path is shorter in semiconductor package of the invention, available better electrical property and antenna performance.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of semiconductor package and its preparation side
Method.
Background technique
In existing antenna mobile phone terminal applies, antenna transmission and reception signal are needed by multiple functional module (examples
Such as, active component and passive element) and antenna go to be composed, the way of traditional encapsulating structure be by each functional module and
Antenna assemblies are on pcb board.And each functional module and antenna are arranged on the surface of pcb board in above structure, can occupy pcb board compared with
Big area so that entire encapsulating structure there are the routes of transmission signal longer, electrical property and antenna performance is poor, power consumption is larger and
The problems such as encapsulation volume is larger.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of semiconductor package and its
Preparation method, route for solving transmission signal existing for encapsulating structure in the prior art is longer, electrical property and antenna performance compared with
Difference, the problems such as power consumption is larger and encapsulation volume is larger.
In order to achieve the above objects and other related objects, the present invention provides a kind of semiconductor package, the semiconductor
Encapsulating structure includes:
Re-wiring layer；
Chip, back bonding are electrically connected in the lower surface of the re-wiring layer, and with the re-wiring layer；
Electric connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and by the electric connection structure plastic packaging；
First antenna layer is connected positioned at the upper surface of the plastic packaging layer, and with the electric connection structure；
Frame structure positioned at the upper surface of the plastic packaging layer, and is located at the periphery of the first antenna layer；
Cover board, positioned at the top of the frame structure；
Second antenna stack has spacing positioned at the lower surface of the cover board, and with the first antenna layer；
Soldered ball convex block is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
Optionally, the re-wiring layer includes:
It is routed dielectric layer, positioned at the upper surface of the sacrificial layer；
Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes what Spaced was arranged
Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal wire
Layer electrical connection.
Optionally, the re-wiring layer further include:
Seed layer is located in the wiring dielectric layer, and is electrically connected with the metallic stacked structure；
Capsulation material layer is located in the wiring dielectric layer, and is located at the lower surface of the seed layer；
Bottom dielectric layer, positioned at the lower surface of the wiring dielectric layer.
Optionally, the frame structure includes resinous framework structure, metal framework structure or ceramic frame configuration；The lid
Plate includes glass cover-plate.
Optionally, the first antenna layer includes several first antennas, second antenna stack include several second
Antenna, the first antenna are correspondingly arranged up and down one by one with second antenna.
Optionally, there is active component and passive element in the chip.
Optionally, the semiconductor package further includes Underfill layer, and the Underfill layer is located at the chip
Between the re-wiring layer.
In order to achieve the above objects and other related objects, the present invention also provides a kind of preparation sides of semiconductor package
The preparation method of method, the semiconductor package includes the following steps:
Substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
Re-wiring layer is formed in the upper surface of the sacrificial layer；
Electric connection structure, the electric connection structure and the re-wiring layer are formed in the upper surface of the re-wiring layer
Electrical connection；
Plastic packaging layer is formed in the upper surface of the re-wiring layer, the plastic packaging layer is by the electric connection structure plastic packaging；
First antenna layer is formed in the upper surface of the plastic packaging layer, the first antenna layer is electrically connected with the electric connection structure
It connects；
Frame structure is formed in the upper surface of the plastic packaging layer, the frame structure is located at the outer of the first antenna layer
It encloses；
Cover board is provided, a surface of the cover board is formed with the second antenna stack；The cover board is bonded to the frame knot
The top of structure, second antenna stack is located at the lower surface of the cover board after bonding, and has spacing with the first antenna layer；
Remove the substrate and the sacrificial layer；
Chip is provided, the flip-chip is bonded to the lower surface of the re-wiring layer, the chip with it is described heavy
New route layer, which is realized, to be electrically connected；
Soldered ball convex block is formed in the lower surface of the re-wiring layer, the soldered ball convex block is electrically connected with the re-wiring layer
It connects.
Optionally, the upper surface of Yu Suoshu sacrificial layer forms the re-wiring layer and includes the following steps:
Bottom dielectric layer is formed in the upper surface of the sacrificial layer；
Capsulation material layer is formed in the upper surface of the bottom dielectric layer；
Seed layer is formed in the upper surface of the capsulation material layer；
Processing is patterned to the seed layer and the capsulation material layer；
Wiring dielectric layer and metallic stacked structure, the metallic stacked structure are formed in the upper surface of the bottom dielectric layer
In the wiring dielectric layer, and it is electrically connected with the seed layer；The metallic stacked structure includes what Spaced was arranged
Metal line layer and metal plug, the metal plug is between the adjacent metal line layer, by the adjacent metal wire
Layer electrical connection.
Optionally, the frame structure of formation includes resinous framework structure, metal framework structure portion or ceramic frame knot
Structure；The cover board provided includes glass cover-plate.
Optionally, the upper surface of Yu Suoshu plastic packaging layer forms the first antenna layer and includes the following steps:
First antenna material layer is formed in the upper surface of the plastic packaging layer；
Perform etching to the first antenna material layer includes described the of multiple first antennas being intervally arranged to obtain
One antenna stack；
Second antenna stack is formed in a surface of the cover board to include the following steps:
The second antenna material layer is formed in a surface of the cover board；
Perform etching to the second antenna material layer includes described the of multiple the second antennas being intervally arranged to obtain
Two antenna stacks；
The first antenna is correspondingly arranged up and down one by one with second antenna.
Optionally, the flip-chip is bonded to the lower surface of the re-wiring layer further includes later in the chip
And the step of Underfill layer is formed between the re-wiring layer.
As described above, semiconductor package and preparation method thereof of the invention, has the advantages that of the invention
Semiconductor package is by that can effectively reduce encapsulating structure for plastic packaging above and below first antenna layer, the second antenna stack and chip
Volume, improve the integrated level of device；By integrating in the chip active component and passive element, envelope can be further decreased
The volume of assembling structure further increases the integrated level of device；Only have air insulated between first antenna layer and the second antenna stack, it is empty
The dielectric loss of gas is minimum, can reduce the loss of signal of first antenna layer and the second antenna stack, and semiconductor package of the invention
Transmission signal path is shorter in assembling structure, available better electrical property and antenna performance.
Detailed description of the invention
Fig. 1 is shown as the flow chart of the preparation method of the semiconductor package provided in the embodiment of the present invention one.
Fig. 2 to 15 is shown as each step institute in the preparation method of the semiconductor package provided in the embodiment of the present invention one
Obtain the cross section structure schematic diagram of structure；Wherein, Figure 15 is shown as the semiconductor package provided in the embodiment of the present invention two
Cross section structure schematic diagram.
Component label instructions
10 substrates
11 sacrificial layers
12 re-wiring layers
121 bottom dielectric layers
122 capsulation material layers
123 seed layers
124 wiring dielectric layers
125 metallic stacked structures
126 openings
13 electric connection structures
14 plastic packaging layers
15 first antenna layers
151 first antennas
16 frame structures
17 cover boards
18 second antenna stacks
181 second antennas
19 soldered ball convex blocks
20 air chambers
21 chips
22 Underfill layers
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 15.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
Referring to Fig. 1, the present invention provides a kind of preparation method of semiconductor package, the semiconductor package
Preparation method includes the following steps:
1) substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
2) upper surface of Yu Suoshu sacrificial layer forms re-wiring layer；
3) upper surface of Yu Suoshu re-wiring layer forms electric connection structure, the electric connection structure and the rewiring
Layer electrical connection；
4) upper surface of Yu Suoshu re-wiring layer forms plastic packaging layer, and the plastic packaging layer is by the electric connection structure plastic packaging；
5) upper surface of Yu Suoshu plastic packaging layer forms first antenna layer, the first antenna layer and electric connection structure electricity
Connection；
6) upper surface of Yu Suoshu plastic packaging layer forms frame structure, and the frame structure is located at the outer of the first antenna layer
It encloses；
7) cover board is provided, a surface of the cover board is formed with the second antenna stack；The cover board is bonded to the frame
The top of structure, second antenna stack is located at the lower surface of the cover board after bonding, and between having with the first antenna layer
Away from；
8) substrate and the sacrificial layer are removed；
9) chip is provided, the flip-chip is bonded to the lower surface of the re-wiring layer, the chip with it is described
Re-wiring layer, which is realized, to be electrically connected；
10) lower surface of Yu Suoshu re-wiring layer forms soldered ball convex block, the soldered ball convex block and the re-wiring layer
Electrical connection.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, substrate 10, the upper surface shape of Yu Suoshu substrate 10 are provided
At sacrificial layer 11.
As an example, the material of the substrate 10 can be in silicon, glass, silica, ceramics, polymer and metal
A kind of material or two or more composite materials, shape can be round, rectangular or other any required shapes.Preferably,
In the present embodiment, the material of the substrate 10 is glass, i.e., the described substrate 10 is preferably substrate of glass.
As an example, the sacrificial layer 11 separating layer as re-wiring layer and the substrate 10 in the subsequent process,
It preferably selects the jointing material with smooth finish surface to be made, and must have certain binding force with the re-wiring layer,
In addition, it also has stronger binding force, in general, the combination of the sacrificial layer 11 and the substrate 10 with the substrate 10
Power need to be greater than the binding force with the re-wiring layer.
As an example, the sacrificial layer 11 may include polymeric layer, band-like adhesion layer or photothermal conversion (LTHC) layer；Tool
Body, the material of the sacrificial layer 11 can be selected from two-sided adhesive tape (for example, chip coherent film or the non-conductive film for all having viscosity
Etc.) or pass through the adhesive glue etc. that spin coating proceeding makes；Preferably, in the present embodiment, the sacrificial layer 11 is preferably UV adhesive tape,
It is easy to pull off after UV light (ultraviolet light) irradiation；Certainly, in other examples, the sacrificial layer 11 can also select object
The other materials layer that physical vapor deposition method or chemical vapour deposition technique are formed, such as epoxy resin (Epoxy), silicon rubber
(silicone rubber), polyimides (PI), polybenzoxazoles (PBO), benzocyclobutene (BCB) etc., in later separation institute
When stating substrate 10, the methods of wet etching, chemical mechanical grinding can be used and remove the sacrificial layer 11.
As an example, the sacrificial layer 11 can also be formed by automatic pasting technique.
In step 2), the S2 step and Fig. 3 to Fig. 5 in Fig. 1 are please referred to, the upper surface of Yu Suoshu sacrificial layer 11 forms weight
New route layer 12.
As an example, the upper surface of Yu Suoshu sacrificial layer 11 forms the re-wiring layer 12 and may include in step 2)
Following steps:
2-1) upper surface of Yu Suoshu sacrificial layer 11 forms bottom dielectric layer 121, as shown in Figure 3；
2-2) upper surface of Yu Suoshu bottom dielectric layer 121 forms capsulation material layer 122, as shown in Figure 3；
2-3) upper surface of Yu Suoshu capsulation material layer 122 forms seed layer 123, as shown in Figure 3；
Processing 2-4) is patterned to the seed layer 123 and the capsulation material layer 122, as shown in Figure 4；Specifically
Processing can be patterned to the seed layer 123 and the capsulation material layer 122 using lithographic etch process；
2-5) upper surface of Yu Suoshu bottom dielectric layer 121 forms wiring dielectric layer 124 and metallic stacked structure 125, institute
It states metallic stacked structure 125 to be located in the wiring dielectric layer 124, and is electrically connected with the seed layer 123, as shown in Figure 5；Institute
State the metal line layer (not indicating) and metal plug (not indicating) that metallic stacked structure 125 includes Spaced arrangement, institute
Metal plug is stated between the adjacent metal line layer, the adjacent metal line layer is electrically connected.
As an example, the material of the bottom dielectric layer 121 may include low k dielectric.Specifically, described second is situated between
The material of matter layer 20 may include using in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
A kind of material；The bottom dielectric layer 121 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the material of the capsulation material layer 122 may include but be not limited only to polyimides, silica gel or epoxy
Resin etc..
The seed layer 123 is formed as an example, can use but be not limited only to sputtering technology；The seed layer 123
Material may include at least one of Ti (titanium) and Cu (copper)；Specifically, the seed layer 123 can be titanium layer, it can also be with
For layers of copper, or the laminated construction of titanium layer and layers of copper can also be CTB alloy layer.
As an example, the material of the wiring dielectric layer 124 may include low k dielectric.As an example, the wiring
Dielectric layer 124 can be using one of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass material
Material, and the wiring dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind material or two or more combined materials.
In step 3), S3 step and Fig. 6 in Fig. 1 are please referred to, the upper surface of Yu Suoshu re-wiring layer 12 forms electricity
Connection structure 13, the electric connection structure 13 are electrically connected with the re-wiring layer 12.
As an example, institute can be formed in the upper surface of the re-wiring layer 12 using routing technique or column bonding technology
State electric connection structure 13；The electric connection structure 13 may include bonding wire or conductive column.
As an example, the quantity of the electric connection structure 13 can be set according to actual needs, only with signal in Fig. 6
Four electric connection structures 13 are as an example, in actual example out, the quantity of the electric connection structure 13 not as
Limit.
In step 4), the S4 step and Fig. 7 to Fig. 8 in Fig. 1, the upper surface shape of Yu Suoshu re-wiring layer 12 are please referred to
At plastic packaging layer 14, the plastic packaging layer 14 is by 13 plastic packaging of electric connection structure.
As an example, molded underfill technique, coining moulding technology, transfer modling work can be used but is not limited only to
The upper surface that skill, hydraulic seal plastic package process, vacuum lamination process or spin coating proceeding are equal to the re-wiring layer 12 forms institute
State plastic packaging layer 14；Preferably, in the present embodiment, using molded underfill technique in the upper surface shape of the re-wiring layer 12
At the plastic packaging layer 14.The plastic packaging layer 14 is formed using molded underfill technique, the plastic packaging layer 14 can be smooth and fast
The gap between the electric connection structure 13 is filled up fastly, it is possible to prevente effectively from there is interface debonding；And molded underfill work
Skill will not be restricted as capillary underfill technique in the prior art, greatly reduced technology difficulty, be can be used for
Smaller joint gap, is more suitable for stacked structure.
As an example, the material of the plastic packaging layer 14 may include but be not limited only to polymer-based material, resin-based materials,
Polyimides, silica gel or epoxy resin etc..
As an example, the upper surface for the plastic packaging layer 14 being initially formed can be higher than the top of the electric connection structure 13
Portion is also needed to execute the plastic packaging layer 14 is carried out thinned work as shown in fig. 7, at this point, after forming the plastic packaging layer 14
Skill, specifically, can use but be not limited only to chemical mechanical milling tech the plastic packaging layer 14 is carried out it is thinned so that retain
The top flush of the upper surface of the plastic packaging layer 14 and the electric connection structure 13, as shown in Figure 8.Certainly, in other examples
In, top flush of the upper surface for the plastic packaging layer 14 being initially formed i.e. with the electric connection structure 13, as shown in figure 8,
Thinned technique is carried out to the plastic packaging layer 14 at this point, can then save.
In step 5), S5 step and Fig. 9 in Fig. 1 are please referred to, the upper surface of Yu Suoshu plastic packaging layer 14 is formed first day
Line layer 15, the first antenna layer 15 are electrically connected with the electric connection structure 13.
As an example, forming the first antenna layer 15 in the upper surface of the plastic packaging layer 14 may include steps of:
5-1) upper surface of Yu Suoshu plastic packaging layer 14 forms first antenna material layer (not shown)；
5-2) perform etching to the first antenna material layer includes multiple first antennas 151 being intervally arranged to obtain
The first antenna layer 15；The i.e. described first antenna layer 15 may include several first antennas 151；Several described first day
Line 151 can be and adjacent described in arbitrary shape arrangement (for example, be arranged in array etc.) in the upper surface of the plastic packaging layer 14
There is spacing between first antenna 151.The quantity of the first antenna 151 can be according to practical need in the first antenna layer 15
Set, in Figure 10 only with the first antenna layer 15 include four first antennas 151 as an example, actually showing
In example, the quantity of the first antenna 151 is not limited thereto in the first antenna layer 15.
As an example, can be formed using electroplating technology, physical gas-phase deposition or chemical vapor deposition process described
First antenna layer 15；The material of the first antenna layer 15 can include but are not limited at least one of copper, aluminium and silver.
As an example, the shape of the first antenna 151 may include but be not limited only to blocky or helical form etc..
In step 6), S6 step and Figure 10 in Fig. 1 are please referred to, the upper surface of Yu Suoshu plastic packaging layer 14 forms frame knot
Structure 16, the frame structure 16 are located at the periphery of the first antenna layer 15.
As an example, the frame structure 16 includes resinous framework structure, metal framework structure or ceramic frame configuration.
As an example, the frame structure 16 can surround 15 surrounding of first antenna layer, and the frame structure 16
There is spacing between the first antenna layer 15.
As an example, the frame structure 16 can be bonded to the upper surface of the plastic packaging layer 14 using bonding technology.
In step 7), S7 step and Figure 11 in Fig. 1 are please referred to, cover board 17, a surface shape of the cover board 17 are provided
At there is the second antenna stack 18；The cover board 17 is bonded to the top of the frame structure 16, second antenna stack after bonding
18 are located at the lower surface of the cover board 17, and second antenna stack 18 and the first antenna layer 15 have spacing.
As exemplary step 7) after, the cover board 17 is by the regional seal in the frame structure 17, to form air
Chamber 20, the first antenna 15 and second antenna 18 are respectively positioned in the air chamber 20.
As an example, the cover board 17 may include but be not limited only to glass cover-plate.
Include the following steps: as an example, forming second antenna stack 18 in a surface of the cover board 17
The second antenna material layer (not shown) is formed in a surface of the cover board 17；
Perform etching to the second antenna material layer includes described in multiple the second antennas 181 being intervally arranged to obtain
Second antenna stack 18；I.e. described second antenna stack 18 may include several second antennas 181, several described second antennas
181 can arrange (for example, being arranged in array) in the lower surface of the frame structure 16 in arbitrary shape, and adjacent described second
There is spacing between antenna 181.In second antenna stack 18 quantity of second antenna 181 can according to actual needs into
Row setting only with second antenna stack 18 includes four second antennas 181 as an example, in actual example in Figure 11
In, the quantity of second antenna 181 is not limited thereto in second antenna stack 18.
As an example, second antenna 181 can be correspondingly arranged up and down one by one with the first antenna 151.
As an example, the material of second antenna 181 may include but be not limited only in copper, aluminium and silver at least one
Kind.
In step 8), S8 step and Figure 12 in Fig. 1 are please referred to, removes the substrate 10 and the sacrificial layer 11.
As an example, the sacrificial layer 11 can be removed while removing substrate 10.
As an example, using grinding technics, reduction process or the technique removal sacrificial layer 11 and the base can be removed
Bottom 10；Preferably, in the present embodiment, the substrate 10 is removed by the way of removing the sacrificial layer 11.
As an example, further including following steps after step 8): forming opening 126, institute in Yu Suoshu re-wiring layer 12
Opening 126 is stated through the bottom dielectric layer 121 and the capsulation material layer 122 to expose the seed layer 123, such as Figure 13
It is shown.Specifically, the lower surface that can use lithographic etch process from the re-wiring layer 12 performs etching described in formation
Opening 126.
In step 9), S9 step and Figure 14 in Fig. 1 are please referred to, chip 21 is provided, by 21 back bonding of chip
In the lower surface of the re-wiring layer 12, the chip 21 is realized with the re-wiring layer 12 to be electrically connected.
As an example, the chip 21 can be any one functional chip, device could be formed in the chip 21
Structure (not shown), the front of the chip 21 could be formed with connection weld pad (not shown), the connection weld pad and the device
The electrical connection of part structure.
As an example, the device architecture in the chip 21 may include active component and passive element.
As an example, can using any one existing bonding technology by 21 back bonding of chip in it is described again
The lower surface of wiring layer 12；The connection weld pad of the chip 21 is via in the part opening and the re-wiring layer 12
The metallic stacked structure 125 be electrically connected.
As an example, further including in institute after the lower surface of the re-wiring layer 12 by 21 back bonding of chip
State the step of Underfill layer 22 are formed between chip 21 and the re-wiring layer 12；Specifically, can use but not only limit
In ink-jetting process, gluing process, compressing and forming process, Transfer molding technique, fluid-tight moulding process, vacuum lamination process or
At least one of spin coating proceeding forms the Underfill layer 22；The material of the Underfill layer 22 may include but not only
It is limited at least one of polyimides, silica gel and epoxy resin.The Underfill layer 22 can be enhanced the chip 21 with
The bond strength of the re-wiring layer 12, and protect the re-wiring layer 12.
In step 10), S10 step and Figure 15 in Fig. 1 are please referred to, the lower surface of Yu Suoshu re-wiring layer 12 is formed
Soldered ball convex block 19, the soldered ball convex block 19 are electrically connected with the re-wiring layer 12.
As an example, the soldered ball convex block 19 is located in the opening 126 of 21 periphery of chip, the soldered ball convex block
19 are in contact with the seed layer 123.
As an example, the material of the soldered ball convex block 19 may include at least one of copper and tin.
The semiconductor package of the preparation method preparation of semiconductor package of the invention passes through described the
About 21 plastic packaging of one antenna stack 15, second antenna stack 18 and the chip, can effectively reduce the semiconductor packages knot
The volume of structure improves the integrated level of device；By the way that the active component and the passive element are integrated in the chip 21,
The volume that the encapsulating structure can be further decreased further increases the integrated level of device；The first antenna layer 15 and institute
State and only have air insulated between the second antenna stack 18, the dielectric loss of air is minimum, can reduce the first antenna layer 15 with
The loss of signal of second antenna stack 18, and transmission signal path is shorter in semiconductor package of the invention, can obtain
To better electrical property and antenna performance.
Embodiment two
Incorporated by reference to Fig. 2 to Figure 14 with continued reference to 15, the present invention also provides a kind of semiconductor package, the semiconductor package
Assembling structure includes: re-wiring layer 12；Chip 21,21 back bonding of chip in the lower surface of the re-wiring layer 12,
And the chip 21 is electrically connected with the re-wiring layer 12；Electric connection structure 13, the electric connection structure 13 are located at described heavy
The upper surface of new route layer 12, and the electric connection structure 13 is electrically connected with the re-wiring layer 12；Plastic packaging layer 14, the modeling
Sealing 14 is located at the upper surface of the re-wiring layer 12, and the plastic packaging layer 14 is by 13 plastic packaging of electric connection structure；First
Antenna stack 15, the first antenna layer 15 are located at the upper surface of the plastic packaging layer 14, and the first antenna layer 15 and the electricity
Connection structure 13 is connected；Frame structure 16, the frame structure 16 are located at the upper surface of the plastic packaging layer 14, and the frame
Structure 16 is located at the periphery of the first antenna layer 15；Cover board 17, the cover board 17 are located at the top of the frame structure 16；The
Two antenna stacks 18, second antenna stack 18 are located at the lower surface of the cover board 17, and second antenna stack 18 and described the
One antenna stack 15 has spacing；Soldered ball convex block 19, the soldered ball convex block 19 are located at the lower surface of the re-wiring layer 12, and institute
Soldered ball convex block 19 is stated to be electrically connected with the re-wiring layer 12.
As an example, the re-wiring layer 12 may include: wiring dielectric layer 124, positioned at the upper of the sacrificial layer 11
Surface；Metallic stacked structure 125, the metallic stacked structure 125 is located in the wiring dielectric layer 124, described metal laminated
Structure 125 includes the metal line layer (not indicating) and metal plug (not indicating) of Spaced arrangement, the metal plug
Between the adjacent metal line layer, the adjacent metal line layer is electrically connected.
As an example, the material of the wiring dielectric layer 124 may include low k dielectric.Specifically, the wiring is situated between
The material of electric layer 124 may include using in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
A kind of material；The wiring dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the re-wiring layer 12 can also include: seed layer 123, the seed layer 123 is located at the cloth
In line dielectric layer 124, and the seed layer 123 is electrically connected with the metallic stacked structure 125；Capsulation material layer 122, the modeling
Closure material layer 122 is located in the wiring dielectric layer 124, and is located at the lower surface of the seed layer 123；The wiring dielectric layer
The 124 cladding capsulation material layers 122 and 123 bottom dielectric layer 121 of the seed layer, the bottom dielectric layer 121 are located at institute
State the lower surface of wiring dielectric layer 124.
As an example, the material of the bottom dielectric layer 121 may include low k dielectric.Specifically, the bottom is situated between
121 material of electric layer may include using in epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass
A kind of material；The bottom dielectric layer 121 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the material of the capsulation material layer 122 may include but be not limited only to polyimides, silica gel or epoxy
Resin etc..
The seed layer 123 is formed as an example, can use but be not limited only to sputtering technology；The seed layer 123
Material may include at least one of Ti (titanium) and Cu (copper)；Specifically, the seed layer 123 can be titanium layer, it can also be with
For layers of copper, or the laminated construction of titanium layer and layers of copper can also be CTB alloy layer.
As an example, the material of the wiring dielectric layer 124 may include low k dielectric.As an example, the wiring
Dielectric layer 124 can be using one of epoxy resin, silica gel, PI, PBO, BCB, silica, phosphorosilicate glass and fluorine-containing glass material
Material, and the wiring dielectric layer 124 can be formed using techniques such as spin coating, CVD, plasma enhanced CVDs.
As an example, the metal line layer may include single metal layer, it also may include two or more layers metal layer.Make
For example, the material of the material of the metal line layer and the metal plug may include copper, aluminium, nickel, gold, silver, one in titanium
Kind material or two or more combined materials.
As an example, the chip 21 can be any one functional chip, device could be formed in the chip 21
Structure (not shown), the front of the chip 21 could be formed with connection weld pad (not shown), the connection weld pad and the device
The electrical connection of part structure.
As an example, the device architecture in the chip 21 may include active component and passive element.
As an example, can using any one existing bonding technology by 21 back bonding of chip in it is described again
The lower surface of wiring layer 12；The connection weld pad and the metal laminated knot in the re-wiring layer 12 of the chip 21
Structure 125 is electrically connected.
As an example, the electric connection structure 13 may include bonding wire or conductive column.
As an example, the quantity of the electric connection structure 13 can be set according to actual needs, only to show in Figure 15
Four electric connection structures 13 anticipate out as an example, in actual example, the quantity of the electric connection structure 13 is not with this
It is limited.
As an example, the material of the plastic packaging layer 14 may include but be not limited only to polymer-based material, resin-based materials,
Polyimides, silica gel or epoxy resin etc..
As an example, the top flush of the upper surface of the plastic packaging layer 14 and the electric connection structure 13.
As an example, the first antenna layer 15 includes several first antennas 151；Several described first antennas 151
In the upper surface of the plastic packaging layer 14 in arbitrary shape arrangement (for example, being arranged in array), and the adjacent first antenna 151 it
Between have spacing.The quantity of the first antenna 151 can be set according to actual needs in the first antenna layer 15, figure
It only with the first antenna layer 15 include four first antennas 151 as an example, in actual example in 15, described first
The quantity of the first antenna 151 is not limited thereto in antenna stack 15.
As an example, can be formed using electroplating technology, physical gas-phase deposition or chemical vapor deposition process described
First antenna layer 15；The material of the first antenna layer 15 can include but are not limited at least one of copper, aluminium and silver.
As an example, the frame structure 16 includes resinous framework structure, metal framework structure or ceramic frame configuration.
As an example, the frame structure 16 can surround 15 surrounding of first antenna layer, and the frame structure 16
There is spacing between the first antenna layer 15.
As an example, the frame structure 16 can be bonded to the upper surface of the plastic packaging layer 14 using bonding technology.
The cover board 17 is by the regional seal in the frame structure 17, to form air chamber 20, the first antenna
15 and second antenna 18 be respectively positioned in the air chamber 20.
As an example, the cover board 17 may include but be not limited only to glass cover-plate.
As an example, second antenna stack 18 may include several second antennas 181, several described second antennas
181 in the frame structure 16 be in arbitrary shape arrangement (for example, being arranged in array), and adjacent second antenna 181 it
Between have spacing.The quantity of second antenna 181 can be set according to actual needs in second antenna stack 18, figure
It only with second antenna stack 18 include four second antennas 181 as an example, in actual example in 11, described second
The quantity of second antenna 181 is not limited thereto in antenna stack 18.
As an example, second antenna 181 can be correspondingly arranged up and down one by one with the first antenna 151.
As an example, the material of second antenna 181 may include but be not limited only in copper, aluminium and silver at least one
Kind.
As an example, the material of the soldered ball convex block 19 may include at least one of copper and tin.
Semiconductor package of the present invention is by by the first antenna layer 15, second antenna stack 18 and institute
About 21 plastic packaging of chip is stated, the volume of the semiconductor package can be effectively reduced, improve the integrated level of device；Passing through will
The active component and the passive element are integrated in the chip 21, can further decrease the body of the encapsulating structure
Product, further increases the integrated level of device；Only have air insulated between the first antenna layer 15 and second antenna stack 18,
The dielectric loss of air is minimum, can reduce the loss of signal of the first antenna layer 15 and second antenna stack 18, and this
Transmission signal path is shorter in the semiconductor package of invention, available better electrical property and antenna performance.
In conclusion the present invention provides a kind of semiconductor package and preparation method thereof, the semiconductor package
It include: re-wiring layer；Chip, back bonding are electrically connected in the lower surface of the re-wiring layer, and with the re-wiring layer
It connects；Electric connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；Plastic packaging layer, is located at
The upper surface of the re-wiring layer, and by the electric connection structure plastic packaging；First antenna layer, positioned at the upper table of the plastic packaging layer
Face, and be connected with the electric connection structure；Frame structure positioned at the upper surface of the plastic packaging layer, and is located at described first day
The periphery of line layer；Cover board, positioned at the top of the frame structure；Second antenna stack, positioned at the lower surface of the cover board, and with institute
First antenna layer is stated with spacing；Soldered ball convex block, positioned at the lower surface of the re-wiring layer, and it is electric with the re-wiring layer
Connection.Semiconductor package of the invention, can be effective by by plastic packaging above and below first antenna layer, the second antenna stack and chip
The volume for reducing encapsulating structure, improves the integrated level of device；It, can be with by the way that active component and passive element is integrated in the chip
The volume for further decreasing encapsulating structure further increases the integrated level of device；Between first antenna layer and the second antenna stack only
There is air insulated, the dielectric loss of air is minimum, can reduce the loss of signal of first antenna layer and the second antenna stack, and this hair
Transmission signal path is shorter in bright semiconductor package, available better electrical property and antenna performance.
The principle of the present invention and its effect is only illustrated in above embodiment, and is not intended to limit the present invention.It is any
Those skilled in the art all without departing from the spirit and scope of the present invention, modifies above embodiment or is changed
Become.Therefore, such as those of ordinary skill in the art without departing from disclosed spirit and technical idea
Lower completed all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of semiconductor package, which is characterized in that the semiconductor package includes:
Re-wiring layer；
Chip, back bonding are electrically connected in the lower surface of the re-wiring layer, and with the re-wiring layer；
Electric connection structure is electrically connected positioned at the upper surface of the re-wiring layer, and with the re-wiring layer；
Plastic packaging layer, positioned at the upper surface of the re-wiring layer, and by the electric connection structure plastic packaging；
First antenna layer is connected positioned at the upper surface of the plastic packaging layer, and with the electric connection structure；
Frame structure positioned at the upper surface of the plastic packaging layer, and is located at the periphery of the first antenna layer；
Cover board, positioned at the top of the frame structure；
Second antenna stack has spacing positioned at the lower surface of the cover board, and with the first antenna layer；
Soldered ball convex block is electrically connected positioned at the lower surface of the re-wiring layer, and with the re-wiring layer.
2. semiconductor package according to claim 1, it is characterised in that: the re-wiring layer includes:
It is routed dielectric layer, positioned at the upper surface of the sacrificial layer；
Metallic stacked structure is located in the wiring dielectric layer, and the metallic stacked structure includes the metal of Spaced arrangement
Line layer and metal plug, the metal plug is between the adjacent metal line layer, by adjacent metal line layer electricity
Connection.
3. semiconductor package according to claim 2, it is characterised in that: the re-wiring layer further include:
Seed layer is located in the wiring dielectric layer, and is electrically connected with the metallic stacked structure；
Capsulation material layer is located in the wiring dielectric layer, and is located at the lower surface of the seed layer；
Bottom dielectric layer, positioned at the lower surface of the wiring dielectric layer.
4. semiconductor package according to claim 1, it is characterised in that: the frame structure includes resinous framework knot
Structure, metal framework structure or ceramic frame configuration；The cover board includes glass cover-plate.
5. semiconductor package according to claim 1, it is characterised in that: the first antenna layer include several
One antenna, second antenna stack include several second antennas, and the first antenna is right up and down one by one with second antenna
It should be arranged.
6. semiconductor package according to claim 1, it is characterised in that: have active component and nothing in the chip
Source element.
7. semiconductor package according to any one of claim 1 to 6, it is characterised in that: the semiconductor packages
Structure further includes Underfill layer, and the Underfill layer is between the chip and the re-wiring layer.
8. a kind of preparation method of semiconductor package, which is characterized in that the preparation method packet of the semiconductor package
Include following steps:
Substrate is provided, the upper surface of Yu Suoshu substrate forms sacrificial layer；
Re-wiring layer is formed in the upper surface of the sacrificial layer；
Electric connection structure is formed in the upper surface of the re-wiring layer, the electric connection structure is electrically connected with the re-wiring layer
It connects；
Plastic packaging layer is formed in the upper surface of the re-wiring layer, the plastic packaging layer is by the electric connection structure plastic packaging；
First antenna layer is formed in the upper surface of the plastic packaging layer, the first antenna layer is electrically connected with the electric connection structure；
Frame structure is formed in the upper surface of the plastic packaging layer, the frame structure is located at the periphery of the first antenna layer；
Cover board is provided, a surface of the cover board is formed with the second antenna stack；The cover board is bonded to the frame structure
Top, second antenna stack is located at the lower surface of the cover board after bonding, and has spacing with the first antenna layer；
Remove the substrate and the sacrificial layer；
Chip is provided, the flip-chip is bonded to the lower surface of the re-wiring layer, the chip and the cloth again
Line layer, which is realized, to be electrically connected；
Soldered ball convex block is formed in the lower surface of the re-wiring layer, the soldered ball convex block is electrically connected with the re-wiring layer.
9. the preparation method of semiconductor package according to claim 8, it is characterised in that: Yu Suoshu sacrificial layer it is upper
Surface forms the re-wiring layer and includes the following steps:
Bottom dielectric layer is formed in the upper surface of the sacrificial layer；
Capsulation material layer is formed in the upper surface of the bottom dielectric layer；
Seed layer is formed in the upper surface of the capsulation material layer；
Processing is patterned to the seed layer and the capsulation material layer；
Wiring dielectric layer is formed in the upper surface of the bottom dielectric layer and metallic stacked structure, the metallic stacked structure are located at
In the wiring dielectric layer, and it is electrically connected with the seed layer；The metallic stacked structure includes the metal of Spaced arrangement
Line layer and metal plug, the metal plug is between the adjacent metal line layer, by adjacent metal line layer electricity
Connection.
10. the preparation method of semiconductor package according to claim 8, it is characterised in that: the frame of formation
Structure includes resinous framework structure, metal framework structure portion or ceramic frame configuration；The cover board provided includes glass cover-plate.
11. the preparation method of semiconductor package according to claim 8, it is characterised in that:
The first antenna layer is formed in the upper surface of the plastic packaging layer to include the following steps:
First antenna material layer is formed in the upper surface of the plastic packaging layer；
Perform etching to the first antenna material layer includes described first day of multiple first antennas being intervally arranged to obtain
Line layer；
Second antenna stack is formed in a surface of the cover board to include the following steps:
The second antenna material layer is formed in a surface of the cover board；
Perform etching to the second antenna material layer includes described second day of multiple the second antennas being intervally arranged to obtain
Line layer；
The first antenna is correspondingly arranged up and down one by one with second antenna.
12. the preparation method of the semiconductor package according to any one of claim 8 to 11, it is characterised in that: will
The flip-chip further includes in the chip and the re-wiring layer after being bonded to the lower surface of the re-wiring layer
Between formed Underfill layer the step of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910476812.6A CN110137157B (en) | 2019-06-03 | 2019-06-03 | Semiconductor packaging structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910476812.6A CN110137157B (en) | 2019-06-03 | 2019-06-03 | Semiconductor packaging structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110137157A true CN110137157A (en) | 2019-08-16 |
| CN110137157B CN110137157B (en) | 2024-06-11 |
Family
ID=67579674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910476812.6A Active CN110137157B (en) | 2019-06-03 | 2019-06-03 | Semiconductor packaging structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110137157B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880482A (en) * | 2019-12-18 | 2020-03-13 | 江阴长电先进封装有限公司 | Chip packaging structure and packaging method thereof |
| CN113299569A (en) * | 2021-06-11 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | Preparation method of large-board-level fan-out substrate flip chip packaging structure |
| WO2023116305A1 (en) * | 2021-12-23 | 2023-06-29 | 华为技术有限公司 | Packaging module and preparation method therefor, base station, and electronic device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN107706521A (en) * | 2017-10-25 | 2018-02-16 | 中芯长电半导体（江阴）有限公司 | Fan-out-type antenna packages structure and preparation method thereof |
| CN207517662U (en) * | 2017-12-07 | 2018-06-19 | 中芯长电半导体（江阴）有限公司 | Fan-out package structure |
| CN108417559A (en) * | 2017-02-08 | 2018-08-17 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
| CN108511400A (en) * | 2018-03-16 | 2018-09-07 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna |
| CN109411434A (en) * | 2017-08-18 | 2019-03-01 | 三星电机株式会社 | Fan-out-type semiconductor package part |
| CN209929301U (en) * | 2019-06-03 | 2020-01-10 | 中芯长电半导体（江阴）有限公司 | Semiconductor packaging structure |
-
2019
- 2019-06-03 CN CN201910476812.6A patent/CN110137157B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105225965A (en) * | 2015-11-03 | 2016-01-06 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out package structure and preparation method thereof |
| CN108417559A (en) * | 2017-02-08 | 2018-08-17 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation device and its manufacturing method |
| CN109411434A (en) * | 2017-08-18 | 2019-03-01 | 三星电机株式会社 | Fan-out-type semiconductor package part |
| CN107706521A (en) * | 2017-10-25 | 2018-02-16 | 中芯长电半导体（江阴）有限公司 | Fan-out-type antenna packages structure and preparation method thereof |
| CN207517662U (en) * | 2017-12-07 | 2018-06-19 | 中芯长电半导体（江阴）有限公司 | Fan-out package structure |
| CN108511400A (en) * | 2018-03-16 | 2018-09-07 | 中芯长电半导体（江阴）有限公司 | The encapsulating structure and packaging method of antenna |
| CN209929301U (en) * | 2019-06-03 | 2020-01-10 | 中芯长电半导体（江阴）有限公司 | Semiconductor packaging structure |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110880482A (en) * | 2019-12-18 | 2020-03-13 | 江阴长电先进封装有限公司 | Chip packaging structure and packaging method thereof |
| CN113299569A (en) * | 2021-06-11 | 2021-08-24 | 广东佛智芯微电子技术研究有限公司 | Preparation method of large-board-level fan-out substrate flip chip packaging structure |
| WO2023116305A1 (en) * | 2021-12-23 | 2023-06-29 | 华为技术有限公司 | Packaging module and preparation method therefor, base station, and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110137157B (en) | 2024-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105225965B (en) | A kind of fan-out package structure and preparation method thereof | |
| CN103943553B (en) | The method that there is the low profile of perpendicular interconnection unit to be fanned out to formula encapsulation for semiconductor devices and formation | |
| CN105514087A (en) | Double-faced fan-out type wafer-level packaging method and packaging structure | |
| CN108511400A (en) | The encapsulating structure and packaging method of antenna | |
| CN109285828A (en) | Fan-out-type antenna packages structure with air chamber and preparation method thereof | |
| CN107507821A (en) | The encapsulating structure and method for packing of integrated image sensor chip and logic chip | |
| CN110148587A (en) | Fan-out-type antenna packages structure and packaging method | |
| CN107958896A (en) | Two-sided plastic packaging fan-out package structure with antenna structure and preparation method thereof | |
| CN107393910A (en) | Fan-out-type system-in-package structure and preparation method thereof | |
| CN110137157A (en) | Semiconductor package and preparation method thereof | |
| CN107706520A (en) | Fan-out-type antenna packages structure and preparation method thereof | |
| CN110085575A (en) | Semiconductor package and preparation method thereof | |
| CN110148588A (en) | A kind of fan-out-type antenna packages structure and its packaging method | |
| CN109768031A (en) | The encapsulating structure and packaging method of antenna | |
| CN110112110A (en) | Semiconductor package and preparation method thereof | |
| CN110120385A (en) | Semiconductor package and preparation method thereof | |
| CN107195625A (en) | Two-sided system-level laminated packaging structure of plastic packaging fan-out-type and preparation method thereof | |
| CN207517662U (en) | Fan-out package structure | |
| CN110085973A (en) | Antenna packages structure and packaging method | |
| CN109755227A (en) | Encapsulating structure and preparation method thereof | |
| CN207852667U (en) | Fan-out-type antenna packages structure with electromagnetic protection | |
| CN206931602U (en) | The two-sided system-level laminated packaging structure of plastic packaging fan-out-type | |
| CN207852897U (en) | Fan-out-type antenna packages structure | |
| CN109727934A (en) | Encapsulating structure and preparation method thereof | |
| CN207977309U (en) | Fan-out-type semiconductor package with antenna module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Applicant before: SJ Semiconductor (Jiangyin) Corp. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |