CN206014407U - Mems - Google Patents
Mems Download PDFInfo
- Publication number
- CN206014407U CN206014407U CN201620714829.2U CN201620714829U CN206014407U CN 206014407 U CN206014407 U CN 206014407U CN 201620714829 U CN201620714829 U CN 201620714829U CN 206014407 U CN206014407 U CN 206014407U
- Authority
- CN
- China
- Prior art keywords
- layer
- quality block
- exercise quality
- polycrystalline
- buried regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Micromachines (AREA)
Abstract
A kind of MEMS, including：Substrate；Polycrystalline buried regions, in the substrate, the graphical one or more polycrystalline figures of the polycrystalline buried regions；Sacrifice layer, on the polycrystalline buried regions, at least a portion in the sacrifice layer with cavity, the polycrystalline figure is located in the cavity；Exercise quality block layer, at least a portion of the exercise quality block layer is supported by the polycrystalline buried regions, the exercise quality block layer includes that the exercise quality block above the cavity, the exercise quality block have the bump prominent to the cavity towards the surface of the cavity；Anti adhering layer, on the exposed surface between the polycrystalline buried regions and the exercise quality block layer.The utility model can reduce the contact area between exercise quality block and substrate and/or polycrystalline buried regions, and the hydrophobicity due to anti adhering layer and low surface adhesion, can efficiently reduce or prevent adhesion.
Description
Technical field
The utility model belongs to MEMS technology field, forms anti-adhesion bump more particularly, to one kind using sacrifice layer
And the MEMS of alchlor adhesion layer is formed between exercise quality block layer and polycrystalline buried regions or substrate.
Background technology
MEMS technology is described as 21 century with revolutionary new and high technology, and its development starts from the sixties in 20th century, MEMS
It is the abbreviation of English Micro Electro Mechanical System, i.e. microelectromechanical systems.Microelectromechanical systems
(MEMS) be a kind of new multi-crossed disciplines developed in recent years technology, the technology will to following human lives produce leather
The impact of life property.The basic technology of MEMS mainly includes anisotropic silicon lithographic technique, silicon bonding technology, surface micro skill
Art, LIGA technology etc., these technology have become the requisite core technologies of development and production MEMS.
Accelerometer, gyroscope in the MEMS process technologies based on silicon, in portioned product such as inertial sensor
Deng the device of micromechanics, the characteristic size of its microstructure part is 100nm～1mm, the surface of microstructure under the size
Product is increased with the ratio of volume, and the surface related to microstructure part surface area such as Van der Waals force, surface tension, electrostatic force is made
With gradually strengthening, in microstructure manufacture and application process, when superficial attractive forces are more than the elastic restoring force of micro-structural, phase
To stick together between adjacent microstructure (or referred to as movable mass) or microstructure and substrate, so as to cause device to lose
Effect, makes decrease in yield.
Adhesion has become the main cause that generation finished product is scrapped in micromachined and application process, seriously constrains MEMS
The development of technology and commercial application.In actual micromechanics finished product development process, due to surface reaction forces such as Van der Waals forces
Approximately proportional with relative contact product, when micro-structural area is larger, it is susceptible to adhesion phenomenon between the two, and works as
During the contact area very little of one micro-structural, the bump of a such as very little, accordingly even when have contact, the elasticity recovery of its micro-structural
Therefore power would not stick together much larger than the superficial attractive forces of little bump, based on the principle, general inertial sensor design
In manufacture process, the in-plane (X and Y-direction) of microstructure part can be prior in pattern layout by layout design
The little bump of anti-adhesion is designed, prevents horizontal direction in motion process from sending out to reduce the contact area in horizontal movement direction
Raw adhesion, but the typically no little bump design that this prevents adhesion on vertical Z direction, even if there is the little bump for preventing adhesion, device is transported
Dynamic component in the course of the work, is also easy to the motion failures that adhesion occurs, and finally resulting in makes whole component failure.
Utility model content
The purpose of this utility model is that providing one kind forms anti-adhesion bump and in exercise quality block using sacrifice layer
The MEMS of alchlor adhesion layer is formed between layer and polycrystalline buried regions or substrate.
According to one side of the present utility model, there is provided a kind of MEMS, including：Substrate；Polycrystalline buried regions, positioned at the base
On bottom, the graphical one or more polycrystalline figures of the polycrystalline buried regions；Sacrifice layer, on the polycrystalline buried regions, the sacrifice
At least a portion in layer with cavity, the polycrystalline figure is located in the cavity；Exercise quality block layer, the moving-mass
At least a portion of block layer is supported by the polycrystalline buried regions, and the exercise quality block layer includes the motion above the cavity
Mass, the exercise quality block have the bump prominent to the cavity towards the surface of the cavity；Wherein, the MEMS
Device also includes：Anti adhering layer, on the exposed surface between the polycrystalline buried regions and the exercise quality block layer.
Preferably, the material of the sacrifice layer is oxidation material.
Preferably, the material of the sacrifice layer is silica.
Preferably, the substrate includes Semiconductor substrate and the separation layer in the Semiconductor substrate, the polycrystalline
Buried regions and sacrifice layer are located on the separation layer.
Preferably, the bump is shaped as square or V-type, and the bump is from the exercise quality block layer towards the sky
The height that the surface in chamber projects is 0.5 μm to 0.8 μm.
Preferably, the MEMS also includes：Metal level, on the exercise quality block layer, the metal level bag
Include lead and/or for the bonding region with sealing cap wafer bonding.
Preferably, in the exercise quality block layer have through hole, the exercise quality block layer via the through hole with described
Polycrystalline buried regions is connected.
Preferably, the material of the polycrystalline buried regions and/or the exercise quality block layer is polysilicon.
Preferably, the material of the anti adhering layer is alchlor.
Preferably, the thickness of the anti adhering layer is 2nm～10nm.
According to another aspect of the present utility model, there is provided a kind of manufacture method of MEMS, including：Substrate is provided；?
Polycrystalline buried regions is formed in the substrate simultaneously graphical, to form one or more polycrystalline figures；Formed and cover the polycrystalline buried regions
Sacrifice layer；The upper surface of the sacrifice layer is performed etching to form pit；Motion is formed in the upper surface of the sacrifice layer
Mass layer, the exercise quality block layer fill the pit；The exercise quality block layer is patterned to form motion
Mass, and deep trouth is formed in the exercise quality block layer, the sacrifice layer is exposed in the deep trouth bottom；By the deep trouth pair
The sacrifice layer is corroded to form cavity in the sacrifice layer below the exercise quality block, is filled in the pit
Exercise quality block layer is prominent to the cavity；Shape on exposed surface between the polycrystalline buried regions and the exercise quality block layer
Into anti adhering layer.
Preferably, the material of the sacrifice layer is oxidation material.
Preferably, the material of the sacrifice layer is silica.
Preferably, there is provided substrate includes：Semiconductor substrate is provided；Separation layer is formed on the semiconductor substrate, described
Polycrystalline buried regions and sacrifice layer are located on the separation layer.
Preferably, the pit is shaped as square or V-type, and depth is 0.5 μm to 0.8 μm.
Preferably, the sacrifice layer is corroded by the way of HF acid is stifling.
Preferably, also included before being patterned to the exercise quality block layer：On the exercise quality block layer
Metal level is formed, and the metal level is patterned to form lead and/or for the bonding region with sealing cap wafer bonding.
Preferably, also included before the exercise quality block layer is formed：Through hole, the fortune is formed in the sacrifice layer
Kinoplaszm gauge block layer is connected with the polycrystalline buried regions via the through hole.
Preferably, the material of the polycrystalline buried regions and/or exercise quality block layer is polysilicon.
Preferably, the material of the anti adhering layer is alchlor.
Preferably, the thickness of the anti adhering layer is 2nm～10nm.
In the MEMS of the utility model embodiment, exercise quality block layer has prominent on the surface of cavity downward
Point, the bump can effectively reduce the contact area of exercise quality block layer and polycrystalline buried regions, so as to reducing or preventing adhesion, keep away
Exempt from component failure；Alchlor anti adhering layer is formed on exposed surface between exercise quality block layer and polycrystalline buried regions, due to three
The hydrophobicity of aluminum oxide and low surface adhesion, had both played the purpose of dual anti-adhesion, and had not affected device performance.
Additionally, in the manufacture method of the MEMS of the utility model embodiment, pit is formed in the upper surface of sacrifice layer,
And exercise quality block layer is formed on sacrifice layer and fills pit, the fortune that after layer segment removes, is filled in pit will sacrificed
Kinoplaszm gauge block layer forms bump, reduces the contact area of exercise quality block and polycrystalline buried regions, glues such that it is able to reducing or preventing
Even, it is to avoid component failure；Alchlor anti adhering layer is formed between exercise quality block and polycrystalline buried regions on exposed surface, by
In hydrophobicity and the low surface adhesion of alchlor, the purpose of dual anti-adhesion was both played, and had not affected device performance.
Description of the drawings
By description referring to the drawings to the utility model embodiment, of the present utility model above-mentioned and other mesh
, feature and advantage will be apparent from, in the accompanying drawings：
Fig. 1 is the schematic flow sheet of the manufacture method of the MEMS according to the utility model embodiment；
Fig. 2 to Figure 11 is the corresponding device of each step in manufacture method according to the MEMS of the utility model embodiment
Part generalized section.
Specific embodiment
Various embodiments of the present utility model are more fully described hereinafter with reference to accompanying drawing.In various figures, identical
Element is represented using same or similar reference.For the sake of clarity, the various pieces in accompanying drawing are not drawn to paint
System.
The utility model can be presented in a variety of manners, some of them example explained below.
Fig. 1 is the schematic flow sheet of the manufacture method of the MEMS according to the utility model embodiment.As shown in figure 1,
Manufacture method according to the MEMS of the present embodiment may include steps of.
In step S101, there is provided substrate.
In step s 102, polycrystalline buried regions is formed on the substrate simultaneously graphical, to form one or more polycrystal patterns
Shape.
In step s 103, the sacrifice layer for covering the polycrystalline buried regions is formed.
In step S104, the upper surface of the sacrifice layer is performed etching to form pit.
In step S105, exercise quality block layer is formed in the upper surface of the sacrifice layer, the exercise quality block layer is filled out
Fill the pit.
In step s 106, the exercise quality block layer is patterned to form exercise quality block, and in the fortune
Kinoplaszm gauge block layer forms deep trouth, and the sacrifice layer is exposed in the deep trouth bottom.
In step s 107, the sacrifice layer is corroded with below the exercise quality block by the deep trouth
Cavity is formed in sacrifice layer, and the exercise quality block layer being filled in the pit is prominent to the cavity.
In step S108, formed on the exposed surface between the polycrystalline buried regions and the exercise quality block layer antiseized
Attached layer.
It is described in detail referring to Fig. 2 to Figure 11.
As shown in Fig. 2 providing substrate 10 first, in the substrate 10, then form separation layer 102.As one preferably
Example, the substrate 10 can be Semiconductor substrate 101.More specifically, Semiconductor substrate 101 can be conventional semiconductor
Silicon substrate in technique, for example, can be that crystal orientation is<100>N-type silicon substrate.The material of separation layer 102 can be that routine is partly led
Insulating materials in body technology, such as silica.It is, for example possible to use thermal oxide, low-pressure chemical vapor phase deposition (LPVCD) or
The methods such as plasma enhanced chemical vapor deposition (PECVD) form the separation layer of silica material in Semiconductor substrate 101
102.The typical thickness of separation layer 102 can be 2 μm to 3 μm.
As shown in figure 3, polycrystalline buried regions 103 is formed on the separation layer 102 simultaneously graphically, one or more many to be formed
Brilliant figure.The material of polycrystalline buried regions 103 can for example be the polysilicon of polysilicon or doping, but be not limited to this.
Furthermore, the polycrystalline of doping is formed on the separation layer 102 by low-pressure chemical vapor phase deposition (LPVCD)
Silicon, and graphical to which.Temperature during deposit can be 570 DEG C to 630 DEG C, and the thickness for depositing the polycrystal layer for being formed can be
0.6 μm to 1.0 μm.Then, formed including graphical including release aperture by the photoetching and etching technics of semiconductor industry.Many
Brilliant buried regions 103 can be used as device lower-layer wiring or be used as capacitor plate.
As shown in figure 4, forming the sacrifice layer 104 for covering the polycrystalline buried regions 103.The material of the sacrifice layer 104 can be with
It is oxidation material, preferably silica.For example, it is possible to pass through low-pressure chemical vapor phase deposition (LPVCD) or plasma enhanced
The method for learning vapor deposition (PECVD) forms the sacrifice layer 104 of silica material, and its thickness can generally be 1.0 μm to 2.0 μ
m.
As shown in figure 5, the upper surface to the sacrifice layer 104 is performed etching to form pit A.Furthermore, can be with
Photoetching process in using conventional semiconductor process, forms the graphical window of pit A, Ran Houtong in the upper surface of sacrifice layer 104
Cross the methods such as dry etching or wet etching and form pit A.The depth of pit A is the height of the bump being subsequently formed, preferably
Ground, the depth of pit 103 is 0.5 μm to 0.8 μm.The flat shape and size of pit 103 can be set according to actual needs
Fixed, for example square or V-type etc..Preferably, the size of the graphical window of pit A is 1 μm to 4 μm.Nonrestrictive as one
Example, the flat shape of pit A can be 4 μm * 0.6 μm square.
As shown in fig. 6, performing etching to the sacrifice layer 104, to form through hole B, the polycrystalline is exposed in the bottom of through hole B
Buried regions 103.
Furthermore, the photoetching process of conventional semiconductor can be adopted, and the window of through hole B is formed on sacrifice layer 104,
Through hole B is formed by the method such as dry etching or wet etching afterwards.The depth of through hole B causes through hole B bottom-exposeds to go out polycrystalline
Buried regions 103.Through hole B can be used as the fairlead that subsequent motion mass layer 105 is connected with polycrystalline buried regions 103.
As shown in fig. 7, forming exercise quality block layer 105, the exercise quality block layer in the upper surface of the sacrifice layer 104
Fill the pit.The material of the exercise quality block layer 105 can for example be the polysilicon of polysilicon or doping, but be not limited to
This.
Furthermore, it is possible to use the method for low-pressure chemical vapor phase deposition (LPVCD), deposit on sacrifice layer 104 and mix
Miscellaneous polysilicon, as seed polycrystal layer.Temperature during deposit can be 570 DEG C to 630 DEG C, deposit the seed polycrystal layer for being formed
Thickness can be 0.6 μm to 1.0 μm.Then, the seed polycrystal layer is made by the method for conventional semiconductor process extension then
15～25u thickness is grown into, by the method for CMP planarization so as to surface planarisation, so as to form exercise quality block layer 105.?
The bottom of exercise quality block layer 105, exercise quality block layer 105 also fill up pit A.Wherein, after being filled in the part formation of pit A
Continuous bump, can prevent adhesion.Through hole B makes exercise quality block layer 105 be connected with polycrystalline buried regions 103.
As shown in figure 8, form metal level 106 on the exercise quality block layer 10, and graphical to the metal level 106
Form lead.Furthermore, sputtering or the evaporation technology in conventional semiconductor process can be adopted, in exercise quality block layer 10
Upper deposited metal layer 106, its thickness can be 1 μm～2 μm, its material can be fine aluminium (Al), aluminium silicon (Al-Si1%) or
Ti+TiN+Al-Si.Afterwards, metal level 106 is patterned by the photoetching and etching technics of semiconductor industry, can conduct
The trace layer of device and the eutectic bonding metal level with sealing cap silicon chip.
As shown in figure 9, being patterned to the exercise quality block layer 105 to form exercise quality block, and in the fortune
Kinoplaszm gauge block layer 105 forms deep trouth, and the sacrifice layer 104 is exposed in the deep trouth bottom.
Furthermore, by conventional semiconductor photoetching technological method, the exercise quality block layer 105 is made to form motion matter
Gauge block figure, by special deep etching machine, can typically select AMS200 deep etching machines of Alcatel companies of the U.S. etc.
Etching apparatus, using MEMS industries routine Bosch techniques, etches deep trouth.
As shown in Figure 10, the sacrifice layer 104 is corroded with below the exercise quality block by the deep trouth
Sacrifice layer 104 in form cavity, the exercise quality block layer 105 being filled in the pit is prominent to the cavity.
Furthermore, for the sacrifice layer 104 of silica material, can be in the way of mutually being fumigated using HF acid gas, will fortune
The corrosion of sacrifice layer 104 between kinoplaszm gauge block layer 105 and substrate 10 is removed so that exercise quality block layer 105 is released, and is transported
Kinoplaszm gauge block.Exercise quality block layer 105 after release motion when, the cavity that at least partly can be entered in sacrifice layer 104.Sacrificial
After domestic animal layer 104 is partially removed, the exercise quality block layer 105 in pit A comes out, and defines bump.The bump can
With reduce the contact area between exercise quality block layer 105 and polycrystalline buried regions 103 or with or substrate 10 between contact area,
Even if thus, coming in contact, as elastic restoring force is much larger than the superficial attractive forces of bump, therefore can't stick together.
As shown in figure 11, formed on the exposed surface between the substrate 10 and the exercise quality block layer 105 antiseized
Attached layer.The material of the anti adhering layer is alchlor.
Furthermore, using atomic layer deposition (ALD) equipment, deposit source is used as by trimethyl aluminium and water, control is anti-
Room temperature is answered in the range of 100 DEG C～400 DEG C, pressure in several millibars, in the substrate 10 and the exercise quality block
Alchlor layer 111 is deposited on exposed surface between layer 105, its thickness can be 2nm～10nm.The hydrophobicity of alchlor
With low surface adhesion, the purpose of dual anti-adhesion was both played, and had not affected device performance.
In the MEMS of the utility model embodiment, exercise quality block layer has prominent on the surface of cavity downward
Point, the bump can effectively reduce the contact area of exercise quality block layer and polycrystalline buried regions, so as to reducing or preventing adhesion, keep away
Exempt from component failure；Alchlor anti adhering layer is formed on exposed surface between exercise quality block layer and polycrystalline buried regions, due to three
The hydrophobicity of aluminum oxide and low surface adhesion, had both played the purpose of dual anti-adhesion, and had not affected device performance.
Additionally, in the manufacture method of the MEMS of the utility model embodiment, pit is formed in the upper surface of sacrifice layer,
And exercise quality block layer is formed on sacrifice layer and fills pit, the fortune that after layer segment removes, is filled in pit will sacrificed
Kinoplaszm gauge block layer forms bump, reduces the contact area of exercise quality block and polycrystalline buried regions, glues such that it is able to reducing or preventing
Even, it is to avoid component failure；Alchlor anti adhering layer is formed between exercise quality block and polycrystalline buried regions on exposed surface, by
In hydrophobicity and the low surface adhesion of alchlor, the purpose of dual anti-adhesion was both played, and had not affected device performance.
According to embodiment of the present utility model as described above, these embodiments do not have all of details of detailed descriptionthe,
Also it is only described specific embodiment not limit the utility model.Obviously, as described above, a lot of modifications and change can be made
Change.This specification is chosen and specifically describes these embodiments, be in order to preferably explain principle of the present utility model and actual should
With so that skilled artisan can repairing using the utility model and on the basis of the utility model well
Change use.The scope that protection domain of the present utility model should be defined by the utility model claim is defined.
Claims (6)
1. a kind of MEMS, it is characterised in that include：
Substrate；
Polycrystalline buried regions, in the substrate, the graphical one or more polycrystalline figures of the polycrystalline buried regions；
Sacrifice layer, on the polycrystalline buried regions, has cavity, at least a portion position of the polycrystalline figure in the sacrifice layer
In the cavity；
Exercise quality block layer, at least a portion of the exercise quality block layer are supported by the polycrystalline buried regions, the moving-mass
Block layer includes that the exercise quality block above the cavity, the exercise quality block have to institute towards the surface of the cavity
State the bump of cavity protrusion；
Wherein, the MEMS also includes：
Anti adhering layer, on the exposed surface between the polycrystalline buried regions and the exercise quality block layer.
2. MEMS according to claim 1, it is characterised in that the substrate includes Semiconductor substrate and is located at described
Separation layer in Semiconductor substrate, the polycrystalline buried regions and sacrifice layer are located on the separation layer.
3. MEMS according to claim 1, it is characterised in that the bump is shaped as square or V-type, described prominent
The height that surface of the point from the exercise quality block layer towards the cavity projects is 0.5 μm to 0.8 μm.
4. MEMS according to claim 1, it is characterised in that also include：Metal level, positioned at the exercise quality block
On layer, the metal level includes lead and/or for the bonding region with sealing cap wafer bonding.
5. MEMS according to claim 4, it is characterised in that there is in the exercise quality block layer through hole, described
Exercise quality block layer is connected with the polycrystalline buried regions via the through hole.
6. MEMS according to claim 1, it is characterised in that the thickness of the anti adhering layer is 2nm～10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620714829.2U CN206014407U (en) | 2016-06-30 | 2016-06-30 | Mems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620714829.2U CN206014407U (en) | 2016-06-30 | 2016-06-30 | Mems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206014407U true CN206014407U (en) | 2017-03-15 |
Family
ID=58244332
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620714829.2U Active CN206014407U (en) | 2016-06-30 | 2016-06-30 | Mems |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206014407U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106115607A (en) * | 2016-06-30 | 2016-11-16 | 杭州士兰集成电路有限公司 | MEMS and manufacture method thereof |
| US11161734B2 (en) | 2017-12-29 | 2021-11-02 | Hangzhou Silan Integrated Circuits Co., Ltd. | MEMS assembly and manufacturing method thereof |
-
2016
- 2016-06-30 CN CN201620714829.2U patent/CN206014407U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106115607A (en) * | 2016-06-30 | 2016-11-16 | 杭州士兰集成电路有限公司 | MEMS and manufacture method thereof |
| US11161734B2 (en) | 2017-12-29 | 2021-11-02 | Hangzhou Silan Integrated Circuits Co., Ltd. | MEMS assembly and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106115607A (en) | MEMS and manufacture method thereof | |
| CN106115602B (en) | MEMS and its manufacture method | |
| CN105197871B (en) | MEMS device and its manufacturing method | |
| US9567207B2 (en) | Recess with tapered sidewalls for hermetic seal in MEMS devices | |
| US7507669B2 (en) | Gap tuning for surface micromachined structures in an epitaxial reactor | |
| CN100477162C (en) | Wafer cutting method | |
| US9090452B2 (en) | Mechanism for forming MEMS device | |
| CN101844739A (en) | Manufacturing method of subminiature MEMS gyroscope sensor | |
| CN206014407U (en) | Mems | |
| TWI700238B (en) | Method to improve stiction by roughing surface | |
| EP2327658B1 (en) | Method for manufacturing microelectronic devices and devices according to such method | |
| JP2009148883A (en) | Micro machine device and its manufacturing method | |
| US8691611B2 (en) | Method for creating a micromechanical membrane structure and MEMS component | |
| CN102602881A (en) | Method for forming multiple silicon trenches on MEMS (Micro Electro Mechanical Systems) sealing-cap silicon chip and etching mask structure thereof | |
| CN205917019U (en) | MEMS devices | |
| CN104991086A (en) | Method for machining MEMS acceleration sensor and acceleration sensor | |
| TW201609522A (en) | Method of manufacturing a MEMS structure | |
| CN103575431A (en) | Device for measuring forces and method of making same | |
| CN205115037U (en) | MEMS devices | |
| CN102530847A (en) | Heat insulation micro-structure and preparation method thereof | |
| CN105628054B (en) | Inertial sensor and preparation method thereof | |
| CN103395736B (en) | MEMS glass paste bonding structure and manufacture method thereof | |
| US20180170748A1 (en) | Semiconductor devices with cavities and methods for fabricating semiconductor devices with cavities | |
| US9013012B2 (en) | Self-sealing membrane for MEMS devices | |
| US20130157005A1 (en) | Method for Wafer-Level Surface Micromachining to Reduce Stiction |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |