CN205789951U - Mosfet package structure - Google Patents

Abstract

The utility model discloses a kind of mosfet package structure, encapsulating structure, including silicon substrate and MOSFET chip, MOSFET chip front side includes source conductive pad and Gate Electrode Conductive pad, the back side includes drain region, on drain region, deposition has metal level, silicon substrate has subsidence trough, conductive layer it is equipped with bottom subsidence trough, this conductive layer extends on substrate surface, as Drain Electrodes Conductive pad, MOSFET chip back mounts the bottom of subsidence trough, the metal level of drain region is connected by metal bonding with the conductive layer bottom subsidence trough, source conductive pad, Gate Electrode Conductive pad and Drain Electrodes Conductive pad are respectively formed on and the electric conductor of outside interconnection；On silicon substrate front, electric conductor is encapsulated by protective layer with outer portion.So, the MOSFET back-side drain electric current of vertical stratification can be caused the front of MOSFET, it is achieved source electrode, grid, drain electrode are electrically in same side, in order to carry out wafer-level packaging, and large area conductive layer ensure that the radiating effect that chip is good.

Description

Mosfet package structure

Technical field

This utility model belongs to technical field of semiconductor encapsulation, particularly relates to a kind of mosfet package structure.

Background technology

MOSFET (metal oxide semiconductor field effect tube) is to utilize field effect brilliant to the field effect controlling quasiconductor Body pipe.Can realize, owing to MOSFET has, the characteristic that low power consumption voltage controls, be widely used in a large amount of electronic equipment in recent years In, medium including power supply, automotive electronics, computer and smart mobile phone, receive more and more attention.

MOSFET element is by applying to work to the grid of MOSFET element by appropriate voltage, and it connects this device shape Become to connect the source electrode (source) of MOSFET and the passage of drain electrode (drain) to allow electric current flowing.In MOSFET element, the phase Hope that having low drain-source when this transistor is connected connects resistance (drain-source resistance, drain-on-source resistance) RDS(on).The quality of MOSFET performance particularly current carrying capacity is heavily dependent on heat dispersion, heat dispersion Quality depends primarily on again packing forms.MOSFET encapsulation require be the bearing capacity of big electric current, the efficient capacity of heat transmission with And less package dimension.The forms such as conventional MOS FET encapsulation mainly TO, SOT, SOP, QFN, QFP, this class wrapper be all by Chip is wrapped in plastic-sealed body, it is impossible to the heat produced during chip operation is led away in time or is dispersed, constrains MSOFET performance Promote.And plastic packaging itself has an increased device size, do not meet the requirement that quasiconductor develops to direction light, thin, short, little.Just envelope For dress technique, this class wrapper is all based on single chips to be carried out, and there is the problem that production efficiency is low, packaging cost is high.

WLP i.e. wafer-level packaging (Wafer Level Package), is different from traditional chip package mode and (first cuts Encapsulate again, and after encapsulating, at least increase the volume of former chip 20%), it is a kind of novel encapsulated technology.WLP is first at full wafer wafer On carry out packaging and testing, cut into single chips the most again, and be the batch encapsulation carried out based on whole wafer.By wafer Level encapsulation technology is incorporated into MOSFET field, is possible not only to promote MOSFET performance, reduce package dimension, and can improve life Produce efficiency, reduce packaging cost.

Face Board level packaging (Panel Level Package), is also the technology that encapsulates together of a kind of multi-chip, encapsulates complete After cut into single chips again, improve production efficiency, reduce packaging cost.

Vertical MOSFET device realizes low RDS by being placed in drain region on the surface contrary with source contact (on).By drain region is placed on the surface contrary with source contact, shorten electric current pathway (conductive path, Conduction path), this makes RDS (on) reduce.For this structure, it is impossible to meet and the most only one side is done processing procedure Wafer scale or panel level, it is necessary to combine silicon perforation TSV and same table is transferred in source conductive pad, Gate Electrode Conductive pad and drain region On face.See patent documentation: ZL201110033784.4 and patent documentation: ZL201210087086.7, open a kind of wafer level Chip size packages, is electrically drawn out to chip front side by source electrode and the grid of chip, and at chip back metal, afterwards, also Need by silicon through hole (TSV) technology from chip front side exposed chip back metal, and belonged to by filled gold in silicon through hole, will set Chip front side is guided in the metal level drain electrode put, and forms homonymy distribution with source electrode and grid.This encapsulation scheme back of the body gold process is complicated, good Rate is low, and uses silicon through hole (TSV) technical costs high.Therefore, industry is constantly looking for new encapsulating structure technology, to meeting Less encapsulating structure, higher heat conduction and excellent electric conductivity.

Summary of the invention

In order to overcome the deficiency of conventional MOS FET encapsulating structure and its implementation, this utility model provides a kind of MOSFET Encapsulating structure so that mosfet package have low drain-source connect resistance, simple in construction, package dimension is little, heat dispersion is excellent, And big electric current can be carried, improve production efficiency and reduce production cost.

The technical solution of the utility model is achieved in that

A kind of mosfet package structure, including silicon substrate and MOSFET chip, described MOSFET chip front side comprises active Pole conductive pad and Gate Electrode Conductive pad, described MOSFET chip back includes drain region, and described drain region is coated with metal level, institute State silicon substrate and there is first surface and second surface corresponding thereto, described first surface is formed subsidence trough, described under Heavy bottom portion of groove is equipped with conductive layer, and this conductive layer extends on the first surface of described silicon substrate, and described MOSFET chip pastes Install in described subsidence trough, and the conduction bottom the drain region metal level of described MOSFET chip back and described subsidence trough Layer connect by metal bonding, described source conductive pad, described Gate Electrode Conductive pad and described Drain Electrodes Conductive pad be respectively formed on and The electric conductor of outside interconnection；On described silicon substrate front, electric conductor is encapsulated by protective layer with outer portion.

Further, described electric conductor is solder bump or copper post solder projection.

Further, on the drain region of described MOSFET chip back, metal layer material is aluminum, titanium, copper, silver, nickel, Jin Yi Kind.

Further, the MOSFET chip front side after attachment is micro-less than 50 with the difference in height of described silicon substrate first surface Rice.

Further, described conductive layer, described electric conductor are single layer structure or multiple structure, its material include aluminum, titanium, Copper, stannum, silver, nickel, the one of gold.

Further, the planar dimension of described conductive layer is less than the planar dimension of described silicon substrate.

Further, described MOSFET chip back realizes electrically connecting with described conductive layer by slicken solder.

Further, there is a layer insulating between described conductive layer and described silicon substrate.

Further, described subsidence trough becomes lumen type or groove-shaped, and the sidewall of described subsidence trough is vertical with bottom or inclines Tiltedly.

The beneficial effects of the utility model are:

(1) this utility model is by mode shapes in silicon substrate first surface and subsidence trough thereon such as sputtering, plating Become conductive layer, MOSFET chip back is mounted in subsidence trough, makes conductive layer direct with MOSFET chip back drain region Contact forms Ohmic contact, through conductive layer, the drain region of MOSFET chip back can be guided to substrate first surface, i.e. MOSFET Chip front side, as the drain electrode of MOSFET chip, it is achieved that source electrode, grid, the same plane distribution of drain electrode, this structure contracts Short MOSFET chip and extraneous interconnection distance, enhance the conductive effect of chip, and MOSFET chip and big of conductive layer Long-pending contact, heat dispersion is excellent.This utility model encapsulating structure is simple simultaneously, improves encapsulation yield.

(2) comparing the encapsulation of conventional MOS FET, the method for packing that the utility model proposes is carried out based on whole wafer, and It is not based on single to carry out, is a kind of wafer-class encapsulation, have that production efficiency is high, heat dispersion is excellent, the cycle is short, be packaged into This low advantage.

Accompanying drawing explanation

Fig. 1 is MOSFET chip structure schematic diagram in this utility model；

Fig. 2 is the silicon substrate structural representation in this utility model with subsidence trough；

Fig. 3 be in this utility model bottom subsidence trough and silicon substrate first surface formed titanium copper Rotating fields schematic diagram；

Fig. 4 be in this utility model on titanium copper layer the structural representation of stannum silver layer；

Fig. 5 is the structural representation mounting in subsidence trough by MOSFET chip back in this utility model；

Fig. 6 is will to form protective layer reserved opening in MOSFET chip front side and basic first surface in this utility model Structural representation；

Fig. 7 is the structural representation making pad in this utility model at reserved opening part；

Fig. 8 is to make electric conductor in this utility model on pad, forms the schematic diagram of mosfet package structure；

Fig. 9 is the top view of this utility model mosfet package structure one embodiment；

Figure 10 is the top view of this utility model mosfet package another embodiment of structure；

Figure 11 is the vertical view of the embodiment that electric conductor is shaped as cuboid projection in this utility model mosfet package structure Figure；

Following description is done in conjunction with accompanying drawing

100-silicon substrate, 101-subsidence trough, 200-MOSFET chip, 201-source conductive pad, 202-Gate Electrode Conductive pad, 203-metal level, 301-Drain Electrodes Conductive pad, 302-titanium copper layer, 303-stannum silver layer；401-the first electric conductor, 402-second conducts electricity Body, 403-the 3rd electric conductor, 500-protective layer, 601-drain pad, 602-source pad, 603-gate pads, 701-drains Opening, 702-source contact openings, 703-gate openings,

Detailed description of the invention

For enabling this utility model more understandable, below in conjunction with the accompanying drawings detailed description of the invention of the present utility model is done in detail Thin explanation.For convenience of description, in the structure of embodiment accompanying drawing, each ingredient does not presses normal rates scaling, therefore does not represent enforcement The actual relative size of each structure in example.Structure described in present embodiment or upper, the above or upside in face, also include that centre has The situation of other layers.

As shown in Fig. 8, Fig. 9, Figure 10, a kind of mosfet package structure, including silicon substrate 100 and MOSFET chip 200, institute Stating MOSFET chip front side and include source conductive pad 201 and Gate Electrode Conductive pad 202, described MOSFET chip back includes leakage Polar region, drain region makes and has metal level 203, described silicon substrate to have first surface and second surface corresponding thereto, described Being formed with subsidence trough 101 on first surface, be equipped with conductive layer bottom described subsidence trough, this conductive layer extends to described On the first surface of substrate, as Drain Electrodes Conductive pad 301, described MOSFET chip back mounts the end of described subsidence trough Metal level in portion, and described MOSFET chip back drain region and the conductive layer bottom described subsidence trough pass through metal bonding Connecting, described source conductive pad, described Gate Electrode Conductive pad and described Drain Electrodes Conductive pad are respectively formed on and the conduction of outside interconnection Body；In described substrate front side, electric conductor is encapsulated by protective layer 500 with outer portion.

In this utility model mosfet package structure, grid control source electrode to drain electrode current switching, due to known respectively The concrete structure of MOSFET chip is variant, in Fig. 8 is simplified MOSFET chip source electrode and grid, and concrete raceway groove is not marked Illustrate.Such as grid not in the front of MOSFET chip, the front of MOSFE chip can be caused by internal circuit.In the present embodiment, Electric conductor includes the first electric conductor 401 being formed on Drain Electrodes Conductive pad, the second electric conductor 402 being formed on source conductive pad With the 3rd electric conductor 403 being formed on Gate Electrode Conductive pad, as the signal connection end mouth of mosfet package structure Yu external circuit. Preferably, first, second, third electric conductor can be solder bump, solder projection etc., salient point or projection include single structure or Multiple structure, its material includes aluminum, titanium, copper, stannum, silver, nickel, the one of gold, is a salient point in the present embodiment, and salient point material is permissible For pure tin or sn-ag alloy.In other embodiments, electric conductor shape can be a cuboid projection, as shown in figure 11.

Preferably, corresponding source conductive pad, Gate Electrode Conductive pad, the opening part system of Drain Electrodes Conductive pad can be reserved on the protection layer Make pad, on pad, then make electric conductor.So, the electrical of drain region leads to chip front side formation leakage by conductive layer Pole pad 601, forms the first electric conductor 401 in drain pad, and the chip front side that electrically leads to of source conductive pad forms source Pole pad 602, forms the second electric conductor 402 in source pad, and the chip front side that electrically leads to of Gate Electrode Conductive pad forms grid Pole pad 603, forms the 3rd electric conductor 403 in gate pads.

Conductive layer can be single layer structure or multiple structure, and its material includes aluminum, titanium, copper, stannum, silver, nickel, the one of gold. In the present embodiment, the conductive layer of mosfet package structure is double-layer structure, and lower floor is titanium copper layer 302, and upper strata is stannum silver layer 303, each layer thickness scope is 0.5 μm-20 μm, is formed on a silicon substrate by modes such as sputtering, plating.Formed conductive layer with The metal level of MOSFET chip back drain region is connected together to form Ohmic contact by stannum silver soldering, so, and MOSFET chip Back-side drain district electrically draws by the way of stannum silver conductive layer, as the drain electrode of MOSFET chip, can realize source electrode, grid, The same EDS maps of drain electrode.Therefore, this utility model technique is simple, and cost reduces；And MOSFET chip connects with conductive layer large area Touch and ensure that the radiating effect that chip is good.In other embodiments, the conductive layer of mosfet package structure is a Rotating fields, leads Electric layer is a titanium copper layer, needs to place on the conductive layer of the subsidence trough bottom position of MOSFET chip and be Xi Yin on substrate Layer, the metal level of MOSFET chip back is bonded with the stannum silver layer on subsidence trough bottom conductive layer, it is achieved be electrically connected with.

Preferably, the planar dimension of described conductive layer is less than the planar dimension of described silicon substrate.I.e. conductive layer does not extends to The edge of silicon substrate, so that described protective layer is coated with described conductive layer, it is to avoid conductive layer exposes and corroded by steam etc..

Preferably, the MOSFET chip front side after attachment and the difference in height of described silicon substrate first surface are less than 50 microns. More preferably, the degree of depth of silicon substrate subsidence trough and MOSFET chip thickness close to identical or identical, i.e. the front of MOSFET chip Basic and silicon substrate upper surface flush.

Preferably, described MOSFET chip back realizes electrically connecting with described conductive layer by slicken solder.

Preferably, solder bump that described drain electrode, source electrode, grid are corresponding or the respective quantity of projection are more than or equal to 1.

Preferably, there is a layer insulating between described conductive layer and described silicon substrate.Such as silicon dioxide, prevent chip from leaking Electricity, improves reliability.

The shape of subsidence trough can be lumen type, and its top view is as shown in Figure 2.It is alternatively channel-type, its top view such as Fig. 3 institute Show.The sidewall of subsidence trough is vertical with bottom or tilts.

As a kind of preferred implementation, the manufacture method of this utility model a kind of mosfet package structure, including following Step:

A, see Fig. 1, it is provided that some MOSFET chips 200, described MOSFET chip front side includes source conductive pad 201 With Gate Electrode Conductive pad 202, the metal level 203 on drain region and drain region is contained at the back side of described MOSFET chip, wherein, described All it is dielectrically separated between Gate Electrode Conductive pad and source conductive pad, drain region；

When being embodied as, some MOSFET chips can be formed by a MOSFET wafer cutting separation.

B, see Fig. 2, Fig. 3 and Fig. 4, it is provided that a surface has the silicon chip of some subsidence troughs 101, as silicon substrate 100, Have the plated surface conductive layer of subsidence trough at silicon chip, conductive layer covers bottom subsidence trough, and extends to silicon chip surface, as Drain Electrodes Conductive pad 301；Following steps are also to encapsulate on silicon chip, for ease of view, only draw the example of a unit.This reality Executing in example, conductive layer is two-layer, first sputters or electroplate one layer of titanium copper layer 302, sees Fig. 3, then is formed on stannum silver layer 303, See Fig. 4.Here silicon chip can be Silicon Wafer or silicon face plate.

C, see Fig. 5, the metal level 203 of MOSFET chip back bondd by conductive material or is welded to conductive layer, Drain region is made to electrically connect with conductive layer；

In other embodiments, conductive layer is a titanium copper layer, position bottom the subsidence trough needing placement MOSFET chip Doing stannum silver layer on the conductive layer put, MOSFET chip back-metal layer 203 is bonded with the stannum silver layer on bottom portion of groove conductive layer, real Now it is electrically connected with.

D, see Fig. 6, Fig. 7 and Fig. 8, prepare layer protective layer 500, described guarantor on the surface of silicon chip embedment MOSFET chip The described source conductive pad of exposure, described Gate Electrode Conductive pad and the opening of described Drain Electrodes Conductive pad it is reserved with, at opening part on sheath Preparation and the outside electric conductor (solder bump or solder projection) interconnected；It is also preferred that the left reserve corresponding source conductive on the protection layer Pad, the opening part of Gate Electrode Conductive pad, Drain Electrodes Conductive pad make pad (salient point UBM under metal), then make conduction on pad Body, to increase the adhesion etc. of solder bump or projection.Concrete, opening is by the drain openings 701 of corresponding Drain Electrodes Conductive pad, right The source contact openings 702 of source conductive pad and the gate openings 703 of corresponding Gate Electrode Conductive pad is answered to form；Pad is by corresponding drain openings The gate pads 603 of drain pad 601, the source pad 602 of corresponding source contact openings and corresponding gate openings form；Electric conductor By the first electric conductor 401 of corresponding drain pad, the second electric conductor 402 of corresponding source pad and the 3rd of corresponding gate pads the Electric conductor 403 forms.Salient point or projection is prepared at opening part.Print solder paste or tin-ball electroplating can be passed through or plant the techniques such as ball, And form solder bump (such as stannum ball) by the method for backflow；Or plating forms solder bump, or plating forms solder bump (metal column) or solder projection (metal derby).The number of each electrode correspondence salient point or projection regards electrode area size, can suitably increase Add quantity.

E, cutting silicon chip, see Fig. 8, form single mosfet package structure.

Comparing the encapsulation of conventional MOS FET, the manufacture method of this utility model mosfet package structure is to enter based on whole wafer Row, it is a kind of wafer-level packaging, and avoids silicon via process, simplify processing step, reduce packaging cost, improve Production efficiency, has the advantage that production efficiency is high, the cycle is short, packaging cost is low.

Above example is referring to the drawings, is described in detail preferred embodiment of the present utility model.The skill of this area Art personnel by carrying out the amendment on various forms or change to above-described embodiment, but without departing substantially from the feelings of essence of the present utility model Under condition, all fall within protection domain of the present utility model.

Claims (9)

1. a mosfet package structure, it is characterised in that include silicon substrate (100) and MOSFET chip (200), described MOSFET chip front side includes source conductive pad (201) and Gate Electrode Conductive pad (202), and described MOSFET chip back includes Drain region, described drain region is coated with metal level (203), and described silicon substrate has first surface and the second table corresponding thereto Face, described first surface is formed subsidence trough (101), is equipped with conductive layer bottom described subsidence trough, and this conductive layer prolongs Extending on the first surface of described silicon substrate, this conductive layer extends to the part on silicon substrate first surface as Drain Electrodes Conductive pad (301), in described MOSFET chip attachment to described subsidence trough, and the drain region metal level of described MOSFET chip back with Conductive layer bottom described subsidence trough is connected by metal bonding, described source conductive pad, described Gate Electrode Conductive pad and described Drain Electrodes Conductive pad is respectively formed on and the electric conductor of outside interconnection；On described silicon substrate front electric conductor with outer portion by protective layer (500) encapsulating.

Mosfet package structure the most according to claim 1, it is characterised in that described electric conductor is solder bump or copper post Solder projection.

Mosfet package structure the most according to claim 1, it is characterised in that the drain region of described MOSFET chip back Upper metal layer material is aluminum, titanium, copper, silver, nickel, gold one.

Mosfet package structure the most according to claim 1, it is characterised in that the MOSFET chip front side after attachment and institute State the difference in height of silicon substrate first surface less than 50 microns.

Mosfet package structure the most according to claim 1, it is characterised in that described conductive layer, described electric conductor are single Rotating fields or multiple structure, its material includes aluminum, titanium, copper, stannum, silver, nickel, the one of gold.

Mosfet package structure the most according to claim 1, it is characterised in that the planar dimension of described conductive layer is less than institute State the planar dimension of silicon substrate.

Mosfet package structure the most according to claim 1, it is characterised in that described MOSFET chip back passes through soft soldering Expect to realize electrically connecting with described conductive layer.

Mosfet package structure the most according to claim 1, it is characterised in that between described conductive layer and described silicon substrate There is a layer insulating.

Mosfet package structure the most according to claim 1, it is characterised in that described subsidence trough becomes lumen type or groove-shaped, The sidewall of described subsidence trough is vertical with bottom or tilts.