CN206282838U - The integrated encapsulation structure of passive device and active device - Google Patents
The integrated encapsulation structure of passive device and active device Download PDFInfo
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- CN206282838U CN206282838U CN201621198970.8U CN201621198970U CN206282838U CN 206282838 U CN206282838 U CN 206282838U CN 201621198970 U CN201621198970 U CN 201621198970U CN 206282838 U CN206282838 U CN 206282838U
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- wiring layer
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Abstract
The utility model provides the integrated encapsulation structure of a kind of passive device and active device, including substrate, also including following structure：There is through hole and cavity filled with conductive material in the substrate inside；Some chips in cavity, the chip front side has metal pad；Positioned at the first conductive wiring layer and the first medium layer of substrate back；Positioned at second conductive wiring layer and second dielectric layer of substrate front side；Front soldered ball on the second conductive wiring layer；The metal pad of chip and the through hole filled with conductive material are electrically connected by the second conductive wiring layer；Through hole filled with conductive material electrically connects the three-dimensional induction structure of composition by the first conductive wiring layer；Second conductive wiring layer is electrically connected with front soldered ball.The utility model is embedded in active chip by substrate while making three-dimensional passive device, it is possible to increase the interconnection density inside encapsulating structure, the integrated module thickness of passive device and active device is greatly reduced, and further save the entire area of encapsulating structure.
Description
Technical field
The utility model is related to system in package field, especially a kind of buried chip package structure.
Background technology
Wafer scale or panel level type encapsulation employed in semiconductor packaging industry is capable of achieving more large area overall package, enters
One step increases packaging efficiency, reduces packaging cost, is expected to turn into following packaging trend in this area.And the encapsulation of flush type type can enter
One step ground increases packaging density, greatly reduces interconnection length in encapsulation, so as to improve encapsulation performance on the whole, reduces encapsulation
The electrical loss of introducing.
In current passive device and the integrated encapsulation structure of active device, it is general using Silicon Wafer as support plate, in advance
Cavity is formed on Silicon Wafer, it would be desirable in the embedment cavity such as the chip of encapsulation, device, made by Silicon Wafer front and connected up again
Layer realizes that chip chamber is interconnected, and is realized and external electrical connections by the soldered ball for connecting up again.
But, in the integrated encapsulation structure of current existing passive device and active device, only Silicon Wafer is used as to carry
Plate, interconnection is realized between different chips or device by the positive wiring layer again of Silicon Wafer, and interconnection density is low, the only conduct of support plate body
Physical support, wastes large area.In addition, main flow module is to fit to active chip finished product and passive device finished product at present
Together, the original encapsulation of passive device can occupy larger area, be unfavorable for that encapsulating structure is further minimized.
The content of the invention
For the deficiencies in the prior art, the utility model provides the integrated envelope of a kind of passive device and active device
Assembling structure, it is possible to increase the interconnection density inside encapsulating structure, and it is further by being directly integrated inside substrate passive device
Save the entire area of encapsulating structure.The technical solution adopted in the utility model is：
The integrated encapsulation structure of a kind of passive device and active device, including substrate, also including following structure：
There is through hole and cavity filled with conductive material in the substrate inside；
Some chips in cavity, the chip front side has metal pad；
Positioned at the first medium layer of first conductive wiring layer of the first conductive wiring layer and covering of substrate back；
Positioned at the second dielectric layer of second conductive wiring layer of the second conductive wiring layer and covering of substrate front side；
Front soldered ball on the second conductive wiring layer；
The metal pad of chip and the through hole filled with conductive material are electrically connected by the second conductive wiring layer；Filled with leading
The through hole of electric material is electrically connected by the first conductive wiring layer；Second conductive wiring layer is electrically connected with front soldered ball.
Further, the through hole filled with conductive material, be used in the first conductive wiring layer to connect the circuit of through hole, and
One end is directly connected to the railway superstructures three-dimensional induction structure of through hole in second conductive wiring layer.
Further, chip passes through bonding die sticker in cavity bottom.
Further, bonding die glue can be conducting resinl, non-conductive adhesive.
Further, being made on the first conductive wiring layer of substrate back has backside pads, and backside pads are situated between by first
Expose first medium layer in opening on matter layer.
Further, the through hole filled with conductive material is cylinder or square column type.
Further, cavity is to substrate front side opening.
Further, chip includes active chip and/or passive chip.
Further, the first conductive wiring layer and the second conducting wiring layer material are copper, nickel, tin, silver, gold or alloy.
Further, first medium layer and second dielectric layer are polymeric medias.
The utility model has the advantage of：The utility model is embedded in by substrate while making three-dimensional passive device
Active chip, it is possible to increase the interconnection density inside encapsulating structure, is greatly reduced the integrated module of passive device and active device
Thickness.
1）The positive back side of substrate all has conductive wiring layer, can improve package interior interconnection density.
2）Inside substrate nothing is made using through hole and the conductive wiring layer at the positive back side of substrate filled with conductive material
Source device, improves integrated level, reduces the use of discrete passive component, further saves the entire area of encapsulating structure.
Brief description of the drawings
Fig. 1 is structure composition schematic diagram of the present utility model.
Specific embodiment
With reference to specific drawings and Examples, the utility model is described in further detail.
As shown in figure 1, the utility model proposes passive device and active device integrated encapsulation structure, including following knot
Structure：
There is through hole 2 and cavity 101 filled with conductive material in one piece of substrate 1, the inside of the substrate 1；
Some chips 6 in cavity 101, the front of the chip 6 has metal pad 601；Chip 6 passes through bonding die glue
5 are affixed on the bottom of cavity 101；
Positioned at the first medium layer 4 of first conductive wiring layer of the first conductive wiring layer 3 and covering at the back side of substrate 1；
Positioned at the second dielectric layer 8 of the second conductive wiring layer of positive second conductive wiring layer 7 of substrate 1 and covering；
Front soldered ball 9 on the second conductive wiring layer 7；
The metal pad 601 of chip and the through hole 2 filled with conductive material are electrically connected by the second conductive wiring layer 7；Fig. 1
In two through holes 2 filled with conductive material electrically connected by the first conductive wiring layer 3；Second conductive wiring layer 7 and face bonding
Ball 9 is electrically connected.Through hole 2 filled with conductive material, it is used in the first conductive wiring layer 3 to connect the circuit of through hole 2, and second
One end is directly connected to the circuit of through hole 2 and may be constructed three-dimensional induction structure in conductive wiring layer 7.
Specifically, substrate 1 can be silicon, glass or other materials.
Specifically, the through hole 2 filled with conductive material can be cylinder, square column type or other shapes；Its packing material
Can be copper, nickel, tin, silver, the conductive material such as gold or other metals, alloy.
Specifically, to the front openings of substrate 1, shape can be cuboid or other shapes to cavity 101.
Specifically, chip 6 can be active chip, passive chip or other chips；The material of metal pad 601 can be
Copper, nickel, tin, silver, the conductive material such as gold or other metals, alloy.
Specifically, bonding die glue 5 can be conducting resinl, non-conductive adhesive, or the other materials with paste functionality.
Specifically, the first conductive wiring layer 3 and the material of the second conductive wiring layer 7 can be copper, nickel, tin, silver, gold or other
The conductive materials such as metal, alloy.
Specifically, first medium layer 4 and second dielectric layer 8 can be polymeric media or other media.
Specifically, the material of front soldered ball 9 can be copper, nickel, tin, silver, the conductive material such as gold or other metals, alloy.
Operation principle：Conductive wiring layer positioned at the positive back side of substrate can serve as the electrical connection of chip chamber, realize packaging body
Internal high density interconnection.Furthermore it is possible to using the through hole 2 inside substrate filled with conductive material and the substrate positive back side
Conductive wiring layer make passive device, improve integrated level, reduce discrete passive component use, further save encapsulating structure
Entire area.For example, two through holes 2 in Fig. 1 are interconnected by the first conductive wiring layer 3 of substrate back, inductance can be formed
（Passive device）.
Further, backside pads 301 can be made on first conductive wiring layer 3 at the back side of substrate 1, backside pads 301 lead to
Expose first medium layer 4 in the opening crossed on first medium layer 4；By the backside pads 301 on the first conductive wiring layer 3, can paste
Other chips are filled, realizes that three-dimensional chip is integrated.
Claims (10)
1. a kind of integrated encapsulation structure of passive device and active device, including substrate（1）, it is characterised in that also including following
Structure：
The substrate（1）There is the through hole filled with conductive material in inside（2）And cavity（101）；
It is some positioned at cavity（101）Interior chip（6）, the chip（6）Front has metal pad（601）；
Positioned at substrate（1）First conductive wiring layer at the back side（3）With the first medium layer of the first conductive wiring layer of covering（4）；
Positioned at substrate（1）Positive second conductive wiring layer（7）With the second dielectric layer of the second conductive wiring layer of covering（8）；
Positioned at the second conductive wiring layer（7）On front soldered ball（9）；
The metal pad of chip（601）With the through hole filled with conductive material（2）By the second conductive wiring layer（7）Electrical connection；
Through hole filled with conductive material（2）By the first conductive wiring layer（3）Electrical connection；Second conductive wiring layer（7）With face bonding
Ball（9）Electrical connection.
2. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Through hole filled with conductive material（2）, the first conductive wiring layer（3）In for connecting through hole（2）Circuit, and second
Conductive wiring layer（7）Middle one end is directly connected to through hole（2）Railway superstructures three-dimensional induction structure.
3. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Chip（6）By bonding die glue（5）It is affixed on cavity（101）Bottom.
4. the integrated encapsulation structure of passive device as claimed in claim 2 and active device, it is characterised in that
Bonding die glue（5）It is conducting resinl or non-conductive adhesive.
5. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Substrate（1）First conductive wiring layer at the back side（3）Upper making has backside pads（301）, backside pads（301）By first
Dielectric layer（4）On opening expose first medium layer（4）.
6. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Through hole filled with conductive material（2）It is cylinder or square column type.
7. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Cavity（101）To the front openings of substrate 1.
8. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
Chip（6）Including active chip and/or passive chip.
9. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
First conductive wiring layer（3）With the second conductive wiring layer（7）Material is copper, nickel, tin, silver, gold or alloy.
10. the integrated encapsulation structure of passive device as claimed in claim 1 and active device, it is characterised in that
First medium layer（4）And second dielectric layer（8）It is polymeric media.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621198970.8U CN206282838U (en) | 2016-11-07 | 2016-11-07 | The integrated encapsulation structure of passive device and active device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621198970.8U CN206282838U (en) | 2016-11-07 | 2016-11-07 | The integrated encapsulation structure of passive device and active device |
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| CN206282838U true CN206282838U (en) | 2017-06-27 |
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| CN201621198970.8U Active CN206282838U (en) | 2016-11-07 | 2016-11-07 | The integrated encapsulation structure of passive device and active device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511431A (en) * | 2018-05-21 | 2018-09-07 | 佛山市国星光电股份有限公司 | A kind of LED display unit group and display panel |
| CN111653520A (en) * | 2017-08-31 | 2020-09-11 | 长江存储科技有限责任公司 | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN113555337A (en) * | 2021-05-27 | 2021-10-26 | 日月光半导体制造股份有限公司 | Semiconductor substrate structure and forming method thereof |
| WO2021227912A1 (en) * | 2020-05-14 | 2021-11-18 | 上海新微技术研发中心有限公司 | Silicon-based optoelectronic device based on silicon photonics interposer technology, and preparation method therefor |
| CN114695339A (en) * | 2020-12-25 | 2022-07-01 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method thereof |
| WO2024114182A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Highly integrated heterogeneous package substrate and module |
| WO2024114181A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and heterogeneous package module |
-
2016
- 2016-11-07 CN CN201621198970.8U patent/CN206282838U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653520A (en) * | 2017-08-31 | 2020-09-11 | 长江存储科技有限责任公司 | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN111653520B (en) * | 2017-08-31 | 2021-05-25 | 长江存储科技有限责任公司 | Method for forming three-dimensional integrated wiring structure and semiconductor structure thereof |
| CN108511431A (en) * | 2018-05-21 | 2018-09-07 | 佛山市国星光电股份有限公司 | A kind of LED display unit group and display panel |
| WO2021227912A1 (en) * | 2020-05-14 | 2021-11-18 | 上海新微技术研发中心有限公司 | Silicon-based optoelectronic device based on silicon photonics interposer technology, and preparation method therefor |
| CN114695339A (en) * | 2020-12-25 | 2022-07-01 | 京东方科技集团股份有限公司 | Substrate integrated with passive device and preparation method thereof |
| CN113555337A (en) * | 2021-05-27 | 2021-10-26 | 日月光半导体制造股份有限公司 | Semiconductor substrate structure and forming method thereof |
| WO2024114182A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Highly integrated heterogeneous package substrate and module |
| WO2024114181A1 (en) * | 2022-11-30 | 2024-06-06 | 深圳飞骧科技股份有限公司 | Heterogeneous package substrate and heterogeneous package module |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180928 Address after: Room 987, Room 1303, 99 South Second Road, Songyu, Xiamen China (Fujian) Free Trade Experimental Zone, 361000 Patentee after: Xiamen Yun Tian Semiconductor Technology Co., Ltd. Address before: 214116 No. 45, joint East Industrial Park, 58 Jinghong Road, Xishan District, Wuxi, Jiangsu. Patentee before: WUXI JIMAI MICROELECTRONICS CO., LTD. |