CN1777988A - 条带引线框和其制作方法以及在半导体包装中应用的方法 - Google Patents
条带引线框和其制作方法以及在半导体包装中应用的方法 Download PDFInfo
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- CN1777988A CN1777988A CNA038228351A CN03822835A CN1777988A CN 1777988 A CN1777988 A CN 1777988A CN A038228351 A CNA038228351 A CN A038228351A CN 03822835 A CN03822835 A CN 03822835A CN 1777988 A CN1777988 A CN 1777988A
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- described method
- lead frame
- metal parts
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Abstract
本发明提供了一种用于制造电子包装的条带引线框。该条带引线框是由一个条带和一个引线框组成,引线框由多个接合在条带上并排列成区域图案的独立金属部件组成。制造本发明的方法使得传统引线框的厚度明显减少,导致较薄的包装,使得散热得到了改善,并且较短的几何尺寸使得电气性能得到改善。多个这种引线框在一个条带上排列成一个阵列,并且每个引线框通过条带上的芯片间隔区和周围的引线框隔离开来,以至于没有金属部件延伸到芯片间隔区域。集成电路芯片和引线框接触并电连接,并且采用了一种封装材料,在引线框和芯片间隔区上硬化干燥。其后,该条带被去除,该引线框通过切割芯片间隔区的封装材料进行单元化,形成独立的包装。单元化是在芯片间隔区进行的并且不会切割到形成引线框的任何金属部件。
Description
发明领域
本发明主要涉及引线框及其在制造电子元件包装之中的应用。特别是,本发明涉及一种条带引线框及其制造方法,和在制作半导体电子包装中的应用。
发明背景
引线框通常是通过对一个金属薄膜蚀刻或者冲压形成特定的形状和尺寸。精密结构的引线框通常就像非常精美的刺绣,或是类似模板的金属结构。这样的传统引线框在工业中用来制造多种芯片包装,包括引线结合器以及倒装晶片包装。
传统引线框缺乏结构刚性。引线框的指状部分非常脆弱并且在处理过程中位置很难固定。这导致组装过程中的处理瑕疵、损坏和变形。
在制作集成电路尺寸包装的自动化过程中,厂商通常在一个分块矩阵中形成多个互连引线框,在块中将芯片和每一个引线框粘合并且电连接,将芯片/引线框封装起来,对每个引线框的连接处之间的金属进行背面蚀刻,然后将每个芯片/引线框单独锯开形成独立的包装。然而,在传统的过程中,块中的引线框相互之间互连直到单元化步骤。在单元化处理过程中,锯条厚度不仅从封装塑料中切过,而且还切过了块中将引线框连接在一起的金属连接。锯条在附属物以及芯片和引线框之间的粘合处和电连接处施加了过度的力量和振动。这将导致结构缺陷,如金属—塑料分界面的分层。本发明解决了这些问题。
发明内容
本发明提供了一种用于电子封装的条带引线框。本发明包括接合有一个一次性的条带或载体的被蚀刻的金属部分,从而形成一个区域图案的引线框外形。这个条带或者载体可以固定金属部件,通过层叠、黏贴或者其他合适的方法表现一个引线框外形的最终形状。该引线框的金属部件为集成电路芯片提供了支撑以及电连接。在该发明的引线框中,在最终形状的样式里,每一个金属部件和其他的金属部件用一个单独的部件或者包装电隔离。这个发明还提供了在条带或者载体上制作引线框金属部件的方法。该方法包括给一个金属薄膜或层接合上一个条带、一个薄膜或是一个载体,用来形成对于单独包装的引线框部分,或者对金属薄膜进行构图,剩下所需的一组隔离金属部件来形成一个金属引线框。除此之外,在一个一次性的条带、薄膜、包括玻璃薄膜或者其他等同载体上,丝网印刷厚度均匀的厚金属薄膜认为也可实现同样的构造。
本发明还涉及一种采用依据本发明的一个引线框形成电子封装的方法。该方法包括根据本发明提供的一种引线框,并且将一个集成电路芯片和引线框的金属部件接合以及电连接。然后在条带的引线框上使用一种封装材料并且硬化。移除条带,带有牢固嵌入的引线框金属部件的封装部分单元化,通过设计不接触任何隔离的金属部件,从而形成一个电子包装。
在一个优选实施例中,根据本发明,多个带状引线框形成一个阵列,用于电子包装的大规模生产。在这个实施例中多个单独金属引线框接合有一片条带。每个引线框被条带上的芯片间隔区域跟邻近的引线框分隔开来。各个金属部件排列在形成每个引线框的区域图案中,互相电隔离,并且没有金属部件延伸到芯片间隔区域。
多个电子包装可以使用带状引线框的排列来形成。在这个方法中,多个集成电路芯片在排列中都和每个引线框接触并且电连接。其后,在引线框和条带的芯片间隔区域上使用一种封装材料。在一个实施例中,封装步骤包括用一种可控的方法在引线框上使用封装材料,环绕该金属部件直到没有生成任何模塑溢料的条带表面。
一旦封装材料硬化干燥后,就去除条带。因为引线框之间电隔离,在单元化之前的这个阶段可以进行条带断裂强度测定。然后该阵列通过芯片间隔区域中的封装进行单元化,形成独立的电子包装。单元化可以通过锯断、激光切割、喷水切割或者其结合来完成。
本发明还包括一些可选择的部分。比如说,可接合引线和焊接成份可以提前设置在每一个金属部件的第一和第二表面的其中一个或者全部表面上。可接合引线和焊接成份可以是镍—钯—金底板镀层。
金属部分的厚度可以大约1-4密耳或者小于1密耳。条带是由一次性的和廉价的塑料材料制成,比如,聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4或者也可选择一个可以像玻璃薄膜、磨光塑料薄膜或者类似的可以移除或处理的等价载体。条带或者可替代的载体可以通过剥离、溶解或背面构图来进行移除。另外,加强件可以接合在条带的下层表面下,处理时提供额外的支持和硬度。使用加强件的地方,在处理过程中,在条带移除之前就要将其除去。
金属部分可以根据特定的生产包装来构造和排列成多种区域图案。比如,金属部分可以为了引线接合处理而包括一个用来支持集成电路芯片的印模焊盘,以及为了引线框和芯片间电连接的引线接点。金属部件还可以为了倒装晶片或者焊盘栅格阵列处理,而提供一种既能支持一个集成电路芯片又能对引线框和芯片进行电连接的引线连接点。
附图简要描述
图1a是根据本发明的含有多个片基的一个条带引线框的顶部视图。
图1b是显示图案部分的一个条带引线框片基的顶部视图,根据本发明,包括一个芯片焊盘以及焊盘周围的连接点。
图1c是沿图1b的C-C线的片基剖视图。
图1d是一个显示引线接合焊盘的集成电路芯片的底部视图。
图1e是根据本发明的一个将图1d的芯片安装在图1b的芯片焊盘上的顶部视图。
图1f是一个沿图1e的F-F线的剖视图,根据本发明,表示将图1d的芯片倒装接合在芯片焊盘上。
图1g是一个剖视图,根据本发明,表示芯片焊盘的引线接合到条带引线框的电连接点。
图1h是一个剖视图,根据本发明,表示几个条带引线框的封装,包括芯片和引线接合,形成一个块。
图1i是一个剖视图,根据本发明,表示从图1h的引线框的块中去除条带和加强件。
图1j是一个剖视图,根据本发明,表示图1i的块的单元化,其中锯条不碰到间隔区中条带引线框的任何金属部件。
图1k是根据本发明的一个单元化的条带引线框包装。
图1l是根据本发明的一个条带引线框片基的阵列或块的顶部视图。
图1m是图11的一部分,根据本发明,表示多个片基的较好的视图。
图1n是图1m的一部分,根据本发明,表示一个片基的细节顶部视图。
图1o是一个流程图,根据本发明,表示一个条带引线框包装的形成。
图2a是根据本发明的适用于倒装晶片的多个片基的一个条带引线框的顶部视图。
图2b是一个条带引线框片基的顶部视图,根据本发明,表示图案部分,包括接受倒装晶片的接点。
图2c是一个沿图2b的片基的C-C线的剖面图,根据本发明,其中也表示出了条带和可选的加强件。
图2d是根据本发明的一个带有焊料隆起的集成电路芯片的底部视图。
图2e是顶部视图,根据本发明,表示将图2d的芯片进行晶片倒装安装到条带引线框的电连接点上。
图2f是沿图2e的F-F线的一个剖视图,根据本发明,表示焊料隆起的焊料流动处理的开始。
图2g是一个剖视图,根据本发明,表示在对于倒装晶片的焊料流动处理后,图2f的焊料隆起的部分收缩。
图2h是一个剖视图,根据本发明,表示几个条带引线框的封装材料,包括芯片和连接点。
图2i是一个剖视图,根据本发明,表示从图2h的引线框的块上去除条带和加强件。
图2j是一个剖面图,根据本发明,表示图2i的块的单元化,其中锯条不接触间隔区中条带引线框的任何金属部分。
图2k根据本发明,表示一个带有倒装晶片的单元化的条带引线框包装。
图21一个倒装晶片包装的剖视图,根据本发明,表示在连接点形成的突边。
图2m根据本发明,是一个热增强的倒装晶片包装的剖视图。
图2n根据本发明,是一个近似芯片尺寸的倒装晶片包装的剖视图。
图2o根据本发明,是条带引线框片基的阵列或是块的顶部视图。
图2p是图2o的一部分,根据本发明,表示多个片基的较好视图。
图2q是图2m的一部分,根据本发明,表示对于倒装晶片的一个片基的细节顶部视图。
图2r是一个流程图,根据本发明,表示一个倒装晶片包装的形成。
图3a根据本发明,是一个条带引线框的顶部视图,包括多个适用于焊盘栅格阵列倒装晶片的片基。
图3b是一个条带引线框片基的顶部视图,根据本发明,表示图案连接部分。
图3c是一个沿图3b的C-C线的剖面图,根据本发明,其中还表示了条带和可选的加强件。
图3d根据本发明,是一个带有焊盘栅格阵列焊料隆起的一个集成电路芯片的底部视图。
图3e是一个剖视图,根据本发明,表示在对焊盘栅格阵列焊料隆起的焊料流动处理的开始时,图3d的两个倒装晶片安装在两个片基上。
图3f根据本发明,表示在焊料流动处理后,图3e的焊料隆起的部分折叠以及引线的封装,包括在一块模塑材料中的倒装晶片。
图3g是一个剖面图,根据本发明,表示条带的去除以及来自图3f的引线框的块的加强件。
图3h是一个剖视图,根据本发明,表示图3g的块的单元化,其中锯条不碰到间隔区域中的引线框的任何金属部件。
图3i根据本发明,表示一个已经单元化的条带引线框包装的剖视图,带有一个焊盘栅格阵列倒装晶片(TLGA)。
图3j根据本发明,是图3i的焊盘栅格阵列包装的一个底部视图。
图3k根据本发明,表示含256个焊盘的TLGA包装的一个剖视图以及一个底部视图。
图31根据本发明,表示含有144个焊盘的TLGA包装的一个剖视图以及一个底部视图。
图3m根据本发明,表示含有36个焊盘的TLGA包装的一个剖视图以及一个底部视图。
图3n根据本发明,是一个适用于焊盘栅格阵列倒装晶片的条带引线框片基的阵列或块的顶部视图。
图3o是图3n的一部分,根据本发明,表示多个片基的较好视图。
图3p是图3o的一部分,根据本发明,表示对于一个焊盘栅格阵列倒装晶片的一个片基的细部顶部视图。
图3q是一个流程图,根据本发明,表示一个焊盘栅格阵列包装的形成。
详细描述
图1a-1o表示对于引线接合芯片的条带引线框的一个阵列的形成,以及将其用在制作一个条带引线框包装中的方法。在图1a所示的一个顶部视图中,一条金属薄膜接合在条带(10)上。将条带附在金属薄膜上可以通过多种办法实现,包括传统的层叠技术或用一种粘合剂。除此以外,一个金属薄膜能被丝网印刷在一次性条带或薄膜上得到一个较薄的包装,其中包括玻璃薄膜载体。然后如图1a所示,对金属薄膜进行构图以形成一个带有每个金属部件的引线框(20)阵列。如图1b和1c所示,每个引线框含有多个金属部件,包括芯片基座(23)和围绕芯片焊盘的一组引线连接点(25)。含有芯片焊盘(23)的部件和引线连接点(25)的区域共同称为片基。一种可选的加强件(30)可以设置在条带的下表面上,在处理过程中来提供额外的机械稳定性。
条带(10)包括一种塑料材料,如聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4,并且厚度可以根据应用而改变。该金属薄膜,最好是铜或是铜合金,厚度可以在约1到4密耳之间,但是厚度也可以少于1密耳。该金属薄膜可以做得尽可能的薄,如经丝网处理,只要该金属可以粘合。优选地,在金属薄膜装配到条带上之前,对其进行预镀处理,该条带具有一个可接合的引线以及包含镍—钯—金底板镀层的可软焊成份。
一种构图的方法是将图案压印到金属上。其他的方法可以包括化学或者电化学蚀刻以及放电加工机床。优选的是照相平版印刷蚀刻。金属的蚀刻一直进行到达到条带表面为止。此外,因为蚀刻将部件间的以及引线框之间的所有金属都去除了,剩下的金属部分通过下面的条带固定在位置上。引线框之间没有金属的部分称之为“间隔区域”(15),如图1a、1h和1j所示。
图1a所示的条带,在下个处理步骤,即将芯片装配在引线框的芯片焊盘上之前,也被用作一个载体。一个沿着单面金属薄膜的弯曲的条带,能够很容易地适应传统的盘—盘装配线。然后,在下个装配线站点,将图1d所示的芯片(40)装配到芯片焊盘上。图1e表示一个芯片片基,其中芯片(40)背面结合到芯片基座(23)上。可以运用环氧树脂(47)并且通过使用焊料或者其他糊状或薄膜形式的低熔点材料,完成背面结合。在环氧树脂硬化后,芯片基座连接点(45)和引线连接点(25)通过运用引线接合技术的线(50)电连接,如图1g所示。因为根据本发明制成的引线框有一个持续的条带支撑,连接点(25)牢固安装并且固定在一个平面上,因形成了很好的结合,这提高了终端产品的可靠性。
如图1h所示,在芯片和相应的电连接点相互连接后,所有在金属薄膜和条带的正面的部件都被一种封装模塑材料(60)覆盖,如树脂。封装材料(60)在金属薄膜和所有暴露的表面上生成,包括引线框和它们的连接线(50)、芯片(40)、连接点(125)以及条带上的芯片间隔区域(15)。在公开的方法中,条带的存在防止了经常遇到的模塑溅在包装背面的覆盖区上的问题。
图1i表示条带(10)和可选的加强件(30)随后被去除。条带可以通过简单的剥离或者化学溶剂溶解来去除。成型的结构是一个形成在块中的引线框包装的阵列或是矩阵。然后该块在间隔区域部分(15)被单元化成多个电子包装(80),正如图1j所示。单元化可以通过多种方法实现,包括图1j中的锯断、喷水切割、激光切割或是它们的组合,或是其他特别适合切割塑料的技术。如图1k所示,每一个单元化的包装的底部表面被清洁并且为下一步处理做准备。经预镀处理的连接点和下一级包装连接。如果需要,已经清洁的连接头能进一步磨平或者进行闪焊,以改进连接。
引线框的一个块可以是与生产线上所需的生产性能相当的任何尺寸。图1l所示的是这个块的顶部视图。块的一部分显示在图1m中,同时片基在图1n中表示出来。用于形成本发明的一个条带引线框包装处理步骤总结,概括在图1o中。优选的步骤包括形成一个引线框片基(90),后面还有芯片或者硬模、附着。附着是通过使用焊料、其他低熔点金属或者一种随后在步骤(92)中硬化干燥的环氧树脂来实现的。接下来,芯片端子在步骤(93)中和引线连接点引线接合,随后被一种模塑材料(94)封装。接下来,在步骤(95)中条带被去除,此后,已成型模块被单元化(96),以生成独立的包装。
在图2r-2r所示的另一个实施例中,用于倒装晶片的形成条带引线框的方法,和将其用于形成倒装晶片电子包装的方法被公开。下面的处理过程和前面的那些实施例都类似,如图2a所示,一条金属薄膜接合在条带(100)上。该金属薄膜然后进行构图,形成带有形成片基(120)的金属部件的引线框的阵列,最好参看图2b。本实施例的特征包括一组引线连接点(125)。该连接点有带有终端(123)的短引线,它向着引线框中央延伸。短引线的终端在所示的下一个步骤中提供了在倒装晶片上加上焊料隆起的区域。图2b的片基的一幅剖视图显示在图1c上。
条带载体(100)最好是聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4。换句话说,可以使用如玻璃薄膜、磨光塑料薄膜或者类似的可以移除或处理的等价载体。该金属薄膜,最好是铜,厚度可以在约1到4密耳之间,厚度也可以小于1密耳。该金属薄膜可以做得尽可能的薄,只要该金属可以粘合。最好也可以在其装配到条带上之前,将金属薄膜进行预镀处理。
构图通过照相平版印刷蚀刻来完成。蚀刻将所有金属去除,除了形成片基的引线框中的部分,去除直到达到下层条带表面为止。因此引线框被如图2a、2h和2j所示的间隔区域(115)隔开。该引线框的部分通过下层条带固定在位置上,既不在引线框之间连接,也不在单个引线框片基中的部件之间连接。间隔区域内没有金属确保了在单元化处理中不会锯到任何金属,正如前面已经公开的实施例。正如上个实施例中,如图2c所示,可以在条带后采用一种类似的加强件(130)。
在下一个步骤中,翻转图2d所示的带有焊料隆起(145)的芯片(140),使得焊料隆起(145)如图2e和2f所示放置在部件(123)上。然后进行回流焊操作,并且焊料隆起稍微收缩,形成了如图2g所示的缩短了的焊料连接点(150)。具有加强件的条带的存在提供了所需的稳定性,来形成优良的倒装晶片结合,如图2g中所示。
在倒装晶片和引线框相连并且电连接后,如图2h所示,条带上的引线框在一种模塑材料中封装。封装体(160)围绕所有芯片和每个引线框片基上的所有部件而形成。
一旦封装材料硬化并干燥,便去除条带和可选的加强件。条带的去除可以用前面提到的多种方法完成。产品的结构是一个形成在块中的引线框包装的阵列或是矩阵,如图2i所示。因为块中的引线框相互之间电隔离,所以块或者剥离测试可以优先于单元化,在这个阶段进行。然后块在间隔区域部分(115)处被单元化,成为如图2j所示的多个电子包装(180)。图2k所示的每个单元化包装的底部表面被清洁并且为下一步处理做好准备。预镀连接点可以和下一级包装连接。如果需要,已经清洁的连接头能进一步磨平或者为了改进连接而进行闪焊。
图2l、2m和2n表示不同类型的电子包装,可以通过运用已公开的形成条带引线框包装的方法来得到。图2l是图2k的放大视图,其中在连接引线下切割的部分称为“突边”(127),可以比较清楚的看见。该突边可以在条带去除后封装之前,从底部表面通过半蚀刻连接引线(125)的延长部分来形成。这种方法防止引线/连接延长部分在封装过程中暴露给焊料隆起结合盘的位置。而且,突边抓住并锁住模塑材料,因此使模塑材料很难从结合表面分开。作为进一步锁定机构,部件的垂直侧被构图,带有随后可将模塑材料夹住的凹角部件,而且防止金属—封装材料分界面脱胶。在图2m中的另外的实施例中,替代焊料隆起(155)以及焊盘(145)为增加的热量提供了一个热量通道。而且如图2n所示,连接点(125)能缩短以提供一个近似于芯片尺寸的包装。
图2o表示对于倒装晶片的条带引线框的一个块的顶部视图。该块的一部分显示在图2p中,图2q表示一个片基。图2r表示一个用于形成该包装的处理步骤的概要。优选的步骤包括在倒装晶片安装以及焊料回流(192)之后形成引线框片基(190)。接下来,采用模塑材料进行封装(194)。然后,条带背衬在步骤(196)中去除,如果有加强件的话,加强件也被去除,其后,模制的块被单元化(198),从而形成一个独立的倒装晶片包装。
在图3a-3q中显示的另一个实施例中,公开了形成一个条带焊盘栅格阵列包装的方法,以及将其用在形成焊盘栅格阵列电子包装的方法。焊盘栅格阵列电子包装的处理步骤和已公开的倒装晶片包装的处理步骤非常接近。本实施例导致形成实际芯片尺寸的包装,拥有较小的覆盖区和更集成化的部件。
即,参见图3a中所示,如前述实施例中,一个金属薄膜条接合在条带(200)上。然后金属薄膜被构图,来形成一个带有形成片基(220)部件的引线框阵列,最好看图3b。本实施例的部件包括一组圆形引线连接点(225)。图3b中片基的剖视图显示在图3c中。图3c还表示了可选的加强件(230)。
构图可通过运用照相平版印刷蚀刻来完成。蚀刻将所有金属去除,除了形成片基(220)的引线框中的部分,去除直到达到下层条带表面为止。引线框被间隔区域(215)隔开,同时该引线框的部分通过下层条带固定在位置上。
在下个步骤中,集成电路芯片和引线框相接合并电连接。图3d所示的芯片(240)拥有一个焊料隆起(245)的焊盘栅格阵列。在每个片基(220)中在连接点(125)之间隔开的空间中对应形成焊料隆起。如图3e所示,翻转芯片使得焊料隆起(245)放置在部件(225)上。图3e表示两个这样的带有两个焊料焊料隆起芯片的片基,但是最好看图3f。进行焊料回流操作使得焊料隆起稍微收缩并且形成了如图3f所示的缩短了的焊料连接点(250)。
同样如图3f所示,在倒装晶片和引线框的相接合并电连接后,条带上的引线框被一种模塑材料封装。封装材料(260)在芯片周围和下面形成。条带的存在防止了模塑材料溅在包装背面的覆盖区,这是常见的问题。
一旦封装材料硬化并干燥,条带和可选的加强件就被去除。条带的去除可以通过包括简单的剥离或者化学溶剂溶解在内的多种方法实现。如图3g所示,产品的结构是一个形成在块中的引线框包装的阵列或是矩阵。然后该块在间隔区域部分(215)被单元化成多个电子包装(280),不切割到任何金属,正如图3h所示。
图3i表示包装之一的放大图。包装的区域和芯片面积很接近,除了包装侧面的模塑材料(260)的厚度。芯片上的焊料隆起直接排列,部件(225)和下一级包装相连。参见图3j所示的包装得底部视图可看得更清晰。如果需要,已经清洁的连接头能进一步磨平或者为了改进连接而进行闪焊。图3k-3m表示带有一个“突边”的焊盘栅格阵列包装的其它例子。图3k表示含有256个焊盘的包装,而图3l表示表示一个含有144个焊盘的类似包装。图3m中的包装含有36个焊盘。
和图1l以及2o类似,图3n表示一个条带引线框的顶部视图,用于带有焊料隆起的焊盘栅格阵列的倒装晶片。图3o表示该块的一部分,图3p表示一个片基。图3q总结了形成一个焊盘栅格阵列包装的处理步骤的梗概。优选的步骤包括在焊盘栅格阵列倒装晶片安装,以及焊料回流(301)之后形成引线框片基(300)。接下来,采用模塑材料进行封装(303)。然后条带背衬在步骤(305)中去除,如果有加强件的话,加强件也被去除;模塑的块被单元化(307),从而形成一个独立的TLPF包装。
本发明使得传统引线框的厚度明显减少,导致较薄的包装,使得散热得到了改善,并且较短的几何尺寸使得电气性能得到改善。这就提供了大量生产极薄的包装的机会。
虽然本发明基于特定的实施例进行了特别图示以及描述,但该领域的技术人员应当理解,不脱离本发明的精神和范围,可以作出各种形式和细节上的修改。
Claims (86)
1、一种条带引线框包括:
一个条带;以及
一个引线框,由多个接合在条带上的独立金属部件形成,并且排列成一个区域图案,为一个集成电路芯片提供支撑和电连接,图案上的每个金属部件和其它金属部件相互电隔离。
2、根据权利要求1所述的条带引线框,还包括一个可接合引线和预镀在每个金属部件的第一和第二表面之一或全部的可软焊成份。
3、根据权利要求2所述的条带引线框,其中可接合引线和可软焊成份是镍—钯—金底板镀层。
4、根据权利要求1所述的条带引线框,其中条带和金属部件通过条带上的粘合剂接合。
5、根据权利要求1所述的条带引线框,其中条带和金属部件通过叠层接合。
6、根据权利要求1所述的条带引线框,其中金属部件被丝网印刷在一个一次性条带、薄膜上,包括玻璃薄膜或者其它类似载体。
7、根据权利要求1所述的条带引线框,还包括一种设置在条带下表面的加强件。
8、根据权利要求1所述的条带引线框,其中金属部分厚度大约1-4密耳。
9、根据权利要求1所述的条带引线框,其中金属部分厚度约小于1密耳。
10、根据权利要求1所述的条带引线框,其中条带由塑料材料构成。
11、根据权利要求10所述的条带引线框,其中条带由聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4构成。
12、根据权利要求1所述的条带引线框,其中区域图案中的金属部件包括一个印模焊盘,用于支撑一个集成电路芯片;和引线连接点,用于电连接引线框和芯片。
13、根据权利要求12所述的条带引线框,其中引线框为引线接合芯片提供支持和连接。
14、根据权利要求1所述的条带引线框,其中区域图案中的金属部分包括一个引线连接点,用于支撑一个集成电路芯片和电连接引线框和芯片。
15、根据权利要求14所述的条带引线框,其中引线框为倒装晶片或者焊盘栅格阵列芯片提供支持和连接。
16、根据权利要求1所述的条带引线框,其中条带可以通过剥离、溶解或者背面构图来加以去除。
17、一种用于大规模制造电子包装的条带引线框阵列包括:
一个条带;以及
多个与条带接合的独立的金属引线框,每个引线框通过条带上的芯片间隔区域和邻近的引线框分开,每个引线框包括排列成区域图案的多个独立金属部件,图案中的每个金属部件和其它金属部件电隔离,并且没有金属部件延伸到芯片间隔区域。
18、根据权利要求17所述的条带引线框阵列,还包括一个可接合引线和预镀在每个金属部件的第一和第二表面之一或全部的可软焊成份。
19、根据权利要求17所述的条带引线框阵列,其中可接合引线和可软焊成份是镍—钯—金底板镀层。
20、根据权利要求17所述的条带引线框阵列,其中条带和金属部件通过条带上的粘合剂接合。
21、根据权利要求17所述的条带引线框阵列,其中条带和金属部件通过叠层接合。
22、根据权利要求17所述的条带引线框阵列,还包括一种设置在条带下表面的加强件。
23、根据权利要求17所述的条带引线框阵列,其中金属部分厚度大约1—4密耳。
24、根据权利要求17所述的条带引线框阵列,其中金属部分厚度约小于1密耳。
25、根据权利要求17所述的条带引线框阵列,其中条带由塑料材料构成。
26、根据权利要求25所述的条带引线框阵列,其中条带由聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4构成。
27、根据权利要求17所述的条带引线框阵列,其中区域图案中的金属部件包括一个印模焊盘,用于支撑一个集成电路芯片;和引线连接点,用于电连接引线框和芯片。
28、根据权利要求27所述的条带引线框阵列,其中引线框为引线接合芯片提供支持和连接。
29、根据权利要求17所述的条带引线框阵列,其中区域图案中的金属部分包括引线连接点,用于支撑一个集成电路芯片,和电连接引线框和芯片。
30、根据权利要求29所述的条带引线框阵列,其中引线框为倒装晶片或者一个焊盘栅格阵列芯片提供支持和连接。
31、根据权利要求17所述的条带引线框阵列,其中条带可以通过剥离、溶解或者背面构图从金属部件中去除。
32、一种形成引线框的方法包括以下步骤:
提供一种金属薄膜;
将一个条带和该薄膜接合;并且
对该薄膜进行构图,在条带上留下一个金属引线框,该引线框包括多个排列成区域图案的金属部件,图案中的每个金属部件和其它金属部件电隔离。
33、根据权利要求32所述的方法,还包括使用一种可接合引线以及可软焊成份对薄膜的上或下表面或者两面进行预镀的步骤。
34、根据权利要求33所述的方法,其中成份是镍—钯—金底板镀层。
35、根据权利要求32所述的方法,其中条带和薄膜通过条带上的粘合剂接合。
36、根据权利要求32所述的方法,其中条带和薄膜通过叠层接合。
37、根据权利要求32所述的方法,其中金属部件被丝网印刷在一个一次性条带、薄膜上,包括玻璃薄膜或者其它类似载体。
38、根据权利要求32所述的方法,还包括将加强件和条带接合的步骤;以及在移除条带前去除加强件的步骤。
39、根据权利要求32所述的方法,其中金属部分厚度大约1-4密耳。
40、根据权利要求32所述的方法,其中金属部分厚度约小于1密耳。
41、根据权利要求32所述的方法,其中条带由塑料材料构成。
42、根据权利要求41所述的方法,其中条带由聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4构成。
43、根据权利要求32所述的方法,其中区域图案中的金属部件包括一个印模焊盘,用于支撑一个集成电路芯片;和引线连接点,用于电连接引线框和芯片。
44、根据权利要求43所述的方法,其中引线框为引线接合芯片提供支持和连接。
45、根据权利要求32所述的方法,其中区域图案中的金属部分包括引线连接点,用于支撑一个集成电路芯片,和电连接引线框和芯片。
46、根据权利要求45所述的方法,其中引线框为倒装晶片或者一个焊盘栅格阵列芯片提供支持和连接。
47、一种形成一个电子包装的方法,包括以下步骤:
提供一种金属薄膜;
将一个条带和该薄膜接合;并且
对该薄膜进行构图,在条带上留下一个金属引线框,该引线框包括多个排列成区域图案的金属部件,图案中的每个金属部件和其它金属部件电隔离;
将集成电路芯片和引线框的金属部件接合和电连接;
将条带上的引线框封装;
去除条带;并且
不分割任何金属部件将封装单元化,从而形成一个电子包装。
48、根据权利要求47所述的方法,还包括使用一种可接合引线以及可软焊成份对薄膜的上或下表面或者两面进行预镀的步骤。
49、根据权利要求48所述的方法,其中成份是镍—钯—金底板镀层。
50、根据权利要求47所述的方法,其中条带和薄膜通过条带上的粘合剂接合。
51、根据权利要求47所述的方法,其中条带和薄膜通过叠层接合。
52、根据权利要求47所述的方法,其中金属部件被丝网印刷在一个一次性条带、薄膜上,包括玻璃薄膜或者其它类似载体。
53、根据权利要求47所述的方法,还包括将加强件和条带接合的步骤;以及在移除条带前去除加强件的步骤。
54、根据权利要求47所述的方法,其中金属部分厚度大约1-4密耳。
55、根据权利要求47所述的方法,其中金属部分厚度约小于1密耳。
56、根据权利要求47所述的方法,其中条带由塑料材料构成。
57、根据权利要求53所述的方法,其中条带由聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4构成。
58、根据权利要求47所述的方法,其中区域图案中的金属部件包括一个印模焊盘,用于支撑一个集成电路芯片;和引线连接点,用于电连接引线框和芯片。
59、根据权利要求58所述的方法,其中该集成电路芯片通过环氧树脂、焊料或者其他低熔点金属和印模焊盘接合。
60、根据权利要求55所述的方法,其中引线框为引线接合芯片提供支持和连接。
61、根据权利要求47所述的方法,其中区域图案中的金属部分包括引线连接点,用于支撑一个集成电路芯片,和电连接引线框和芯片。
62、根据权利要求57所述的方法,其中引线框为倒装晶片或者一个焊盘栅格阵列芯片提供支持和电连接。
63、根据权利要求47所述的方法,其中条带可以通过剥离、溶解或者条带背面构图从金属部件和封装中去除,使得引线框的区域图案暴露出来。
64、根据权利要求47所述的方法,其中封装步骤包括用一种可控的方法在引线框上使用封装材料,环绕该金属部件并且一直到条带表面,而且没有生成任何模塑溢料。
65、根据权利要求47所述的方法,其中单元化步骤包括锯断、激光切割、喷水切割或者其结合来完成。
66、根据权利要求47所述的方法,还包括在分割封装前进行包装的剥离测试。
67、一种形成多个电子包装的方法,包括以下步骤:
提供一种金属薄膜;
将一个条带和该薄膜接合;并且
对该薄膜进行构图,在条带上留下多个独立金属引线框,每个引线框通过条带上的芯片间隔区域和邻近的引线框相分开,每个引线框包括排列成区域图案并相互电隔离的多个金属部件,并且没有金属部件延伸到芯片间隔区域;
将集成电路芯片和每个引线框的金属部件接合和电连接;
将条带上的引线框和芯片隔离区域封装;
去除条带;并且
在芯片隔离区域分割封装,从而形成独立的电子包装。
68、根据权利要求67所述的方法,还包括使用一种可接合引线以及可软焊成份对薄膜的上或下表面或者两面进行预镀的步骤。
69、根据权利要求64所述的方法,其中成份是镍—钯—金底板镀层。
70、根据权利要求67所述的方法,其中条带和薄膜通过条带上的粘合剂接合。
71、根据权利要求67所述的方法,其中条带和薄膜通过叠层接合。
72、根据权利要求67所述的方法,其中金属部件被丝网印刷在一个一次性条带、薄膜上,包括玻璃薄膜或者其它类似载体。
73、根据权利要求67所述的方法,还包括当条带与薄膜结合时,将加强件和条带接合的步骤;以及在移除条带前去除加强件的步骤。
74、根据权利要求67所述的方法,其中金属部分厚度大约1-4密耳。
75、根据权利要求67所述的方法,其中金属部分厚度约小于1密耳。
76、根据权利要求67所述的方法,其中条带由聚酰亚胺、聚脂薄膜、聚酰亚胺薄膜、或者Fr-4构成。
77、根据权利要求67所述的方法,其中在每一个区域图案中的金属部件包括一个印模焊盘,用于支撑一个集成电路芯片;和引线连接点,用于电连接引线框和芯片。
78、根据权利要求75所述的方法,其中引线框为引线接合芯片提供支持和连接。
79、根据权利要求67所述的方法,其中在每个区域图案中的金属部分包括引线连接点,用于支撑一个集成电路芯片和电连接引线框和芯片。
80、根据权利要求79所述的方法,其中该集成电路芯片通过环氧树脂、焊料或者其他低熔点金属和印模焊盘接合。
81、根据权利要求79所述的方法,其中引线框为倒装晶片或者焊盘栅格阵列芯片提供支持和电连接。
82、根据权利要求67所述的方法,其中多个引线框在条带上形成一个阵列。
83、根据权利要求67所述的方法,其中条带可以通过剥离、溶解或者条带背面构图金属部件和封装中去除,使得引线框的区域图案暴露出来。
84、根据权利要求67所述的方法,其中封装步骤包括用一种可控的方法在引线框上和间隔区域使用封装材料,环绕该金属部件并且一直到条带表面,而且没有生成任何模塑溢料。
85、根据权利要求67所述的方法,其中单元化步骤包括锯断、激光切割、喷水切割或者其结合来完成。
86、根据权利要求67所述的方法,还包括在分割封装前进行包装的剥离测试。
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-
2002
- 2002-09-25 US US10/256,288 patent/US20040058478A1/en not_active Abandoned
-
2003
- 2003-09-22 WO PCT/IB2003/004632 patent/WO2004030030A2/en active Application Filing
- 2003-09-22 KR KR1020057005241A patent/KR20050084598A/ko not_active Application Discontinuation
- 2003-09-22 EP EP03748499A patent/EP1543556A2/en not_active Ceased
- 2003-09-22 CN CNA038228351A patent/CN1777988A/zh active Pending
- 2003-09-22 AU AU2003267803A patent/AU2003267803A1/en not_active Abandoned
- 2003-09-22 JP JP2004539371A patent/JP2006514779A/ja not_active Abandoned
- 2003-09-25 TW TW092126480A patent/TWI323931B/zh not_active IP Right Cessation
-
2005
- 2005-06-17 US US11/155,878 patent/US7439097B2/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101221941B (zh) * | 2007-01-09 | 2011-04-06 | 日月光半导体制造股份有限公司 | 基板及封装结构的制造方法 |
CN104821306A (zh) * | 2015-04-28 | 2015-08-05 | 上海凯虹科技电子有限公司 | 超小型封装方法及封装体 |
CN105329850A (zh) * | 2015-10-21 | 2016-02-17 | 美新半导体(无锡)有限公司 | 圆片级芯片尺寸封装的测试方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20050084598A (ko) | 2005-08-26 |
AU2003267803A8 (en) | 2004-04-19 |
EP1543556A2 (en) | 2005-06-22 |
TW200416969A (en) | 2004-09-01 |
US7439097B2 (en) | 2008-10-21 |
TWI323931B (en) | 2010-04-21 |
JP2006514779A (ja) | 2006-05-11 |
US20040058478A1 (en) | 2004-03-25 |
US20060001130A1 (en) | 2006-01-05 |
AU2003267803A1 (en) | 2004-04-19 |
WO2004030030A3 (en) | 2004-06-03 |
WO2004030030A2 (en) | 2004-04-08 |
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