CN1525330A

CN1525330A - Method for testing storage unit having universal serial bus interface and storage unit

Info

Publication number: CN1525330A
Application number: CNA031067050A
Authority: CN
Inventors: 邱延诚; 叶奇典; 邱文彬
Original assignee: Elan Microelectronics Corp
Current assignee: Elan Microelectronics Corp
Priority date: 2003-02-27
Filing date: 2003-02-27
Publication date: 2004-09-01
Anticipated expiration: 2023-02-27
Also published as: CN1321374C

Abstract

The invention is a method of testing USB interface storage device, where the storage device at least contains USB interface, a USB controller linked with the USB interface, at least a semiconductor memory linked with the USB controller and the method includes the steps: USB controller receives test command transmitted by host machine through the USB interface; after the USB controller has received the test command, the USB controller makes write and read operations on the semiconductor memory and compare if the write and read data are the same, thus testing if the semiconductor memory is good or not; after the write and read test, the USB controller transmits the data of test result to the host machine through the USB interface.

Description

Test has the method and the memory storage of the memory storage of USB (universal serial bus)

Technical field

The present invention relates to test the method for testing and the memory storage thereof of memory storage with semiconductor memory, be particularly related to the method for testing that a kind of test has the memory storage of USB (universal serial bus) (USB-Universal Serial Bus) interface, and a kind of memory storage with self-test USB (universal serial bus).

Background technology

Known memory storage with body short-access storage, it for example is the memory storage of thumb, its test mode is to send test data (test pattern) by main frame, via usb bus read-write short-access storage, test data is write short-access storage, read short-access storage then, contrast test data and reading of data on main frame, it is quite long, especially more consuming time to the test of the big memory storage of memory capacity that such known way is finished the required time of test.

Summary of the invention

The purpose of this invention is to provide the method for testing that a kind of test has the memory storage of USB (universal serial bus) (USB) interface, make it possible to finish fast test memory storage.

Another object of the present invention provides a kind of memory storage with self-test USB (universal serial bus) (USB) interface, and it can finish test automatically fast after receiving test command.

For realizing purpose of the present invention, the invention provides the method for testing that a kind of test has the memory storage of USB (universal serial bus) (USB) interface, it is applied to memory storage, wherein memory storage includes the USB controller of USB interface, a connection USB interface, the semiconductor memory of at least one connection USB controller at least, and this method of testing comprises the following steps: that the USB controller receives the test command that is transmitted by main frame via USB interface; After the USB controller received test command, the USB controller write and reads semiconductor memory, and whether two piece of data that contrast writes and reads are identical, so that the measuring semiconductor storer is bad; After the USB controller was finished readwrite tests to semiconductor memory, the USB controller transmitted test result data via USB interface to main frame.

In addition,, the invention provides a kind of memory storage, comprising: USB interface with self-test USB (universal serial bus) (USB) interface for realizing another object of the present invention; A USB controller that connects USB interface; At least one connects the semiconductor memory of USB controller; Program code is used to offer the USB controller and carries out, so that carry out: receive the test command that is transmitted via USB interface by main frame; Semiconductor memory is write and reads, and whether two piece of data that contrast writes and reads are identical, so that the measuring semiconductor storer is bad; Behind the readwrite tests of finishing semiconductor memory, transmit test result data via USB interface.

For making those skilled in the art understand purpose of the present invention, feature and effect, hereinafter will be by following specific embodiment, and in conjunction with the accompanying drawings, describe the present invention in detail.

Description of drawings

Fig. 1 shows the structural drawing of the memory storage of implementing according to the principle of the invention.

Fig. 2 shows the process flow diagram of method of testing of the present invention.

Fig. 3 A and Fig. 3 B show the spirit according to Fig. 2, the process flow diagram of the concrete program code of implementing in memory storage.

Fig. 4 shows the structural drawing of first connected mode of a plurality of memory storages of host test.

Fig. 5 shows the structural drawing of second connected mode of a plurality of memory storages of host test.

Fig. 6 shows the efficient comparison diagram of the present invention and known test mode.

Drawing reference numeral

10 memory storages

101 USB controllers

103 USB interface

105 semiconductor memories

107 program codes

12 main frames

14 usb hubs

16 switches

Embodiment

Fig. 1 shows the structural drawing of the memory storage of implementing according to the principle of the invention.Memory storage 10 comprises: usb 1 03 is used to connect main frame 12, or connects main frame 12 via usb hub 14 again; At least one connects the semiconductor memory 105 of USB controller 101, as data storage, and the memory capacity of semiconductor memory 105 and unrestricted, for example can be configured to 32MB, 64MB, 128MB... or the like according to the actual requirements, specific embodiment of semiconductor memory 105 can be a short-access storage; Program code 107 and USB controller, wherein program code 107 is used to offer USB controller 101 with the shown flow process of execution graph 2, in view of the above, program code 107 is embodiments of the shown flow process of Fig. 2, and program code 107 can be implemented on memory storage 10 with firmware (firmware) form.Main frame 12 can be personal computer or the instrument that is used for test memory device 10.

Fig. 2 shows the process flow diagram of method of testing of the present invention.The method of testing of Fig. 2 is applied to memory storage shown in Figure 1 10, and step (20) is that USB controller 101 receives the test command that is transmitted by main frame 12 via usb 1 03.Step (22) is after USB controller 101 receives test command, and 101 pairs of semiconductor memories 105 of USB controller write and read, and whether two piece of data that contrast writes and reads are identical, are bad with measuring semiconductor storer 105.Step (26) is after USB controller 101 is finished the readwrite tests of semiconductor memory 105, and USB controller 101 transmits test result data via usb 1 03 to main frame 12.

Fig. 3 A and Fig. 3 B show the spirit according to Fig. 2, the process flow diagram of the concrete program code of implementing in memory storage, and main frame 12 can be followed scsi command (command) form as the specific implementation means with memory storage 10 test mode and test command to each other.Step (30) is that memory storage 10 receives the order that main frame 12 transmits.Step (32) is to judge the type of order, the next procedure under entering respectively according to command type.Step (34) is to handle test command (test command), it provides semiconductor memory 105 is bad test transmission, and can being main frame 12, the concrete means of test command send out test command, USB controller 101 is after receiving test command, respectively semiconductor memory 105 is set different voltage conditions, for example be 3.0V low-voltage, 3.3V normal voltage, 3.6V high voltage etc., under each voltage conditions, finish the test of test command.That chip that will test for main frame 12 specified semiconductor memories 105 then, each address of the 0th piece of this chip (block) is write " AA ", read the content of this piece subsequently, judge whether to be " AA ", the address that record makes a mistake, and wipe (erase) this piece, again this piece is write each address with " 55 ", read the content of this piece, judge whether to be " 55 ", and write down the address of making a mistake, and repeat above-mentioned action up to last piece of this chip, pass test result data back main frame at last.

Step (36) is that (control transfer) order is shifted in processing controls, its mainly with the unit describe symbol (device descriptor) of memory storage 10, descriptor (configuration descriptor), character string descriptor (string descriptor) etc. be set be transferred to main frame 12.

Step (38) is to judge that the scsi command type is to enter treatment S CSI process of commands step.Step (40) is to handle reading order (read command), it provides the data content of read semiconductor storer 105, and the concrete means of reading order can be USB controller 101 check whether LUT (look-up-table (look-up table)) have set up, if then do not set up LUT earlier, then read LUT (this is physical block address (physical block address)), again 5 LSB bits (bit) of LBA (logical blockaddress (LBA (Logical Block Addressing))) are added to the LSB of physical block address, to form the initial address of reading of semiconductor memory 105, begin the data of read semiconductor storer 105 subsequently.Step (42) is to handle write command (write command), it provides data content is write semiconductor memory 105, and the concrete means of write command can be USB controller 101 check earlier whether LBA have existed semiconductor memory 105, if then do not search empty physicalblock (setting of start address is then as reading order), start programization (program) semiconductor memory 105 subsequently, if LBA has existed in the semiconductor memory 105, step is same as described above, but need data copy (duplicating) with old LBA to new LBA to reach the purpose of covering.Step (44) is treatment state transmission command (status transport command), and it provides the transmission of the result phase after write command, reading order are handled, the transmission of other state of storage arrangement 10.

The present invention further discloses the enforcement means of above-mentioned test command, it is main with following the scsi command form, and Command Block Wrapper (CBW (command block packing)) and CommandStatus Wrapper (CSW (coomand mode packing)) are therefore arranged.When main frame 12 sends the CBW of test command, the CBW decoding that USB controller 101 is sent main frame 12, find that the order that this CBW has is notice USB controller 101 measuring semiconductor storeies 105, in view of the above, 101 pairs of semiconductor memories 105 of USB controller write and read contrast test data (Test Pattern) " AA " and " 55 ", when test finishes, USB controller 101 is to main frame 12 test transmission result datas, for example be that piece of chip of test crash, test result data is transferred to main frame 12.Then, USB controller 101 returns to form CSW to main frame 12, with the situation of confirming that test command is carried out.

The form of above-mentioned CBW is " 55 53 42 43 74 07 F8 DB, 00 00 04 00 01 00 03 F000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ".Wherein the 0th to the 3rd byte (byte) " 55 53 42 43 " be bCBWSignature, represent this to be packaged as CBW.Wherein the 4th to the 7th byte " 74 07 F8 DB " is dCBWTag, and USB controller 101 needs the identical dCBWTag of recovery in CSW.Wherein the 8th to the 11 bit line " 00 00 00 00 " is dCBWDataTransferLength, for main frame 12 expection by Data-In (input data), the byte number that is read, its length is fixing, because of the size of semiconductor memory 105 different.For example the size of semiconductor memory 105 is that 128M Bytes promptly has 8192 blocks (piece), and we represent a block with a bit, and (0 to represent this block be good (good); 1 to represent this block be bad (bad)), need to recover 1024bytes (8192 bits) altogether and give main frame 12.In like manner, 105 of the semiconductor memories of 64M Bytes need to recover 512bytes and give main frame 12.Wherein the 12 byte " 01 " representative data is delivered to main frame 12 by memory storage 10.Wherein the 13 byte " 00 " represented LUN (Logic Unit Number (logical unit number)).Wherein the 14 byte " 03 " represented the effective length of CBWCB, and it is effective that its expression has 3 bytes.Wherein the 15 byte " F0 " is the 0th byte of CBWCB, and representing this is a test command.Wherein the 16 byte " 00 " is the 1st byte of CBWCB, represents main frame 12 to require the 0th chips of USB controller 101 measuring semiconductor storeies 105.Wherein the 17 byte " 00 " is the 2nd byte of CBWCB, represents main frame 12 to require USB controller 101 to set the voltage conditions of test, " 00 " expression normal voltage, " 01 " expression high voltage, " 10 " expression low-voltage.Wherein the 18 to the 30 byte all is made as " 00 ".Above-mentioned Data-In partly is the data that USB controller 101 recovers to give main frame 12, as the 8th as described in the 11 byte.

The form of above-mentioned CSW is " 55 53 42 53 74 07 F8 DB 00 00 00 00 00 ".Wherein the 0th to the 3rd byte " 55 53 42 53 " be dCSWSignature, representing this is CSW.Wherein the 4th to the 7th byte " 74 07 F8 DB " is dCSWTag, and this value need be identical with dCBWTag.Wherein the 8th to the 11 byte " 00 00 00 00 " be dCSWDataResidue, on behalf of USB controller 101, it recover to give the byte number of main frame 12 and the difference of byte number that main frame 12 is expected.Wherein the 12 byte " 00 " represented executed commands.

The connected mode of the test memory device 10 of Fig. 4 and Fig. 5 can realize the purpose of substantive test memory storage 10.Fig. 4 shows the structural drawing of first connected mode of a plurality of memory storages of host test.Main frame 12 connects a memory storage 10 to be tested via each port (port) of usb hub 14, and main frame 12 connects usb hub 14.The tester is test memory device 10 in regular turn, when making a mistake as if memory storage 10, learns that memory storage 10 has problem, behind to be tested the finishing, plugs another memory storage 10 to be measured more at once.In addition, also all memory storages to be tested 10 can be inserted on the usb hub 14, judge the memory storage 10 that makes a mistake by main frame 12 executive softwares.

Fig. 5 shows the structural drawing of second connected mode of a plurality of memory storages of host test.The change-over switch of Fig. 5 is used to replace the usb hub of Fig. 4, when the some memory storage 10 of test, then is communicated with corresponding switch 16, and all the other then open circuit.Signal D+ and the signal D-of Fig. 5 are expressed as usb signal.

Fig. 6 shows the efficient comparison diagram of the present invention and known test mode.Find out obviously that from Fig. 6 efficient of the present invention is better than the test mode of known technology, when especially the capacity of semiconductor memory 105 was big more, the efficient of institute of the present invention tool was just remarkable more.

Though the present invention with preferred embodiment openly as above, yet it is not to be used to limit the present invention, any those skilled in the art, under the situation that does not break away from the spirit and scope of the present invention, can do various changes and polishing, all various changes of making and polishing are all within the scope of the appended claim of the present invention.

Claims

1. a test has the method for testing of the memory storage of USB (universal serial bus) (USB) interface, it is applied to memory storage, this memory storage includes USB controller that USB interface, one connect this USB interface at least, at least one connects the semiconductor memory of this USB controller, and this method of testing comprises the following steps:

This USB controller receives the test command that is transmitted by main frame via this USB interface;

After this USB controller received this test command, this USB controller write and reads this semiconductor memory, and whether identical, be bad to test this semiconductor memory if contrasting these two piece of data that write and read;

After this USB controller was finished readwrite tests to this semiconductor memory, this USB controller transmitted test result data via this USB interface to this main frame.

2. method of testing as claimed in claim 1, wherein this semiconductor memory is to be short-access storage.

3. memory storage with self-test USB (universal serial bus) (USB) interface comprises:

USB interface;

A USB controller that connects this USB interface;

At least one connects the semiconductor memory of this USB controller;

Program code is used to offer this USB controller and carries out, so that carry out:

The test command that reception is transmitted via this USB interface by main frame;

This semiconductor memory is write and reads, and whether identical, be bad to test this semiconductor memory if contrast these two piece of data that write and read;

Behind the readwrite tests of finishing this semiconductor memory, transmit test result data via this USB interface.

4. proving installation as claimed in claim 3, wherein this semiconductor memory is a short-access storage.