CN113193017B - Display panel and display device - Google Patents
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- CN113193017B CN113193017B CN202110427753.0A CN202110427753A CN113193017B CN 113193017 B CN113193017 B CN 113193017B CN 202110427753 A CN202110427753 A CN 202110427753A CN 113193017 B CN113193017 B CN 113193017B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
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Abstract
The present application relates to a display panel and a display device, the display panel including: a substrate having a binding region; test traces and binding electrodes located on the binding region; and the heightening structure is positioned between the binding electrode and the substrate and is used for increasing the height difference of the binding electrode relative to the test wiring, so that the problem of short circuit between the binding electrode of the display panel and the test wiring caused by alignment deviation of the binding electrode of the display panel and the binding electrode of the peripheral circuit can be avoided when the display panel is subsequently bound with the peripheral circuit, and the display screen abnormality of the display panel is avoided.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of technology and the improvement of product requirements, display devices with higher resolution become a popular development direction of the display industry, so that the binding process requirements on display panels are higher and higher.
At present, an integrated circuit chip (IC) is generally bound to a binding electrode of a binding area of a display panel through an anisotropic conductive film (ACF, anisotropic Conducti ve Film), however, since a test trace exists between the binding electrodes arranged at intervals on the binding area of the display panel, and the whole surface of the anisotropic conductive film covers the binding electrode and the test trace, once alignment deviation occurs in the binding process, the anisotropic conductive film between the binding electrodes is pressed, which causes a short circuit between the test trace and the binding electrode, and further causes abnormal display images (for example, a vertical line bad phenomenon exists).
Disclosure of Invention
An object of the present application is to provide a display panel and a display device, which can avoid the problem of short circuit between the binding electrode of the display panel and the test wiring in the binding process.
In order to solve the above-described problems, an embodiment of the present application provides a display panel including: a substrate having a binding region; test traces and binding electrodes located on the binding region; and the heightening structure is positioned between the binding electrode and the substrate and is used for increasing the height difference of the binding electrode relative to the test wire.
Wherein, the base plate includes the display area, is located the peripheral non-display area of display area, and the binding area is located non-display area, and display panel still includes: a source/drain layer on the display region; the test wiring and the source drain electrode layer are arranged on the same layer, the pad structure comprises a first pad layer, and the first pad layer and the source drain electrode layer are arranged on the same layer.
Wherein, the display panel still includes: an active layer and a first grid layer which are positioned between the substrate and the source drain layer and are sequentially far away from the substrate; the pad structure further comprises a second pad layer and a third pad layer which are stacked with the first pad layer in the direction perpendicular to the substrate, the second pad layer and the active layer are arranged on the same layer, and the third pad layer and the first grid layer are arranged on the same layer.
Wherein, the display panel still includes: a second gate layer located between the first gate layer and the source drain layer; the pad structure further comprises a fourth pad layer which is arranged in a lamination mode with the first pad layer in the direction perpendicular to the substrate, and the fourth pad layer and the second grid layer are arranged in the same layer.
Wherein, the display panel still includes: the first pixel electrode and the second pixel electrode are positioned on the source drain electrode layer and are sequentially far away from the substrate; the binding electrode and the second pixel electrode are arranged on the same layer, the pad structure further comprises a fifth pad layer which is arranged on the first pad layer in a lamination mode in the direction perpendicular to the substrate, and the fifth pad layer and the first pixel electrode are arranged on the same layer.
Wherein, the display panel still includes: the shielding layer and the buffer layer are positioned between the substrate and the active layer and are sequentially far away from the substrate, the shielding layer is positioned on the display area, and the buffer layer is positioned on the substrate and covers the shielding layer; the pad structure further comprises a sixth pad layer which is arranged in a lamination mode with the first pad layer in the direction perpendicular to the substrate, and the sixth pad layer and the shielding layer are arranged in the same layer.
Wherein, the display panel still includes: binding wires arranged on the same layer as the first cushion layer, and the binding wires are electrically connected with the binding electrodes through the first cushion layer.
Wherein, the display panel still includes: the passivation layer is arranged on the substrate, covers the test wiring, and the binding electrode is arranged on the passivation layer.
In order to solve the above-mentioned problem, the embodiment of the application provides a display device, including the display panel of any one of the above-mentioned aspects, a conductive adhesive layer, and a circuit board, the conductive adhesive layer covers the bonding electrode and the test trace of the display panel, the circuit board includes the bonding electrode for providing driving voltage to the display panel, and the bonding electrode of the circuit board is bonded and electrically connected with the bonding electrode of the display panel through the conductive adhesive layer.
The conductive adhesive layer comprises insulating glue, and a plurality of conductive particles are uniformly doped in the insulating glue.
The beneficial effects of this application are: in contrast to the prior art, the display panel and the display device that this application provided, including the base plate that has the binding area, be located test wiring and binding electrode on the binding area, and be located the bed hedgehopping structure between binding electrode and the base plate, bed hedgehopping structure is used for increasing the difference in height of binding electrode for test wiring, thereby when binding display panel and peripheral circuit follow-up, can avoid because display panel's binding electrode takes place counterpoint skew with peripheral circuit's binding electrode, and lead to display panel's binding electrode and test to walk the problem of short circuit between the line, display panel has been avoided appearing showing the picture unusual.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram showing the effect of binding a conventional display panel with a peripheral circuit;
FIG. 2 is a schematic diagram showing another effect of binding a conventional display panel with a peripheral circuit;
fig. 3 is a schematic cross-sectional structure of a display panel according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram showing the effect of binding the display panel of FIG. 3 with peripheral circuits;
fig. 5 is a schematic top view of a display panel according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of another cross-sectional structure of a display panel according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
[ detailed description ] of the invention
The present application is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustration of the present application, but do not limit the scope of the present application. Likewise, the following embodiments are only some, but not all, of the embodiments of the present application, and all other embodiments obtained by one of ordinary skill in the art without inventive effort are within the scope of the present application.
Currently, as shown in fig. 1, the bonding electrode 31 of the peripheral circuit 30 is aligned and bonded to the bonding electrode 11 of the display panel 10 by the anisotropic conductive film 20, so as to realize the electrical connection between the peripheral circuit 30 and the display panel 10, and further enable the peripheral circuit 30 to provide a driving voltage to the display panel 10. The anisotropic conductive film 20 mainly includes a colloid layer and conductive particles uniformly distributed in the colloid layer, the conductive particles are used for imparting conductive performance to the anisotropic conductive film 20, and the colloid layer is used for imparting adhesive performance and insulating performance to the anisotropic conductive film 20.
Specifically, in the process of aligning and binding the display panel 10 and the peripheral circuit 30, the anisotropic conductive film 20 may be interposed between the binding electrode 11 of the display panel 10 and the binding electrode 31 of the peripheral circuit 30, and the anisotropic conductive film 20 may be thermally pressed by a pressing device, so that the viscosity of the anisotropic conductive film 20 may be changed to bond the binding electrode 11 of the display panel 10 and the binding electrode of the peripheral circuit 30 together, and at the same time, since the conductive particles between the binding electrode 11 of the display panel 10 and the binding electrode 31 of the peripheral circuit 30 are pressed, an electrical connection may be formed between the display panel 10 and the peripheral circuit 30.
However, since the test traces 12 are disposed between the bonding electrodes 11 disposed at intervals on the bonding area of the display panel 10, and the anisotropic conductive film 20 covers the bonding electrodes 11 and the test traces 12 of the display panel 10, in the process of aligning and bonding the display panel 10 and the peripheral circuit 30, as shown in fig. 2, once the alignment shift occurs (i.e., the bonding electrodes 31 of the peripheral circuit 30 are not aligned with the bonding electrodes 11 of the display panel 10 in the thickness direction), the anisotropic conductive film 20 between the bonding electrodes 11 is pressed, which may cause the conductive particles between the bonding electrodes 11 and the test traces 12 of the display panel 10 to be pressed, thereby causing a short circuit between the test traces 12 and the bonding electrodes 11 of the display panel 10, and thus causing a problem of abnormal display screen (for example, having a vertical line defect).
In order to avoid the problem of short circuit between the bonding electrode of the display panel and the test trace due to the alignment deviation of the bonding electrode of the display panel and the bonding electrode of the peripheral circuit, the inventor of the application finds out in long-term research and development that by increasing the height difference between the bonding electrode of the display panel and the test trace, the pressure born by conductive particles between the bonding electrode of the display panel and the test trace when the alignment deviation occurs can be effectively reduced in the process of aligning and bonding the display panel and the peripheral circuit, so that the possibility of short circuit between the bonding electrode of the display panel and the test trace in the bonding process is greatly reduced, and the problem of abnormal display picture of the display panel is avoided.
Referring to fig. 3, fig. 3 is a schematic cross-sectional structure of a display panel according to an embodiment of the present application, and as shown in fig. 3, the display panel 40 includes a substrate 41 having a bonding region 41B, a bonding electrode 42 and a test trace 43 disposed on the bonding region 41B, and a raised structure 44 disposed between the bonding electrode 42 and the substrate 41. In the present embodiment, the pad structure 44 is used to increase the height difference of the bonding electrode 42 in the display panel 40 relative to the test trace 43, so that the height of the bonding electrode 42 in the display panel 40 relative to the substrate 41 is greater than the height of the test trace 43 relative to the substrate 41. Specifically, the pad structure 44 may include a plurality of pad layers (not shown) stacked in a direction perpendicular to the substrate 41.
Specifically, the number of the bonding electrodes 42 may be plural, and the plurality of bonding electrodes 42 may be disposed on the bonding region 41B of the substrate 41 at intervals. Accordingly, the number of the raised structures 44 may be plural, and a corresponding raised structure 44 is disposed between each of the bonding electrodes 42 and the substrate 41. Specifically, the test trace 43 may be located in an area between two adjacent bonding electrodes 42 on the substrate 41, and the test trace 43 may be disposed in the same layer as the bonding electrodes 42 or may not be disposed in the same layer as the bonding electrodes 42. In addition, when the test trace 43 and the bonding electrode 42 are disposed on the same layer, the height of the bonding electrode 42 relative to the substrate 41 in the display panel 40 is greater than the height of the test trace 43 relative to the substrate 41, which can be understood that the raised structure 44 under the layer where the test trace 43 and the bonding electrode 42 are disposed together and between the bonding electrode 42 and the substrate 41 raises the height of the bonding electrode 42 corresponding thereto, and since the raised structure 44 is only disposed between the bonding electrode 42 and the substrate 41, only the height of the bonding electrode 42 is raised, but not the height of the test trace 43.
It can be understood that, compared with the technical solution that the raised structure is not disposed between the substrate of the display panel 10 and the bonding electrode 11 in fig. 2, as shown in fig. 3 and 4, the raised structure 44 is disposed between the substrate 41 and the bonding electrode 42 in the display panel 40 in the embodiment, and the raised structure 44 increases the height difference between the bonding electrode 42 and the testing trace 43 in the display panel 40 relative to the substrate 41, so that even if the alignment offset occurs during the process of aligning and bonding the bonding electrode 31 of the peripheral circuit 30 and the bonding electrode 11 of the display panel 10 by using the anisotropic conductive film 20, the bonding electrode 31 of the peripheral circuit 30 is far away from the conductive particles located directly under the raised structure 44 and between the testing trace 43, so that the pressure received by the conductive particles located between the raised structure 44 and the testing trace 43 is limited, the deformation generated is limited, and thus the electrical connection between the bonding electrode 42 and the testing trace 43 of the display panel 40 is difficult, and the problem of abnormal display screen 40 and the abnormal display screen will not occur.
In addition, in the implementation, the height of the raised structure 44 and the number of the pad layers included in the raised structure 44 can be as large as possible without affecting other performances of the display panel 40, and each pad layer included in the raised structure 44 and other layer structures in the display panel 40 can be formed together by the same etching process, so that masks and processes are saved.
In one embodiment, as shown in fig. 5, the substrate 41 may further include a display area 41C, and a non-display area 41D located around the display area 41C, and the binding area 41B may be located in the non-display area 41D, for example, at an edge position of the substrate 41. In some embodiments, as shown in fig. 5, the plurality of binding electrodes 42 may also be distributed in a plurality of rows in a direction (horizontal direction in fig. 5) perpendicular to the boundary line between the display region 41C and the non-display region 41D and away from the display region 41C. Specifically, as shown in fig. 5, the display panel 40 may further include a bonding wire 45, one end of the bonding wire 45 is electrically connected to a signal line (not shown) located on the display area 41C, such as a data line or a scan line, and the other end is electrically connected to a corresponding bonding electrode 42. Moreover, among the two adjacent rows of bonding electrodes 42, the bonding trace 45 electrically connected to the bonding electrode 42 of the row of bonding electrodes 42 far from the display area 41C is located between the two adjacent bonding electrodes 42 of the row of bonding electrodes 42 near the display area 41C.
In some embodiments, as shown in fig. 6, the display panel 40 may further include a thin film transistor layer on the substrate 41, and a plurality of scan lines (not shown) extending in a first lateral direction and a plurality of data lines (not shown) extending in a second lateral direction, wherein the second lateral direction is perpendicular to the first lateral direction. The thin film transistor layer may include a first gate layer 461, an interlayer dielectric layer 462, a source/drain layer 463, and a planarization layer 464, which are sequentially provided on the substrate 41. The scan lines may be disposed in the same layer as the first gate layer 461, the data lines may be disposed in the same layer as the source/drain layer 463, and two adjacent gate lines and two adjacent data lines crossing the two adjacent gate lines may collectively define a sub-pixel (not shown) on the display region 41C.
In one embodiment, as shown in fig. 6, the source/drain layer 463 may be only located on the display region 41C, the test trace 43 may be disposed on the same layer as the source/drain layer 463, the pad structure 44 may include a first pad layer 441, and the first pad layer 441 may be disposed on the same layer as the source/drain layer 463. Accordingly, the bonding wire 45 and the first pad layer 441 may be disposed on the same layer, and the bonding wire 45 may be electrically connected to the corresponding bonding electrode 42 through the first pad layer 441. In addition, in the implementation, the source/drain layer 463, the test trace 43, the first pad layer 441 and the bonding trace 45 may be formed together in the same process, so as to save the process.
In some embodiments, as shown in fig. 6, the thin film transistor layer may further include an active layer 465 on the display region 41C, the active layer 465 being located between the substrate 41 and the first gate layer 461, and correspondingly, the thin film transistor layer may further include a gate insulating layer 466, the gate insulating layer 466 being located between the active layer 465 and the first gate layer 461 and covering the active layer 465. The pad structure 44 may further include a second pad layer 442 and a third pad layer 443 stacked with the first pad layer 441 in a direction perpendicular to the substrate 41, and the second pad layer 442 may be disposed in the same layer as the active layer 465, and the third pad layer 443 may be disposed in the same layer as the first gate layer 461. Wherein the active layer 465 may be a polysilicon layer (e.g., a low temperature polysilicon layer). In addition, in the embodiment, the second pad layer 442 and the active layer 465 may be formed in the same etching process, and the third pad layer 443 and the first gate layer 461 may be formed in the same etching process, so as to save masks and processes.
In some embodiments, as shown in fig. 6, the thin film transistor layer may further include a second gate layer (not shown) disposed on the display region 41C, and the second gate layer is disposed between the first gate layer 461 and the source drain layer 463. Accordingly, the raised structure 44 may further include a fourth pad layer (not shown) stacked with the first pad layer 441 in a direction perpendicular to the substrate 41, and the fourth pad layer may be disposed in the same layer as the second gate layer, and, in particular, the fourth pad layer and the second gate layer may be formed in the same etching process, so as to save masks and processes.
In some embodiments, the display panel 40 may further include a first pixel electrode 47 and a second pixel electrode (not shown) sequentially away from the substrate 41, where the first pixel electrode 47 and the second pixel electrode are located on the source drain layer 463 (or the flat layer 464). Accordingly, the bonding electrode 42 may be disposed on the same layer as the second pixel electrode, the pad structure 44 may further include a fifth pad layer 445 stacked on the first pad layer 441 in a direction perpendicular to the substrate 41, and the fifth pad layer 445 may be disposed on the same layer as the first pixel electrode 47, and, in particular, the bonding electrode 42 and the second pixel electrode may be formed in the same etching process, and the fifth pad layer 445 and the first pixel electrode 47 may be formed in the same etching process, so as to save masks and processes.
Specifically, the flat layer 464 may not cover the bonding region 41B of the substrate 41, and the fifth pad layer 445 corresponding to the first pixel electrode 47 and disposed on the same layer may directly contact the first pad layer 441 of the source/drain layer 463. The materials of the first pad layer 441 and the fifth pad layer 445 are conductive materials, and specifically, the material of the first pad layer 441 may be the same as the material of the source/drain layer 463, and the material of the fifth pad layer 445 may be the same as the material of the first pixel electrode 47.
In some embodiments, when the display panel 40 is an organic light emitting display panel (OL ED), the corresponding display panel 40 may further include an organic light emitting layer (not shown) between the first pixel electrode 47 and the second pixel electrode.
In the above embodiment, as shown in fig. 6, the display panel 40 may further include a shielding layer 48 and a buffer layer 49 sequentially distant from the substrate 41, the shielding layer 48 and the buffer layer 49 being located between the substrate 41 and the active layer 465, and the shielding layer 48 being located on the display region 41C, the buffer layer 49 being located on the substrate 41 and covering the shielding layer 48. Accordingly, the pad structure 44 may further include a sixth pad layer 446 stacked with the first pad layer 441 in a direction perpendicular to the substrate 41, and the sixth pad layer 446 may be disposed in the same layer as the shielding layer 48, wherein the sixth pad layer 446 and the shielding layer 48 may be formed in the same etching process to save masks and processes.
Specifically, the shielding layer 48 is used to absorb light and prevent outdoor light from being incident on the active layer 465, and the shielding layer 48 may be made of a metal material such as molybdenum or a black organic material. In particular, in the display panel 40, the above-described active layer 465 is formed to overlap the shielding layer 48, and thus outdoor light is prevented from being incident on the active layer 465. Also, the shielding layer 48 may have a width larger than that of the active layer 465 so as to completely block the outdoor light from being incident on the active layer 465.
The active layer 465 may include a source region electrically connected to a source electrode in the source/drain layer, a drain region electrically connected to a drain electrode in the source/drain layer, and a channel region overlapping the first gate layer 461.
In the above embodiment, as shown in fig. 6, the display panel 40 may further include a passivation layer 50 disposed on the substrate 41, the passivation layer 50 covers the test trace 43, and the bonding electrode 42 is disposed on the passivation layer 50, so that in the process of bonding the display panel 40 and the peripheral circuit in alignment, even if alignment deviation occurs, and the conductive particles between the bonding electrode 42 and the test trace 43 are pressed, as long as the passivation layer 50 between the bonding electrode 42 and the test trace 43 is not crushed and broken, the problem of short circuit between the bonding electrode 42 and the test trace 43 will not be generated, which is beneficial to improving the stability and yield of the display panel.
Specifically, the passivation layer 50 may cover the bonding region 41B (or the non-display region 41D) of the substrate 41 entirely, and the passivation layer 50 is made of an insulating material. And, a via hole may be provided on the passivation layer 50 so that the bonding electrode 42 on the passivation layer 50 can be electrically connected with the bonding wire 45 under the passivation layer 50 through the via hole. In a specific implementation, the via hole on the passivation layer 50 may electrically connect the bonding electrode 42 on the passivation layer 50 to the first pad layer 441 in the corresponding pad structure 44, and since the first pad layer 441 is electrically connected to the bonding trace 45, the bonding electrode 42 can be electrically connected to the bonding trace 45. In some embodiments, the first pad layer 441 may be electrically connected to the third pad layer 443 disposed on the same layer as the first gate layer 461 through a via penetrating the interlayer dielectric layer 462, so as to reduce the connection resistance between the bonding electrode 42 and the bonding wire 45. The third pad layer 443 may be made of a conductive material, and may be made of the same material as the first gate layer 461.
In the above embodiment, the substrate 41 may be made of glass or hard resin, or may be made of one of organic polymers such as polyimide, polycarbonate, polyethylene terephthalate, and polyethersulfone. The peripheral circuit 30 may be a flexible circuit board, a flip-chip, an integrated circuit chip, or a touch chip.
In the above embodiment, the buffer layer 49, the gate insulating layer 466, and the interlayer dielectric layer 462 may be formed entirely on the substrate 41 by a deposition process, and the shielding layer 48, the active layer 465, the first gate layer 461, the second gate layer, the source drain layer 463, and the first pixel electrode 47 may be patterned films and may be located only on the display region 41C of the substrate 41. It is to be understood that the buffer layer 49, the gate insulating layer 466, and the interlayer dielectric layer 462 may have a partially raised height by covering at least one of the shielding layer 48, the active layer 465, the first gate layer 461, the second gate layer, the source drain layer 463, and the first pixel electrode 47, but the partially raised height of these layers is not shown in fig. 6 for convenience of description.
Compared with the prior art, the display panel in the embodiment has the advantages that the heightening structure is arranged between the binding electrode and the substrate, so that the height difference of the binding electrode on the substrate relative to the test wiring is increased, and the problem of short circuit between the binding electrode of the display panel and the test wiring caused by alignment deviation of the binding electrode of the display panel and the binding electrode of the peripheral circuit can be avoided when the display panel is subsequently bound with the peripheral circuit, and the display panel is prevented from abnormal display picture.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a display device according to an embodiment of the disclosure. The display device 70 may include the display panel 71 of any of the above embodiments, the conductive adhesive layer 72, and the circuit board 73, the conductive adhesive layer 72 covers the bonding electrodes and the test traces of the display panel 71, the circuit board 73 includes bonding electrodes 731 for providing driving voltages to the display panel 71, and the bonding electrodes 731 of the circuit board 73 are bonded and electrically connected to the bonding electrodes of the display panel 71 through the conductive adhesive layer 72.
Specifically, the display panel 71 may include a substrate having a bonding region, bonding electrodes and test traces on the bonding region, and a raised structure between the bonding electrodes and the substrate. The pad structure is used for increasing the height difference of the binding electrode in the display panel 71 relative to the test wire, so that the height of the binding electrode in the display panel 71 relative to the substrate is greater than the height of the test wire relative to the substrate. Specifically, the above-described elevated structure may include a plurality of underlayments stacked in a direction perpendicular to the substrate of the display panel 71.
The circuit board 73 may be a flexible circuit board, a flip-chip film, an integrated circuit chip, a touch chip, or the like. The display panel 71 may be a liquid crystal display panel or an organic light emitting display panel. The conductive adhesive layer 72 may include an insulating paste, and a plurality of conductive particles may be uniformly doped in the insulating paste, wherein the insulating paste may be a thermosetting resin for imparting adhesive property and insulating property to the conductive adhesive layer 72, the conductive particles may include a resin core, a nickel layer coating the resin core, and a gold layer coating the nickel layer for imparting conductive property to the conductive adhesive layer 72, and the particle size of the conductive particles may be 3-5 μm.
Specifically, as shown in fig. 7, in the process of aligning and bonding the display panel 71 and the circuit board 73, the display panel 71 and the circuit board 73 may have a plurality of bonding electrodes corresponding to each other, the conductive bonding layer 72 is interposed between the display panel 71 and the circuit board 73, and then the conductive bonding layer 72 is thermally pressed by a pressing device so that the conductive bonding layer 72 reacts, specifically, the viscosity of the conductive bonding layer 72 can be changed by heating, and the conductive bonding layer 72 between the display panel 71 and the circuit board 73 can be pressed by pressing so that the conductive particles in the conductive bonding layer 72 are deformed, thereby increasing the contact area of the conductive particles, and an electrical connection is formed between the bonding electrode of the display panel 71 and the bonding electrode 731 of the circuit board 73 by using the deformed conductive particles.
Compared with the prior art, the display device in the embodiment increases the height difference of the binding electrode on the substrate in the display panel relative to the test wiring by arranging the heightening structure between the binding electrode of the display panel and the substrate, so that the problem of short circuit between the binding electrode of the display panel and the test wiring due to alignment deviation of the binding electrode of the display panel and the binding electrode of the peripheral circuit can be avoided when the display panel is bound with the peripheral circuit, and abnormal display picture of the display panel is avoided.
The foregoing description of the preferred embodiments of the present application is not intended to be limiting, but is intended to cover any and all modifications, equivalents, and alternatives falling within the spirit and principles of the present application.
Claims (7)
1. A display panel, comprising:
a substrate having a binding region;
the test wiring and the binding electrode are positioned on the binding area; the method comprises the steps of,
the heightening structure is positioned between the binding electrode and the substrate and is used for increasing the height difference of the binding electrode relative to the test wire;
the substrate comprises a display area and a non-display area positioned at the periphery of the display area, the binding area is positioned in the non-display area, and the display panel further comprises:
the source-drain electrode layer is positioned on the display area;
the active layer and the first grid layer are positioned between the substrate and the source-drain electrode layer and are sequentially far away from the substrate;
the flat layer and the passivation layer are arranged on one side of the source drain electrode layer far away from the substrate, the flat layer and the passivation layer are arranged on the same layer, the flat layer is positioned in a display area, and the passivation layer is positioned in a non-display area;
a first pixel electrode and a second pixel electrode located at one side of the planarization layer and the passivation layer away from the substrate;
the test wiring and the source drain electrode layer are arranged in the same layer, the pad structure comprises a first pad layer, a third pad layer and a fifth pad layer, the third pad layer and the first pad layer are arranged in a stacked mode in the direction perpendicular to the substrate, the first pad layer and the source drain electrode layer are arranged in the same layer, the third pad layer and the first grid electrode layer are arranged in the same layer, the fifth pad layer and the first pixel electrode are arranged in the same layer, and the binding electrode and the second pixel electrode are arranged in the same layer; and the first cushion layer is connected with the third cushion layer through corresponding through holes, the first cushion layer is connected with the fifth cushion layer in a direct contact manner, and the binding electrode is connected with the fifth cushion layer through the through holes on the passivation layer.
2. The display panel of claim 1, further comprising:
a second gate layer located between the first gate layer and the source drain layer;
the elevating structure further comprises a fourth cushion layer which is arranged in a lamination mode with the first cushion layer in the direction perpendicular to the substrate, and the fourth cushion layer and the second grid layer are arranged in the same layer.
3. The display panel of claim 1, further comprising:
the first pixel electrode and the second pixel electrode are positioned on the source-drain electrode layer and sequentially far away from the substrate;
the binding electrode and the second pixel electrode are arranged on the same layer, the pad structure further comprises a fifth pad layer which is arranged on the first pad layer in a lamination mode in the direction perpendicular to the substrate, and the fifth pad layer and the first pixel electrode are arranged on the same layer.
4. The display panel of claim 1, further comprising:
binding wires arranged on the same layer as the first cushion layer, and the binding wires are electrically connected with the binding electrodes through the first cushion layer.
5. The display panel of claim 1, further comprising:
and the passivation layer is positioned on the substrate, covers the test wiring, and the binding electrode is arranged on the passivation layer.
6. A display device comprising the display panel of any one of claims 1-5, a conductive adhesive layer covering the bonding electrodes and the test traces of the display panel, and a circuit board for providing a driving voltage to the display panel, the circuit board being electrically connected to the bonding electrodes of the display panel through the conductive adhesive layer.
7. The display device according to claim 6, wherein the conductive adhesive layer includes an insulating paste in which a plurality of conductive particles are uniformly doped.
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| CN202110427753.0A CN113193017B (en) | 2021-04-21 | 2021-04-21 | Display panel and display device |
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| CN114185210A (en) * | 2021-12-03 | 2022-03-15 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN115240567B (en) * | 2022-06-21 | 2023-11-14 | 京东方科技集团股份有限公司 | Display panel and display device |
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| CN107784952A (en) * | 2017-11-17 | 2018-03-09 | 京东方科技集团股份有限公司 | A kind of display panel and preparation method thereof, display device |
| CN111933066A (en) * | 2020-08-28 | 2020-11-13 | 京东方科技集团股份有限公司 | OLED display substrate, display module and display panel |
| CN112002715B (en) * | 2020-09-15 | 2023-03-31 | 武汉华星光电技术有限公司 | Array substrate and display panel |
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| CN107683020A (en) * | 2017-10-17 | 2018-02-09 | 京东方科技集团股份有限公司 | A kind of display panel, its detection method, flexible PCB and display device |
| CN109521584A (en) * | 2018-11-16 | 2019-03-26 | 合肥京东方显示技术有限公司 | A kind of display master blank, array substrate and preparation method thereof and display panel |
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