CN113032791B - IP core, IP core management method and chip - Google Patents
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- 238000007726 management method Methods 0.000 title abstract description 12
- 238000012545 processing Methods 0.000 claims abstract description 105
- 238000000034 method Methods 0.000 claims description 26
- 238000012795 verification Methods 0.000 claims description 19
- 238000003860 storage Methods 0.000 claims description 5
- 230000006870 function Effects 0.000 description 23
- 238000013461 design Methods 0.000 description 8
- 238000013507 mapping Methods 0.000 description 8
- 239000011159 matrix material Substances 0.000 description 7
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/101—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM] by binding digital rights to specific entities
- G06F21/1015—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM] by binding digital rights to specific entities to users
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/107—License processing; Key processing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
- G06F21/12—Protecting executable software
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Abstract
The IP core, the IP core management method and the chip provided by the invention receive the secret key input from the outside; judging whether the secret key is correct or not, if so, processing the received data to be processed, and outputting a correct processing result; if the secret key is incorrect, the received data to be processed is processed, and an error processing result is output according to a preset probability. Therefore, the complete function of the IP core can be used only when the correct secret key is obtained, the IP core is prevented from being abused, and the intellectual property rights of products such as the IP core are protected.
Description
Technical Field
The invention relates to the field of chip design, in particular to an IP core, an IP core management method and a chip.
Background
At present, the design scale of the chip is more and more huge, and for the development of the chip, the chip company is difficult to independently complete all design works. Chip companies often reduce the complexity of design by purchasing third party hardware IP cores, focusing limited resources on the development of critical modules for integrated design cores. The form of the hardware IP core may be various, including software code (hardware description language), netlist or layout (GDS). For the hardware IP core, especially for the front-end digital IP, the method has the characteristic of strong applicability, namely, the method can be quickly adapted to other chip projects, which leads to the problem that the IP of a manufacturer of the hardware IP core is easy to be used for unauthorized chip products, and intellectual property rights are infringed.
Disclosure of Invention
The invention provides an IP core, a management method of the IP core and a chip, aiming at protecting the intellectual property of the IP core.
An embodiment provides a method for managing an IP core, including:
Receiving an externally input key;
Judging whether the secret key is correct, if so, processing the received data to be processed, and outputting a correct processing result; if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result with preset probability.
In the management method, the processing the received data to be processed and outputting the error processing result with a preset probability includes:
Judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an erroneous processing result; otherwise, processing the data to be processed, and outputting a correct processing result; the duty ratio of the special data in all possible data to be processed is the preset probability.
In the management method, the preset probability is not more than 1%.
In the management method, the determining whether the key is correct includes:
judging whether the key belongs to a preset key set, if so, determining that the key is correct, otherwise, determining that the key is incorrect; the key set includes a plurality of correct keys.
An embodiment provides an IP core comprising:
The key verification module is used for receiving an externally input key and judging whether the key is correct or not;
The data processing module is used for processing the received data to be processed when the secret key is correct and outputting a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result with preset probability.
In the IP core, the data processing module processes the received data to be processed, and outputs an error processing result with a preset probability, including:
Judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an erroneous processing result; otherwise, processing the data to be processed, and outputting a correct processing result; the duty ratio of the special data in all possible data to be processed is the preset probability.
In the IP core, the preset probability is not more than 1%.
In the IP core, the determining, by the key verification module, whether the key is correct includes:
judging whether the key belongs to a preset key set, if so, determining that the key is correct, otherwise, determining that the key is incorrect; the key set includes a plurality of correct keys.
An embodiment provides a chip, and a part of a circuit of the chip is manufactured according to the IP core.
An embodiment provides a computer-readable storage medium having stored thereon a program executable by a processor to implement a method as described above.
According to the IP core, the IP core management method and the IP core management chip of the embodiment, the secret key input from the outside is received; judging whether the secret key is correct or not, if so, processing the received data to be processed, and outputting a correct processing result; if the secret key is incorrect, the received data to be processed is processed, and an error processing result is output according to a preset probability. Therefore, the complete function of the IP core can be used only when the correct secret key is obtained, the IP core is prevented from being abused, and the intellectual property rights of products such as the IP core are protected.
Drawings
FIG. 1 is a block diagram illustrating an embodiment of an IP core according to the present invention;
FIG. 2 is a flowchart of an embodiment of a method for managing IP cores according to the present invention;
FIG. 3 is a flowchart of an embodiment of a method for managing IP cores according to the present invention;
fig. 4 is a block diagram of an IP core circuit in the chip provided by the present invention.
Detailed Description
The application will be described in further detail below with reference to the drawings by means of specific embodiments. Wherein like elements in different embodiments are numbered alike in association. In the following embodiments, numerous specific details are set forth in order to provide a better understanding of the present application. However, one skilled in the art will readily recognize that some of the features may be omitted, or replaced by other elements, materials, or methods in different situations. In some instances, related operations of the present application have not been shown or described in the specification in order to avoid obscuring the core portions of the present application, and may be unnecessary to persons skilled in the art from a detailed description of the related operations, which may be presented in the description and general knowledge of one skilled in the art.
Furthermore, the described features, operations, or characteristics of the description may be combined in any suitable manner in various embodiments. Also, various steps or acts in the method descriptions may be interchanged or modified in a manner apparent to those of ordinary skill in the art. Thus, the various orders in the description and drawings are for clarity of description of only certain embodiments, and are not meant to be required orders unless otherwise indicated.
The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The term "coupled" as used herein includes both direct and indirect coupling (coupling), unless otherwise indicated.
As shown in fig. 1, the IP core provided by the present invention includes a key verification module 10 and a data processing module 20. Wherein, the IP core is an intellectual property core or an intellectual property module. The IP cores are largely classified into soft IP (core), solid IP (core), and hard IP (core). The soft IP may be, for example, a functional block (software code) described in a hardware description language. The hard IP may be, for example, a layout (GDS) from which a mask for producing a chip may be made. The solid IP is an intermediate form of soft IP and hard IP, such as a netlist.
The key verification module 10 is configured to receive an externally input key, and determine whether the key is correct; the judgment result is output to the data processing module 20. For soft IP cores, the key verification module 10 may be a functional module. For a hard IP core, the key verification module 10 may be a digital logic circuit. For a solid IP core, key verification module 10 may be a netlist that reflects the digital logic circuit.
The data processing module 20 is used for processing the received data to be processed when the secret key is correct, and outputting a correct processing result; when the secret key is incorrect, the received data to be processed is processed, and an error processing result is output according to the preset probability. Therefore, the complete function of the IP core can be used only when the correct secret key is obtained, so that the IP core is prevented from being abused, and the intellectual property rights of products such as the IP core are protected. In addition, the invention can output correct processing results with a certain probability when the key is wrong, so that if other people want to crack the key, correct data processing results can still be obtained after the crack fails, the key is easy to misunderstand to be cracked, and finally, the abuse of the IP core is avoided. Even if others know that the processing result output by the IP core has a certain probability of error when the secret key is incorrect, when others want to crack the secret key, whether the secret key is cracked or not, the others need to repeatedly verify the accuracy of the data processing result, the cracking cost is high, the situation that the IP core is abused is effectively reduced, and the intellectual property of the IP core is protected. Likewise, for soft IP cores, the data processing module 20 may be a functional module. For a hard IP core, data processing module 20 may be a type of digital logic circuit. For a solid IP core, data processing module 20 may be a netlist that reflects the digital logic circuit.
As shown in fig. 2, the process of data processing by the IP core includes the following steps:
Step 1, the key verification module 10 receives an externally input key and data to be processed, which may be sequentially input to the IP core or may be input to the IP core together.
Step 2, the key verification module 10 judges whether the received key is correct, if so, the step 4 is entered; if the key is incorrect, go to step 3. Specifically, the key verification module 10 may determine whether the key belongs to a preset key set, if so, determine that the key is correct, otherwise, determine that the key is incorrect. The key set is a set of a plurality of correct keys. In other words, for the same IP core, a plurality of correct keys can be provided, and an IP manufacturer only needs to provide different keys for different chip manufacturers, so that the reusability of an IP core circuit is ensured, and after the hardware IP core is delivered, the source and evidence collection can be performed by providing different key values for different chip manufacturers.
And 3, the data processing module 20 processes the received data to be processed, and outputs an error processing result according to a preset probability. In some embodiments, the predetermined probability is not more than 1%, preferably not more than 0.3%, not more than 0.1%, or between 0.1% and 0.3%, etc. The chips on the market generally need to be designed and verified in advance and then mass-produced to form the final product. The chip manufacturer typically evaluates the IP core of at least one IP manufacturer during the chip design phase. If the IP core is simply encrypted by adopting the secret key, the IP manufacturer needs to provide the IP core using different secret keys for each chip manufacturer for the same IP core, and the maintenance and management cost of the IP core is high. In addition, although the chip is designed and even verified, the chip is not necessarily produced in mass production for various reasons, which easily leads to misuse (embezzlement) of keys provided by IP manufacturers in the earlier stage, is unfavorable for protecting the IP cores and brings loss to hardware IP core manufacturers. Currently, a hardware IP core manufacturer often determines whether there is an abused situation by embedding a serial number in an IP product. However, since tampering with the serial number does not affect the function of the IP core, the method cannot fundamentally solve the abused situation, but is a evidence obtaining and proving method. The IP core provided by the invention can correctly process more than 99% of data even if the key is wrong, so that the IP manufacturer does not need to provide the key when designing and verifying the chip, the security of the key is improved, the public version of the IP core can be issued for a plurality of chip manufacturers to evaluate, and the maintenance cost of the IP core is reduced; in addition, the accuracy rate of more than 99 percent can also meet the requirements of chip manufacturers for designing and verifying chips. When the chip enters the mass production stage or the product stage, the IP manufacturer provides the key to the chip manufacturer, and the chip manufacturer writes the key into the starting flow of the SoC, so that the abuse of the IP core is avoided. The present embodiment is described by taking the preset probability of 0.3% as an example.
Specifically, the data processing module 20 includes a judging unit 210, a correct processing unit 220, and an error processing unit 230. As shown in fig. 3, this step may include:
Step 3.1, the judging unit 210 judges whether the received data to be processed belongs to preset special data, if yes, the step 3.2 is entered, and if not, the step 4 is entered. The duty ratio of the special data in all possible data to be processed is the preset probability. For example, the data to be processed is binary data with n bits, n is an integer greater than 0, the determining unit 210 determines whether the preset k specified bits are preset values, if yes, it is determined that the data to be processed belongs to preset special data, and if not, it is determined that the data to be processed does not belong to preset special data. k is an integer greater than 0 and less than n, The preset probability is obtained.
Step 3.2, the error processing unit 230 performs the second processing on the data to be processed, and outputs the error processing result. The second processing method has various modes, only the error result needs to be output, and the binary bit number of the error result can be kept the same as that of the data to be processed and is n bits.
Step 4, the correct processing unit 220 performs a first process on the received data to be processed, and outputs a correct processing result. The correct processing unit 220 performs the main or core function of the IP core, for example, the IP core is an IP core with an addition carry, and then the normal processing unit 220 is configured to calculate the sum of a plurality of input values, and the error processing unit 230 ignores the carry between bits to complete a no-carry addition operation.
The function of the key can be used for starting the correct processing unit 220, and also can be used for operating the correct processing unit 220, in other words, after the correct key is input once, the subsequently received data to be processed are processed by the correct processing unit 220, namely, only the correct key is input once; the key and the data to be processed may be input to the IP core together, and after the key is determined to be correct, the correct processing unit 220 processes the data to be processed which is input together, that is, the key needs to be input once for each processing of the data to be processed.
Specifically, the operation logic of the IP core (the key verification module 10 and the data processing module 20) may be a mapping function, which is designed based on a cryptographic algorithm in this embodiment, and implemented using hardware codes. The mapping function has two inputs, namely data input to be processed and key input; there is a data output of the same length as the data input to be processed. Under the condition that the secret key is correct, the input data to be processed can be output through correct calculation. In the case of incorrect keys, the output may be incorrect when the input is some special value, which may cause erroneous input values to be about 0.3% of the total input. This would make the whole chip work normally in most scenarios, but in some extreme cases work with errors. Only if the input key is correct, it can be ensured that no matter any value is input, the correct output can be obtained. The key may be contained in an SDK (Software Development Kit ), provided to the chip vendor, and the key may not be contained in the hardware circuitry.
The mapping function is exemplified below.
For circuits in a conventional IP core (circuit diagrams in a solid IP and a hard IP, and software codes capable of being converted into circuit diagrams, i.e. functional modules in a soft IP), the functions of the circuits can be abstracted into a feature matrix B. An n-bit binary input a= [ a 0 … an-1 ], after passing through the circuit (eigenvmatrix B), yields an n-bit output c= [ C 0 … cn-1 ].
In order to achieve the purpose of protecting the hardware IP core of the invention, we reform the feature matrix B of the existing IP core, and for some specific A (preset special data), we have a modified feature matrix B' as follows:
In this case, the output C' does not coincide with the desired output C, which may lead to subsequent calculation errors. To control that B '(corresponding to the error handling unit 230) will only be used in a small fraction of cases (e.g. the 0.3% probability mentioned above) for operation, we randomly choose a subset AX of these special a (preset special data) in advance, e.g. we can agree that B' is used when the value of [ a 0 … an-k ] = [1 … ] is used for operation, so that there is May lead to errors (e.g., when n=32, k=27, an error rate of about 0.3% may be met). Our purpose is to avoid unauthorized use, so B' is only introduced if unauthorized. A key value k 0 may be introduced to ensure that in the case where the correct k 0 is entered externally, B' will not be introduced and will still remain in use (corresponding to the correct processing unit 220).
To guarantee the reusability of the circuit, we need to introduce more than one key value, so that when delivering the hardware IP core, the plastic source can be performed by giving different key values to different clients. That is, there are other key values K 1、k2、…、km, that is, when the input key value does not belong to the set k= { K 0、k1、k2、…、km }, and the input value (data to be processed) belongs to the set AX, the feature matrix B is replaced with B'. We can recombine K, AX, B and B' into a new feature matrix, which is used to replace the original feature matrix B, input these designed matrix modules into an EDA (electronic design automation) tool, and generate corresponding circuits by the EDA tool to integrate into the hardware IP core.
The key value K is ultimately given by the application software and is not provided during the chip design phase. The key value may be part of the boot firmware or the running firmware and may include a special field header that may be more easily identified. After the chip is produced, the IP manufacturer will formally deliver the key to the chip manufacturer along with the SDK. Because there is more than one key, the same mapping function and different correct keys can be used as unique identities provided to a certain chip vendor.
The above process is also a management method, a usage method or a protection method of the IP core. By designing some key operation logic in the circuit as a mapping function that requires an external input of a key, the mapping function can perform a correct mapping of its function in case the key is correct. In case of incorrect key inputs, most inputs can be mapped to the correct outputs, but the mapping of some inputs will be wrong, i.e. the correct outputs cannot be obtained, resulting in a wrong function. Thus, the key is necessary compared to the current use of only a function-independent serial number as identification. The invention does not influence the integrated evaluation and verification of the chip to the IP core under the condition of no correct key, and can completely carry out small-scale test evaluation under the condition of no correct key. The key can also be used as a unique identification number of the chip item, and source tracing and evidence obtaining can be carried out according to the key. Therefore, the IP core is well protected from being stolen and abused, and the intellectual property of the IP core is protected.
Based on the IP core, the chip provided by the invention comprises at least one IP core, in other words, part of circuits of the chip are manufactured according to the IP core. Correspondingly, as shown in fig. 4, the chip comprises an IP core circuit comprising a key verification circuit 10 'and a data processing circuit 20'.
The key verification circuit 10 'is configured to receive an externally input key, determine whether the key is correct, and output the determination result to the data processing circuit 20'. That is, the function of the key verification circuit 10 'is the same as the key verification module 10, except that the key verification circuit 10' is in the form of an integrated circuit in a chip.
The data processing circuit 20' is configured to process the received data to be processed when the key is correct, and output a correct processing result; and when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result with preset probability. Likewise, the data processing circuit 20 'functions identically to the data processing module 20, except that the data processing circuit 20' is in the form of an integrated circuit in a chip.
The data processing circuit 20 'includes a determination sub-circuit 210', a correct processing sub-circuit 220', and an error processing sub-circuit 230'. The judging sub-circuit 210 'is configured to judge whether the received data to be processed belongs to preset special data, if yes, start the error processing sub-circuit 230' to perform a second type of processing on the data to be processed, and output an error processing result; if the data to be processed does not belong to the preset special data, the correct processing sub-circuit 220' is started to perform the first processing on the received data to be processed, and a correct processing result is output. That is, the functions of the judging sub-circuit 210', the correct processing sub-circuit 220' and the error processing sub-circuit 230' are respectively the same as the judging unit 210, the correct processing unit 220 and the error processing unit 230 of the above embodiment, except that each sub-circuit is presented in the form of an integrated circuit in a chip, and not described herein.
Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments may be implemented by hardware, or may be implemented by a computer program. When all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a computer readable storage medium, and the storage medium may include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc., and the program is executed by a computer to realize the above-mentioned functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the functions described above can be realized. In addition, when all or part of the functions in the above embodiments are implemented by means of a computer program, the program may be stored in a storage medium such as a server, another computer, a magnetic disk, an optical disk, a flash disk, or a removable hard disk, and the program in the above embodiments may be implemented by downloading or copying the program into a memory of a local device or updating a version of a system of the local device, and when the program in the memory is executed by a processor.
The foregoing description of the invention has been presented for purposes of illustration and description, and is not intended to be limiting. Several simple deductions, modifications or substitutions may also be made by a person skilled in the art to which the invention pertains, based on the idea of the invention.
Claims (8)
1. A method for managing an IP core, comprising:
Receiving an externally input key;
Judging whether the secret key is correct, if so, processing the received data to be processed, and outputting a correct processing result; if the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result with preset probability;
The processing the received data to be processed, outputting a processing result of errors with a preset probability, including:
Judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an erroneous processing result; otherwise, processing the data to be processed, and outputting a correct processing result; the special data is a subset of the data to be processed, k appointed bits of the special data are appointed values, and the duty ratio of the special data in all possible data to be processed is the preset probability.
2. The method of management according to claim 1, wherein the preset probability is not more than 1%.
3. The method of managing as set forth in claim 1, wherein said determining whether the key is correct comprises:
judging whether the key belongs to a preset key set, if so, determining that the key is correct, otherwise, determining that the key is incorrect; the key set includes a plurality of correct keys.
4. An IP core, comprising:
The key verification module is used for receiving an externally input key and judging whether the key is correct or not;
The data processing module is used for processing the received data to be processed when the secret key is correct and outputting a correct processing result; when the secret key is incorrect, processing the received data to be processed, and outputting an incorrect processing result with preset probability;
The data processing module processes the received data to be processed, and outputs an error processing result according to a preset probability, and the data processing module comprises:
Judging whether the received data to be processed belongs to preset special data or not, if so, processing the data to be processed, and outputting an erroneous processing result; otherwise, processing the data to be processed, and outputting a correct processing result; the special data is a subset of the data to be processed, k appointed bits of the special data are appointed values, and the duty ratio of the special data in all possible data to be processed is the preset probability.
5. The IP core of claim 4, wherein said predetermined probability is not more than 1%.
6. The IP core of claim 4, wherein said key verification module determining whether said key is correct comprises:
judging whether the key belongs to a preset key set, if so, determining that the key is correct, otherwise, determining that the key is incorrect; the key set includes a plurality of correct keys.
7. A chip, characterized in that part of the circuit of the chip is manufactured according to the IP core of any one of claims 4-6.
8. A computer readable storage medium, characterized in that the medium has stored thereon a program executable by a processor to implement the method of any one of claims 1 to 4.
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