Chaurasia et al., 2024 - Google Patents
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLSChaurasia et al., 2024
- Document ID
- 7909293668144856006
- Author
- Chaurasia R
- Sengupta A
- Publication year
- Publication venue
- Integration
External Links
Snippet
This paper presents a novel dual defense security methodology for fault detectable reusable hardware intellectual property (IP) core against reverse engineering and piracy using multi- cut based architectural obfuscation and handprint biometric signature, useful for consumer …
- 230000001052 transient effect 0 title description 29
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
- G06F21/12—Protecting executable software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/50—Computer-aided design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/07—Indexing scheme relating to G06F21/10, protecting distributed programs or content
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06F—ELECTRICAL DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for programme control, e.g. control unit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3247—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials involving digital signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/0021—Image watermarking
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Similar Documents
Publication | Publication Date | Title |
---|---|---|
Zhang et al. | Recent attacks and defenses on FPGA-based systems | |
Cui et al. | A robust FSM watermarking scheme for IP protection of sequential circuit design | |
Xie et al. | Mitigating SAT attack on logic locking | |
Rostami et al. | A primer on hardware security: Models, methods, and metrics | |
Sengupta et al. | Exploring low cost optimal watermark for reusable IP cores during high level synthesis | |
US7017043B1 (en) | Methods and systems for the identification of circuits and circuit designs | |
Rathor et al. | IP core steganography using switch based key-driven hash-chaining and encoding for securing DSP kernels used in CE systems | |
Liu et al. | VLSI supply chain security risks and mitigation techniques: A survey | |
Chang et al. | A blind dynamic fingerprinting technique for sequential circuit intellectual property protection | |
Anandakumar et al. | Rethinking watermark: Providing proof of IP ownership in modern socs | |
Chang et al. | Hardware IP watermarking and fingerprinting | |
Roy et al. | Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis | |
Anshul et al. | A survey of high level synthesis based hardware security approaches for reusable IP cores [feature] | |
Rathor et al. | Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores | |
Chaurasia et al. | Palmprint biometric versus encrypted hash based digital signature for securing DSP cores used in CE systems | |
Chaurasia et al. | Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS | |
Durvaux et al. | Intellectual property protection for integrated systems using soft physical hash functions | |
Chaurasia et al. | Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template | |
Sengupta et al. | Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs | |
Cui et al. | Stego-signature at logic synthesis level for digital design IP protection | |
Saha et al. | SoC: a real platform for IP reuse, IP infringement, and IP protection | |
Potkonjak et al. | 20 years of research on intellectual property protection | |
Naveenkumar et al. | Design of INV/BUFF Logic Locking For Enhancing the Hardware Security | |
Biswas | Using pattern of on-off routers and links and router delays to protect network-on-chip intellectual property | |
Sengupta et al. | Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure |