CN112563207A - Method for manufacturing semiconductor memory device - Google Patents
Method for manufacturing semiconductor memory device Download PDFInfo
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- CN112563207A CN112563207A CN201910911915.0A CN201910911915A CN112563207A CN 112563207 A CN112563207 A CN 112563207A CN 201910911915 A CN201910911915 A CN 201910911915A CN 112563207 A CN112563207 A CN 112563207A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
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- 239000003990 capacitor Substances 0.000 claims abstract description 39
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/764—Air gaps
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a manufacturing method of a semiconductor memory. The manufacturing method comprises the following steps: forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending in a first direction and being repeatedly arranged in a second direction; forming a barrier layer on the semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures; forming a sacrificial material layer filling the grooves between the bit line structures; forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along the second direction; forming a first protection spacer on the sidewall of the sacrificial spacer, wherein the first protection spacer and the bit line structure define a capacitor contact window together; the sacrificial spacers are removed, an air gap is formed between two first protective spacers corresponding to the same sacrificial spacer, and a sealing layer is formed on top of the air gap.
Description
Technical Field
The invention relates to the technical field of semiconductor memory devices, in particular to a manufacturing method of a semiconductor memory device.
Background
One of the trends in DRAM (dynamic Random Access Memory) is to reduce the size of devices such as transistors by process scaling, so as to achieve the purpose of producing more chips on one wafer. However, as the size of the semiconductor device is smaller and smaller, the parasitic capacitance generated between adjacent metal wires is increased, which results in the delay of reading signals in the DRAM, the strength of the signals is reduced, and more seriously results in the low yield and even zero yield of the chip.
The bit line structure of the dram commonly used at present usually adopts a stacked structure, and the silicon nitride is an etching mask layer and also an insulating layer, so as to prevent the metal conductive layer in the bit line structure from being damaged when the subsequent capacitor contact window is etched. On one hand, the thickness of the silicon nitride is thick enough to ensure that the silicon nitride remains after the capacitor contact window is etched, on the other hand, the silicon nitride of the bit line structure is etched in the process of forming the capacitor contact window structure, so that the height of the silicon nitride in the bit line direction is lower than that of the silicon nitride in the word line direction, and the thickness of the dielectric layer is uniform by a subsequent etching-back process, so that the process flow is complex.
Disclosure of Invention
In view of the above, it is necessary to provide a method for fabricating a semiconductor memory device, which aims at the problem of complicated process flow when forming a capacitor contact.
The embodiment of the invention provides a manufacturing method of a semiconductor memory device, which comprises the following steps:
forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending in a first direction and being repeatedly arranged in a second direction;
forming a barrier layer on a semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures;
forming a sacrificial material layer filling the grooves between the bit line structures;
forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along the second direction;
forming a first protective spacer on the sidewall of the sacrificial spacer, wherein the first protective spacer and the bit line structure define a capacitor contact window together;
and removing the sacrificial spacers, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap.
In one embodiment, the manufacturing method further includes: and synchronously forming a second protective spacer on the side wall of the bit line structure by utilizing the process for forming the first protective spacer.
In one embodiment, the step of forming the first protective spacer and the second protective spacer comprises:
forming an isolation material layer on the semiconductor substrate on which the sacrificial spacer is formed, wherein the isolation material layer covers the barrier layer and the sacrificial spacer;
and etching the isolation material layer to form the first protective isolator and the second protective isolator.
In one embodiment, the forming the hard mask pattern includes:
sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on the sacrificial material layer;
forming a target pattern on the photoresist layer;
forming a sacrificial oxide material layer on the surface of the photoresist layer containing the target pattern;
forming a hard mask pattern in the sacrificial oxide material layer and the second hard mask layer by using a back etching process;
removing the residual photoresist by taking the first hard mask layer as a barrier layer;
and transferring the hard mask pattern to the first hard mask layer by using a dry etching process.
In one embodiment, the manufacturing method further includes: after the sacrificial spacer is formed, the hard mask pattern is removed.
In one embodiment, the step of forming the sealing layer comprises:
forming an insulating material layer on the semiconductor substrate with the sacrificial spacer removed;
and etching the insulating layer material, and forming the sealing layer at the top end of the air gap.
In one embodiment, the barrier layer is formed using silicon nitride.
In one embodiment, the sacrificial material layer is formed of a material having an etch selectivity relative to the barrier layer.
In one embodiment, the sacrificial material layer is formed using one or more of organic carbon, borophosphosilicate glass, and phosphosilicate glass.
In one embodiment, the size of the sacrificial spacer is equal to the size of the air gap.
In one embodiment, the first direction and the second direction are perpendicular to each other.
In one embodiment, the manufacturing method further includes:
forming a non-metal conductive material layer in the capacitor contact window;
and forming a metal layer in the capacitor contact window, wherein the metal layer and the nonmetal conductive material layer jointly form a contact plug.
In one embodiment, the manufacturing method further includes: and removing the barrier layer between the bit lines before the non-metal conductive material layer to form the capacitor contact window.
In summary, the present invention provides a method for fabricating a semiconductor memory. The manufacturing method comprises the following steps: forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending in a first direction and being repeatedly arranged in a second direction; forming a barrier layer on a semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures; forming a sacrificial material layer filling the grooves between the bit line structures; forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along the second direction; forming a first protective spacer on the sidewall of the sacrificial spacer, wherein the first protective spacer and the bit line structure define a capacitor contact window together; and removing the sacrificial spacers, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap. In the invention, the dielectric material in the bit line structure can be prevented from being etched by forming the barrier layer, so that the thickness of the dielectric layer in the bit line structure can be properly reduced. In addition, the capacitive coupling effect between the metal lines can be well reduced by forming the air gap, so that the thickness of the dielectric layer in the bit line structure can be further reduced. In addition, after the capacitor contact window is formed, the dielectric layer above the bit line structure does not need to be further flattened, so that the process flow for forming the capacitor contact window is simplified.
Drawings
Fig. 1 is a flowchart of a method for fabricating a semiconductor memory device according to an embodiment of the present invention;
fig. 2 to fig. 3 are flowcharts illustrating a method for forming a barrier layer according to an embodiment of the present invention;
fig. 4-5 are flowcharts illustrating a method of forming a sacrificial spacer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram after forming a first protective spacer and a second protective spacer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram after forming a first protective spacer and a second protective spacer according to an embodiment of the present invention;
FIG. 8 is a flowchart of a method for forming a hard mask pattern according to an embodiment of the present invention;
FIG. 9 is a flowchart of a method of forming a first protective spacer and a second protective spacer according to an embodiment of the present invention;
fig. 10 is a flowchart of a method for forming a contact plug according to an embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather should be construed as broadly as the present invention is capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a method for manufacturing a semiconductor memory device, including:
in step S110, a plurality of bit line structures 200 are formed on the semiconductor substrate 100, wherein the bit line structures 200 extend along a first direction and are repeatedly arranged in a second direction, as shown in fig. 2.
Step S120 is to form a barrier layer 300 on the semiconductor substrate 100 on which the bit line structure 200 is formed, wherein the barrier layer 300 covers the semiconductor substrate 100 and the plurality of bit line structures 200, as shown in fig. 3.
In step S130, a sacrificial material layer 400 is formed to fill the grooves between the bit line structures 200, as shown in fig. 4.
Step S140 is to form a hard mask pattern, and etch the sacrificial material layer 400 by using the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers 410 extending along the second direction, as shown in fig. 5.
In step S150, a first protective spacer 510 is formed on the sidewall of the sacrificial spacer 410, and the first protective spacer 510 and the bit line structure together define a capacitor contact, as shown in fig. 6.
In step S160, the sacrificial spacers 410 are removed, an air gap AG is formed between two first protective spacers 510 corresponding to the same sacrificial spacer 410, and a sealing layer 600 is formed on top of the air gap AG, as shown in fig. 7.
The bit line structure of the dram commonly used at present usually adopts a stack structure of metal + dielectric material, and the dielectric layer is an etching mask layer and also an insulating layer. And the metal layer is prevented from being damaged during the subsequent etching of the capacitor contact window, and on one hand, the thickness of the dielectric layer is thick enough to ensure that the dielectric material is remained after the capacitor contact window is etched. On the other hand, the dielectric layer of the bit line structure is etched in the process of forming the capacitor contact window structure, so that the height of the dielectric layer in the bit line direction is lower than that of the dielectric layer in the word line direction, and the subsequent etching back process is needed to enable the dielectric layers to be at the same height. In addition, silicon nitride is an important dielectric material in the semiconductor manufacturing field, and is widely used for forming the dielectric layer of the bit line structure 200. In order to obtain a silicon nitride film meeting the requirements of semiconductor manufacturing processes, the silicon nitride film is usually grown in a furnace tube by a low-pressure vapor deposition technology at present, and a thick SIN film needs a long film time of several hours to more than ten hours, so that the production period is prolonged.
With the shrinking structure size of semiconductor memory devices, especially in the manufacturing process of dram with critical dimension less than 20nm, there are higher requirements for the insulating material of the conductive lines, for example, higher bandwidth is required to ensure good insulating performance, lower dielectric coefficient is required to ensure small parasitic capacitance and coupling effect, and various dielectric materials with low dielectric coefficient are widely used in semiconductor manufacturing. The air layer structure of silicon nitride-air layer-silicon nitride is one of the optimal low-k dielectric material structures, the air layer in the structure can ensure good insulating property, and meanwhile, the air layer has the lowest dielectric coefficient, and reduces the coupling effect and parasitic capacitance between metal wires, thereby achieving the effects of reducing IC delay and improving the response speed of a device.
In the present application, by forming the barrier layer 300, the dielectric material in the bit line structure 200 can be prevented from being etched away, so that the thickness of the dielectric layer in the bit line structure 200 can be reduced properly, in one embodiment, the thickness of the dielectric layer in the bit line structure 200 is 60 to 180 nm. In addition, the capacitive coupling effect between the metal lines can be well reduced by forming the air gap AG in the present invention, so that the thickness of the dielectric layer in the bit line structure 200 can be further reduced, and the time required for forming the dielectric layer can be reduced, thereby shortening the production cycle. In addition, after the formation of the capacitor contact, the dielectric layer above the bit line structure 200 does not need to be further planarized, thereby simplifying the process flow of forming the capacitor contact.
In a specific process, the semiconductor substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto.
In one embodiment, the barrier layer 300 is formed using silicon nitride. It will be appreciated that silicon nitride is chemically stable and reacts little with other inorganic acids than hydrofluoric acid and hot phosphoric acid, thereby facilitating the selection of suitable etching gases for etching other structures when used as the barrier layer 300. The process for forming the barrier layer 300 may include a deposition process suitable for the material to be deposited. For example, the formation process may include Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), metal organic CVD (mocvd), Atomic Layer Deposition (ALD), and plasma enhanced ALD (peald).
In one embodiment, the size of the sacrificial spacer 410 is equal to the size of the air gap AG. It is understood that the present invention improves the problem of large coupling capacitance between metal lines by etching away the sacrificial spacer 410 to form a void gap to form a capacitor contact window having a void gap, and thus the size of the sacrificial spacer 410 is equal to the size of the air gap AG.
In one embodiment, the sacrificial material layer 400 is formed of a material having an etch selectivity with respect to the barrier layer 300. It can be understood that, when the sacrificial material layer 400 is etched to form the air gap AG, the barrier layer 300 is used as a barrier to prevent the etching gas from damaging the dielectric layer in the bit line structure 200, thereby effectively reducing the thickness of the dielectric layer in the bit line structure 200. Therefore, in the present embodiment, when the barrier layer 300 is made of a silicon nitride material, the sacrificial material layer 400 may be formed by a material having an etching selectivity ratio with respect to silicon nitride, so that the sacrificial material layer 400 is rapidly etched, and the etching speed of the barrier layer 300 is almost 0.
In one embodiment, the sacrificial material layer 400 is formed using one or more of organic carbon, borophosphosilicate glass, and phosphosilicate glass. It can be understood that the organic carbon, the borophosphosilicate glass and the phosphosilicate glass have good filling capability, and can increase the flatness of the surface of the entire sacrificial material layer 400, thereby providing a wider process range for photolithography and subsequent processes.
Referring to fig. 4 and 8 together, in one embodiment, the forming of the hard mask pattern includes:
sequentially forming a first hard mask layer 710, a second hard mask layer 720 and a photoresist layer 730 on the sacrificial material layer 400;
forming a target pattern on the photoresist layer 730;
forming a sacrificial oxide layer 740 on the surface of the photoresist layer containing the target pattern;
forming a hard mask pattern in the sacrificial oxide material layer and the second hard mask layer by using a back etching process;
removing the residual photoresist by taking the first hard mask layer 710 as a barrier layer;
the target pattern is transferred to the first hard mask layer 710 using a dry etch process.
In this embodiment, a mask pattern is formed by a self-aligned double patterning technique. That is, an organic material (e.g., tetraethylorthosilicate) is deposited on the sacrificial material layer 400 to form a first hard mask layer, a silicon oxynitride material is deposited to form a second hard mask layer 720, and a layer of photoresist is coated on the surface of the second hard mask layer. Then, irradiating the photoresist through a mask plate by utilizing ultraviolet light to cause the photoresist in the exposure area to generate chemical reaction; and then, dissolving and removing the photoresist (the former is called positive photoresist, and the latter is called negative photoresist) in an exposed area or an unexposed area by a developing technology, and transferring the pattern on the mask plate to the photoresist layer 730, wherein the size of the residual photoresist on the photoresist layer 730 corresponds to the size of a subsequently formed capacitor contact window. Then depositing a sacrificial oxide material on the surface of the photoresist layer 730 to form a sacrificial oxide material layer, etching the top and the bottom of the sacrificial oxide material layer by an etch-back process, and reserving the sacrificial oxide material on the sidewall of the photoresist layer 730 to form a hard mask pattern; etching is then continued to transfer the mask pattern to the second hard mask layer 720. In one embodiment, the manufacturing method further includes: after the sacrificial spacer 410 is formed, the hard mask pattern is removed.
In this embodiment, the pattern is transferred to the first hard mask layer 710, and simultaneously, a portion of the sacrificial material layer 400 is etched, in this process, the etching machine integrates the etching of two different materials by adjusting the process parameters, but the process parameters should be controlled during the etching of the sacrificial material layer 400 to ensure that the bottom of the sacrificial material layer 400 is not completely opened and a thickness of 20 to 100nm remains. Furthermore, a small amount of the first hard mask layer is removed by dry etching or wet etching (preferably dry etching), and the step can be integrated with the previous etching process and completed in the same etching machine, so that the production efficiency is improved.
In one embodiment, the manufacturing method further includes: a second protective spacer 520 is simultaneously formed on the sidewalls of the bitline structure 200 using the process of forming the first protective spacer 510. It can be understood that, while the first protective spacer 510 is formed by using the etching process, due to the geometric effect of the sidewall of the bit line structure 200, the spacer material deposited on both sides of the bit line structure 200 will be preserved to form the second protective spacer 520, and the capacitive coupling effect between the metal in the bit line structure 200 and the metal in the capacitive contact window is further reduced by the second protective spacer 520.
Referring to fig. 6 and 9, in one embodiment, the step of forming the first protective spacer 510 and the second protective spacer 520 includes:
forming an isolation material layer 500 on the semiconductor substrate 100 on which the sacrificial spacer 410 is formed, the isolation material layer 500 covering the barrier layer 300 and the sacrificial spacer 410;
the isolation material layer 500 is etched to form the first protective spacer 510 and the second protective spacer 520.
In this embodiment, the isolation material layer 500 and the like are formed using an insulating material such as a silicon nitride material, silicon oxynitride, or silicon carbonitride as an isolation material. An isolation material is deposited on the surface of the sacrificial spacer 410 by using a plasma deposition process, and the isolation material layer 500 covers the sacrificial spacer 410 and the barrier layer 300. The top and bottom of the layer of isolation material 500 is then etched away using an etch-back process, exposing the top surfaces of the sacrificial spacer 410 and the barrier layer 300.
In one embodiment, the step of forming the sealing layer 600 comprises:
forming an insulating material layer 600a on the semiconductor substrate 100 from which the sacrificial spacer 410 is removed;
and etching the insulating layer material layer 600a, and forming the sealing layer 600 on the top end of the air gap AG.
It is understood that in order to avoid the occurrence of leakage caused by metal particles falling into the air gap AG in the subsequent process, the top end of the air gap AG needs to be sealed. In this embodiment, an insulating material is first formed by atomic deposition, and the insulating material may be silicon nitride or silicon oxynitride. The top and bottom of the insulating material layer are then removed by etching to form a sealing layer 600 on top of the air gap AG to form a spacer structure having a silicon nitride-air gap AG-silicon nitride layer structure, thereby reducing the coupling capacitance between adjacent metals.
In one embodiment, the first direction and the second direction are perpendicular to each other. It can be understood that when the first direction and the second direction are perpendicular to each other, the cross-sectional area of the capacitor contact window is increased, the resistance of the capacitor connection line formed in the capacitor contact window is reduced, and the performance of the semiconductor memory device is improved.
Referring to fig. 10, in one embodiment, the manufacturing method further includes:
forming a non-metal conductive material layer 710 in the capacitor contact window;
and forming a metal layer 720 in the capacitor contact window, wherein the metal layer 720 and the non-metal conductive material layer 710 together form a contact plug 700.
In this embodiment, the non-metallic conductive material layer 710 is formed by polysilicon, amorphous silicon, or other non-metallic conductive material containing or not containing silicon, and the metal layer 720 is formed by aluminum, tungsten, copper, titanium-aluminum alloy, or other suitable low resistance metallic conductive material.
In this embodiment, the specific steps of manufacturing the contact plug 700 by using polysilicon and metal tungsten include:
forming a polysilicon material layer 710a filling the capacitor contact window;
etching the polysilicon material layer 710a to a height required for forming a capacitor connecting line by an etching process;
forming a tungsten material layer 720a filling the upper part of the capacitor contact window;
then, the tungsten material is planarized by a chemical mechanical polishing process or a back etching process to expose the first protective spacers 510, the air gaps AG and the top surface of the bit line structure.
It is understood that the barrier layer 300 is also present at the bottom of the contact window before the contact plug 700 is formed, and thus the barrier layer 300 needs to be etched away. In one embodiment, the manufacturing method further includes: before the non-metal conductive material layer 710, the barrier layer 300 between the bit lines is removed to form the capacitor contact window. In some embodiments, the same etching process may be used to remove the top and bottom of the barrier layer 300 and the insulating material layer, which is beneficial to further simplify the process flow.
Based on the same inventive concept, embodiments of the present invention also provide a semiconductor memory device formed by using the above method for manufacturing a semiconductor memory device, the semiconductor memory device including a semiconductor substrate 100, a bit line structure 200, a barrier layer 300, a contact plug 700, a first protective spacer 510, a void gap, and a sealing layer 600.
The semiconductor substrate 100 may be a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator substrate, but not limited thereto.
The bit line structure 200 is disposed on the semiconductor substrate 100, and the bit line structure 200 extends along a first direction and is repeatedly arranged in a second direction. In this embodiment, the bit line structure 200 is designed to have a stacked structure of metal + dielectric layer. The metal used in the manufacturing process includes aluminum, tungsten, copper, titanium-aluminum alloy or other suitable low-resistance metal conductive material, the dielectric layer is made of a silicon nitride material, and in other embodiments, silicon oxynitride, silicon carbide nitride or other suitable insulating material may also be used, but not limited thereto.
The barrier layer 300 encapsulates the semiconductor substrate 100 and the bit line structure 200. In the present embodiment, the barrier layer 300 is formed to prevent the dielectric material in the bit line structure 200 from being etched away, so that the thickness of the dielectric layer in the bit line structure 200 can be reduced properly, for example, the thickness of the dielectric layer in the bit line structure 200 is 60 to 180nm in the present embodiment. In one embodiment, the barrier layer 300 is made of silicon nitride. It will be appreciated that silicon nitride is chemically stable and reacts little with other inorganic acids than hydrofluoric acid and hot phosphoric acid, thereby facilitating the selection of suitable etching gases for etching other structures when used as the barrier layer 300. The process for forming the barrier layer 300 may include a deposition process suitable for the material to be deposited. For example, the formation process may include Chemical Vapor Deposition (CVD), low pressure CVD (lpcvd), plasma enhanced CVD (pecvd), metal organic CVD (mocvd), Atomic Layer Deposition (ALD), and plasma enhanced ALD (peald).
The contact plug 700 is formed between two adjacent bit line structures 200. The contact plug 700 includes a non-metal conductive layer and a bit line metal which are stacked. In the present embodiment, the non-metal conductive layer may include polysilicon, amorphous silicon, or other non-metal conductive material containing silicon or not containing silicon, and the bit line metal may include aluminum, tungsten, copper, titanium-aluminum alloy, or other suitable low-resistance metal conductive material.
The first protective spacers 510 are disposed over the barrier layer 300, extend along the second direction, and are spaced apart by the bitline structure 200 in the second direction. In this embodiment, the two first protective spacers 510 with similar distances and the gap therebetween form a dielectric layer-air gap AG-dielectric layer spacing structure, which enhances the dielectric isolation effect, thereby reducing the capacitive coupling effect between the metal lines and improving the device performance. Furthermore, the thickness of the dielectric layer in the bit line structure 200 can be further reduced, and the time required for forming the dielectric layer can be reduced, thereby shortening the production cycle.
The air gap, formed between two matching first protective spacers 510, utilizes air to enhance dielectric isolation.
The sealing layer 600 is disposed on the top of the air gap AG to prevent metal from falling into the air gap AG in the subsequent process.
In one embodiment, the semiconductor memory device further includes a second protective spacer 520, the second protective spacer 520 being adjacent to a sidewall of the bit line structure 200. It is understood that while the first protective spacer 510 is formed by etching process, due to the geometric effect of the sidewall of the bit line structure 200, the spacer material deposited on both sides of the bit line structure 200 will be preserved to form the second protective spacer 520, and the capacitive coupling effect between the metal in the bit line structure 200 and the metal in the capacitive contact window is further reduced by the second protective spacer 520.
In one embodiment, the first direction and the second direction are perpendicular to each other. It can be understood that when the first direction and the second direction are perpendicular to each other, the cross-sectional area of the capacitor contact window is increased, the resistance of the capacitor connection line formed in the capacitor contact window is reduced, and the performance of the semiconductor memory device is improved.
In summary, the present invention provides a semiconductor memory and a method for fabricating the same. The manufacturing method comprises the following steps: forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending in a first direction and being repeatedly arranged in a second direction; forming a barrier layer on a semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures; forming a sacrificial material layer filling the grooves between the bit line structures; forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along the second direction; forming a first protective spacer on the sidewall of the sacrificial spacer, wherein the first protective spacer and the bit line structure define a capacitor contact window together; and removing the sacrificial spacers, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap. In the invention, the dielectric material in the bit line structure can be prevented from being etched by forming the barrier layer, so that the thickness of the dielectric layer in the bit line structure can be properly reduced. In addition, the capacitive coupling effect between the metal lines can be well reduced by forming the air gap, so that the thickness of the dielectric layer in the bit line structure can be further reduced. In addition, after the capacitor contact window is formed, the dielectric layer above the bit line structure does not need to be further flattened, so that the process flow for forming the capacitor contact window is simplified.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (13)
1. A method of fabricating a semiconductor memory device, comprising:
forming a plurality of bit line structures on a semiconductor substrate, the bit line structures extending in a first direction and being repeatedly arranged in a second direction;
forming a barrier layer on a semiconductor substrate on which the bit line structures are formed, wherein the barrier layer covers the semiconductor substrate and the plurality of bit line structures;
forming a sacrificial material layer filling the grooves between the bit line structures;
forming a hard mask pattern, and etching the sacrificial material layer by taking the hard mask pattern as a mask plate to form a plurality of strip-shaped sacrificial spacers extending along the second direction;
forming a first protective spacer on the sidewall of the sacrificial spacer, wherein the first protective spacer and the bit line structure define a capacitor contact window together;
and removing the sacrificial spacers, forming an air gap between two first protective spacers corresponding to the same sacrificial spacer, and forming a sealing layer on top of the air gap.
2. The method of manufacturing of claim 1, further comprising: and synchronously forming a second protective spacer on the side wall of the bit line structure by utilizing the process for forming the first protective spacer.
3. The method of manufacturing of claim 2, wherein the step of forming the first protective spacer and the second protective spacer comprises:
forming an isolation material layer on the semiconductor substrate on which the sacrificial spacer is formed, wherein the isolation material layer covers the barrier layer and the sacrificial spacer;
and etching the isolation material layer to form the first protective isolator and the second protective isolator.
4. The method of claim 1, wherein said forming a hard mask pattern comprises:
sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on the sacrificial material layer;
forming a target pattern on the photoresist layer;
forming a sacrificial oxide material layer on the surface of the photoresist layer containing the target pattern;
forming a hard mask pattern in the sacrificial oxide material layer and the second hard mask layer by using a back etching process;
removing the residual photoresist by taking the first hard mask layer as a barrier layer;
and transferring the hard mask pattern to the first hard mask layer by using a dry etching process.
5. The method of manufacturing of claim 1, further comprising: after the sacrificial spacer is formed, the hard mask pattern is removed.
6. The method of manufacturing of claim 1, wherein the step of forming the sealing layer comprises:
forming an insulating material layer on the semiconductor substrate with the sacrificial spacer removed;
and etching the insulating layer material, and forming the sealing layer at the top end of the air gap.
7. The method of claim 1, wherein the barrier layer is formed using silicon nitride.
8. The method of claim 1, wherein the sacrificial material layer is formed of a material having an etch selectivity relative to the barrier layer.
9. The method of claim 8, wherein the sacrificial material layer is formed using one or more of organic carbon, borophosphosilicate glass, and phosphosilicate glass.
10. The method of claim 1, wherein a size of the sacrificial spacer is equal to a size of the air gap.
11. The method of claim 1, wherein the first direction and the second direction are perpendicular to each other.
12. The method of manufacturing of claim 1, further comprising:
forming a non-metal conductive material layer in the capacitor contact window;
and forming a metal layer in the capacitor contact window, wherein the metal layer and the nonmetal conductive material layer jointly form a contact plug.
13. The method of manufacturing of claim 12, further comprising: and removing the barrier layer between the bit lines before the non-metal conductive material layer to form the capacitor contact window.
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