CN112259519A - Wafer level packaging structure of accelerometer - Google Patents
Wafer level packaging structure of accelerometer Download PDFInfo
- Publication number
- CN112259519A CN112259519A CN202011166039.2A CN202011166039A CN112259519A CN 112259519 A CN112259519 A CN 112259519A CN 202011166039 A CN202011166039 A CN 202011166039A CN 112259519 A CN112259519 A CN 112259519A
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- Prior art keywords
- wafer
- metal
- hole
- redistribution layer
- accelerometer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
- B81B7/007—Interconnections between the MEMS and external electrical signals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
- B81B2201/0228—Inertial sensors
- B81B2201/0235—Accelerometers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Pressure Sensors (AREA)
Abstract
The invention relates to the technical field of semiconductors, in particular to a wafer level packaging structure of an accelerometer, which is applied to the accelerometer and comprises the following components: a support wafer having a first surface and a second surface facing away from the first surface; a device wafer bonded to the first side of the support wafer; the redistribution layer is arranged on the second surface; the lead connecting pad is arranged on one surface of the device wafer, which faces the supporting wafer; the through holes are arranged on the supporting wafer and respectively correspond to the positions of the lead connecting pads, and the first surface of the supporting wafer penetrates through the second surface; and the metal conductor is arranged in the through hole, so that the lead connecting pad corresponding to the through hole is communicated with the first preset position of the redistribution layer. Has the advantages that: through set up the through-hole in the position that corresponds the lead bonding pad on supporting the wafer, set up metallic conductor in the through-hole for the lead bonding pad leads out through the second face that supports the wafer, and then uses the redistribution layer to carry out wafer level packaging, reduces the size of the product of final formation, promotes the performance of product, reduce cost.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a wafer level packaging structure of an accelerometer.
Background
Accelerometers have a wide range of applications, such as automotive airbags and automotive suspension systems, computer hard drive protection, LCD projectors, precision detonation systems for bombs and missiles, and mechanical vibration monitors.
At present, accelerometers in the market are all traditional epoxy resin packaging molded products, and for MEMS (Micro-Electro-Mechanical System) products such as accelerometers, the sensitivity to stress is higher, the stress generated in the process of packaging by using epoxy resin can directly influence the product performance, the requirements on production process and material characteristics are higher, the packaging cost and difficulty of the products are increased, and the packaging by using epoxy resin needs a longer production period. Therefore, the above problems are difficult problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above problems in the prior art, a wafer level package structure of an accelerometer is provided.
The specific technical scheme is as follows:
the invention provides a wafer level packaging structure of an accelerometer, which is applied to the accelerometer and comprises the following components:
the supporting wafer is provided with a first surface and a second surface back to the first surface;
a device wafer bonded to the first side of the support wafer;
a redistribution layer disposed on the second side;
at least one lead connecting pad arranged on one surface of the device wafer facing the supporting wafer;
the through hole is arranged on the supporting wafer and corresponds to the position of the at least one lead connecting pad respectively, and the first surface of the supporting wafer penetrates through the second surface;
and the metal conductor is arranged in the at least one through hole, so that the lead connecting pad corresponding to the at least one through hole is conducted with at least one first preset position of the redistribution layer.
Preferably, the method further comprises the following steps:
at least one solder ball respectively connected to a second predetermined position of the side of the redistribution layer facing away from the support wafer.
Preferably, the redistribution layer includes a metal interconnection structure, and the first predetermined location and the second predetermined location are conducted in a predetermined connection relationship through the metal interconnection structure.
Preferably, the device wafer is bonded to the support wafer by at least one metal pad.
Preferably, the metal pad is an aluminum pad.
Preferably, the first surface is provided with a cavity structure corresponding to the at least one metal pad.
Preferably, the at least one via is formed by a through silicon via process.
Preferably, the metal conductor is a metal layer filled in the at least one through hole.
Preferably, the metal layer is copper filled by an electroplating process.
Preferably, the accelerometer is formed in the device wafer.
The technical scheme has the following advantages or beneficial effects: through setting up the through-hole in the position that corresponds at least one lead bonding pad respectively on supporting the wafer to pierce through the second face by the first face that supports the wafer, and set up metallic conductor in the through-hole, make lead bonding pad lead out through the second face that supports the wafer, and then use redistribution layer to carry out wafer level encapsulation, reduce the size of the product of final formation, and promote the performance of product, reduce cost.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
Fig. 1 is a schematic structural diagram of an embodiment of the present invention.
The above reference numerals denote descriptions:
supporting the wafer 1; a device wafer 2; a redistribution layer 3; a metal interconnect structure 30; lead connection pads 4; a through hole 5; a metal conductor 6; solder balls 7; a metal pad 8; a cavity structure 80.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention provides a wafer level packaging structure of an accelerometer, which is applied to the accelerometer, as shown in figure 1, wherein the wafer level packaging structure comprises:
a supporting wafer 1, wherein the supporting wafer 1 has a first surface and a second surface opposite to the first surface;
a device wafer 2 bonded to the first side of the support wafer 1;
a redistribution layer 3 disposed on the second surface;
at least one lead connecting pad 4 arranged on one surface of the device wafer 2 facing the support wafer 1;
at least one through hole 5, which is arranged on the support wafer 1 and corresponds to the position of at least one lead connecting pad 4 respectively, and penetrates the second surface from the first surface of the support wafer 1;
and the metal conductor 6 is arranged in the at least one through hole 5, so that the lead connecting pad 4 corresponding to the at least one through hole 5 is communicated with at least one first preset position of the redistribution layer 3.
Specifically, in the present embodiment, during the bonding and wiring process between the support wafer 1 and the device wafer 2, a lead pad 4 is disposed on a surface of the device wafer 2 facing the support wafer 1, and at least one through hole 5 is disposed on the support wafer 1 corresponding to the lead pad 4, the through hole 5 penetrates through the second surface from the first surface of the support wafer 1, and the through hole 5 is further filled with a metal conductor 6, so that the lead pad 4 corresponding to the through hole 5 is conducted with the first predetermined position of the redistribution layer 3.
Further, set up redistribution layer 3 and directly carry out functional test after wafer level encapsulation at the second face that supports wafer 1 to need not to test the wafer, and then reduce the size of the product of final formation, and promote the performance of product, reduce cost.
In this embodiment, through providing the through holes 5 at positions corresponding to the at least one lead bonding pad 4 on the support wafer 1, respectively, and penetrating the second surface through the first surface of the support wafer 1, and providing the metal conductor 6 in the through holes 5, the lead bonding pads 4 are led out through the second surface of the support wafer 1, and then wafer level packaging is performed by using the redistribution layer 3, thereby reducing the size of the finally formed product, improving the performance of the product, and reducing the cost.
In a preferred embodiment, the method further comprises:
at least one solder ball 7 is respectively connected to a second predetermined position of the side of the redistribution layer 3 facing away from the support wafer 1.
Specifically, in the present embodiment, at least one solder ball 7 is disposed on the upper surface of the redistribution layer 3.
In a preferred embodiment, the redistribution layer 3 includes a metal interconnection structure 30, and the first predetermined location and the second predetermined location are conducted in a predetermined connection relationship through the metal interconnection structure 30.
Specifically, the redistribution layer 3 is provided with a metal interconnection structure 30 therein, which is used for connecting an upper portion, i.e. a second predetermined position, of the redistribution layer 3 with a lower portion, i.e. a first predetermined position, of the redistribution layer 3.
In a preferred embodiment, the device wafer 2 is bonded to the support wafer 1 by at least one metal pad 8.
Specifically, in the above technical solution, a metal pad 8 is disposed between the device wafer 2 and the support wafer 1, and the device wafer 2 and the support wafer 1 are bonded through the metal pad 8.
In a preferred embodiment, the metal pad 8 is an aluminum pad.
In a preferred embodiment, the first side is provided with a cavity structure 80 corresponding to the at least one metal pad 8.
Specifically, the metal pad 8 includes at least one cavity structure 80, and a portion of the metal pad 8 excluding the cavity structure 80 is a solder joint, so as to bond the first surface of the support wafer 1 and the device wafer 2.
In a preferred embodiment, the at least one via 5 is formed by a through silicon via process.
Specifically, in the above technical solution, the metal conductor 6 is filled in the through hole 5 by a through silicon via process.
In a preferred embodiment, the metal conductor 6 is a metal layer filled in the at least one via 5.
In a preferred embodiment, the metal layer is copper filled by an electroplating process.
In a preferred embodiment, the accelerometer is formed in a device wafer.
The technical scheme has the following advantages or beneficial effects: through setting up the through-hole in the position that corresponds at least one lead bonding pad respectively on supporting the wafer to pierce through the second face by the first face that supports the wafer, and set up metallic conductor in the through-hole, make lead bonding pad lead out through the second face that supports the wafer, and then use redistribution layer to carry out wafer level encapsulation, reduce the size of the product of final formation, and promote the performance of product, reduce cost.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A wafer level packaging structure of an accelerometer is applied to the accelerometer and is characterized by comprising:
the supporting wafer is provided with a first surface and a second surface back to the first surface;
a device wafer bonded to the first side of the support wafer;
a redistribution layer disposed on the second side;
at least one lead connecting pad arranged on one surface of the device wafer facing the supporting wafer;
the through hole is arranged on the supporting wafer and corresponds to the position of the at least one lead connecting pad respectively, and the first surface of the supporting wafer penetrates through the second surface;
and the metal conductor is arranged in the at least one through hole, so that the lead connecting pad corresponding to the at least one through hole is conducted with at least one first preset position of the redistribution layer.
2. The wafer level package structure of claim 1, further comprising:
at least one solder ball respectively connected to a second predetermined position of the side of the redistribution layer facing away from the support wafer.
3. The wafer-level package structure of claim 2, wherein the redistribution layer includes a metal interconnect structure, and the first predetermined location and the second predetermined location are in a predetermined connection relationship through the metal interconnect structure.
4. The wafer-level package structure of claim 1, wherein the device wafer is bonded to the support wafer through at least one metal pad.
5. The wafer level package structure of claim 4, wherein the metal pads are aluminum pads.
6. The wafer-level package structure of claim 4, wherein the first face is provided with a cavity structure corresponding to the at least one metal pad.
7. The wafer level package structure of claim 1, in which the at least one via is formed by a through silicon via process.
8. The wafer-level package structure of claim 7, wherein the metal conductor is a metal layer filled in the at least one via.
9. The wafer-level package structure of claim 8, wherein the metal layer is copper filled by an electroplating process.
10. The wafer level package structure of any of claims 1-9, wherein the accelerometer is formed in the device wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011166039.2A CN112259519A (en) | 2020-10-27 | 2020-10-27 | Wafer level packaging structure of accelerometer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011166039.2A CN112259519A (en) | 2020-10-27 | 2020-10-27 | Wafer level packaging structure of accelerometer |
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| Publication Number | Publication Date |
|---|---|
| CN112259519A true CN112259519A (en) | 2021-01-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011166039.2A Pending CN112259519A (en) | 2020-10-27 | 2020-10-27 | Wafer level packaging structure of accelerometer |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750521B1 (en) * | 1999-10-22 | 2004-06-15 | Delphi Technologies, Inc. | Surface mount package for a micromachined device |
| CN103253625A (en) * | 2012-02-17 | 2013-08-21 | 台湾积体电路制造股份有限公司 | Micro-electro mechanical systems (mems) structures and methods of forming the same |
| CN105977222A (en) * | 2016-06-15 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave device wafer level packaging structure and packaging method thereof |
-
2020
- 2020-10-27 CN CN202011166039.2A patent/CN112259519A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6750521B1 (en) * | 1999-10-22 | 2004-06-15 | Delphi Technologies, Inc. | Surface mount package for a micromachined device |
| CN103253625A (en) * | 2012-02-17 | 2013-08-21 | 台湾积体电路制造股份有限公司 | Micro-electro mechanical systems (mems) structures and methods of forming the same |
| CN105977222A (en) * | 2016-06-15 | 2016-09-28 | 苏州晶方半导体科技股份有限公司 | Semiconductor chip packaging structure and packaging method |
| CN109286385A (en) * | 2018-09-13 | 2019-01-29 | 中国电子科技集团公司第二十六研究所 | Surface acoustic wave device wafer level packaging structure and packaging method thereof |
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| CB02 | Change of applicant information |
Address after: Room 307, 3rd floor, 1328 Dingxi Road, Changning District, Shanghai 200050 Applicant after: Shanghai Sirui Technology Co.,Ltd. Address before: Floor 1, building 2, No. 235, Chengbei Road, Jiading District, Shanghai, 201800 Applicant before: QST Corp. |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210122 |
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| RJ01 | Rejection of invention patent application after publication |