CN111540722B - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN111540722B CN111540722B CN202010643230.5A CN202010643230A CN111540722B CN 111540722 B CN111540722 B CN 111540722B CN 202010643230 A CN202010643230 A CN 202010643230A CN 111540722 B CN111540722 B CN 111540722B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/8585—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/8589—Bonding techniques using an inorganic non metallic glass type adhesive, e.g. solder glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention provides a chip packaging structure and a chip packaging method, and belongs to the technical field of chip packaging. Chip package structure, including: the circuit board comprises a substrate, wherein the substrate is provided with a circuit layer, the substrate is provided with a connecting structure, the connecting structure comprises a glue inlet hole, a glue outlet hole and a channel which are communicated with each other, the channel is formed in the substrate and is connected with the circuit layer, the glue inlet hole and the glue outlet hole are formed in one side of a board surface of the substrate, a conductive colloid is filled in the connecting structure, a first chip is mounted on the substrate in an attached mode, and the leading-out end of the first chip is bonded with the connecting structure through the conductive colloid. The invention aims to provide a chip packaging structure and a chip packaging method.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging method.
Background
With the rapid development of the semiconductor industry, Flip Chip (FC) technology is widely used in electronic products.
In the current flip chip mounting, a bump formed on a surface of a chip and connected to a terminal is generally used to solder the chip on a pad of a substrate, so as to connect the chip with a circuit layer in the substrate through the bump.
However, when the bumps of the chip and the pads of the substrate are bonded, the substrate and the chip are easily deformed by the high heat generated in the bonding process, and the bonding structure formed after bonding is affected by the deformation stress due to the difference in the expansion coefficients of the substrate and the chip, resulting in poor bonding.
Disclosure of Invention
The invention aims to provide a chip packaging structure and a chip packaging method.
The embodiment of the invention is realized by the following steps:
in one aspect of the embodiments of the present invention, a chip package structure is provided, including: the circuit board comprises a substrate, wherein the substrate is provided with a circuit layer, the substrate is provided with a connecting structure, the connecting structure comprises a glue inlet hole, a glue outlet hole and a channel which are communicated with each other, the channel is formed in the substrate and is connected with the circuit layer, the glue inlet hole and the glue outlet hole are formed in one side of a board surface of the substrate, a conductive colloid is filled in the connecting structure, a first chip is mounted on the substrate in an attached mode, and the leading-out end of the first chip is bonded with the connecting structure through the conductive colloid.
Optionally, the first chip has a plurality of terminals, and the connection structures are respectively provided in a plurality of numbers corresponding to the terminals of the first chip.
Optionally, the leading-out end of the first chip is connected with the glue outlet of the connection structure.
Optionally, the board surface of the substrate has a mounting area corresponding to the first chip and a non-mounting area surrounding the mounting area, the glue outlet of the connection structure is located in the mounting area, and the glue inlet is located in the non-mounting area.
Optionally, the chip package structure further includes a second chip stacked on the first chip, and the lead-out end of the second chip is bonded to the glue inlet hole of the connection structure through a conductive glue.
Optionally, a bump is formed on the terminal of the second chip, and the bump is connected to the glue inlet of the connection structure.
Optionally, the bump includes a conductive pillar and a solder ball, one end of the conductive pillar is connected to the leading-out end of the second chip, the other end of the conductive pillar is connected to the solder ball, and the solder ball is connected to the glue inlet of the connection structure.
Optionally, a plastic package body is disposed on one side of the substrate, where the first chip is disposed, to plastic package the first chip on the substrate.
In another aspect of the embodiments of the present invention, a chip packaging method is provided, including:
forming a channel in the substrate on which the circuit layer is formed; wherein, the channel is connected with the circuit layer;
a glue inlet hole and a glue outlet hole which are communicated with the channel are respectively formed on one side plate surface of the substrate, and the channel, the glue inlet hole and the glue outlet hole form a connecting structure;
and mounting the first chip on the substrate, and filling the connecting structure with conductive colloid through the glue inlet hole so as to bond the leading-out end of the first chip and the glue outlet hole through the conductive colloid.
Optionally, mounting the first chip on the substrate, and filling the conductive colloid into the connection structure through the glue inlet hole, so that the terminal of the first chip is bonded to the glue outlet hole through the conductive colloid, and the method further includes:
mounting a second chip on the substrate so that the leading-out end of the second chip is bonded with the glue inlet hole through the conductive glue; wherein the second chip is stacked on the first chip.
The embodiment of the invention has the beneficial effects that:
the chip packaging structure provided by the embodiment of the invention comprises a substrate with a circuit layer, and a connecting structure is formed on the substrate. This connection structure is including advancing gluey hole, play gluey hole and the passageway that communicates each other, and wherein, the passageway is formed in the base plate, and is connected with the circuit layer in the base plate, advances gluey hole and goes out gluey hole and all forms on one side face of base plate. All pack in this connection structure has conductive adhesive, and the base plate facing is equipped with first chip, and the end of drawing forth of first chip passes through conductive adhesive with connection structure and bonds. Because the channel of the connecting structure is connected with the circuit layer in the substrate, and the first chip is bonded through the conductive colloid filled in the connecting structure, the leading-out end of the first chip can be conducted with the circuit layer in the substrate. The chip is packaged through the packaging structure, and the electric connection between the leading-out end of the chip and the circuit layer of the chip substrate is bonded through the conductive adhesive, so that the problem that when the flip chip is mounted on the substrate, the chip and the substrate are poorly connected due to welding is avoided, and the performance and yield of chip packaging are improved.
According to the chip packaging method provided by the embodiment of the invention, the channel is formed in the substrate with the circuit layer, and the channel is connected with the circuit layer. And then a glue inlet hole and a glue outlet hole which are communicated with the channel are respectively formed on the board surface on one side of the substrate, so that the channel, the glue inlet hole and the glue outlet hole form a connecting structure. Then, the first chip is mounted on the substrate, and the connecting structure is filled with the conductive colloid through the glue inlet hole, so that the leading-out end of the first chip is bonded with the glue outlet hole through the conductive colloid. By adopting the method, the chip can be fixed on the substrate through the conductive adhesive, and the leading-out end of the chip and the circuit layer of the substrate can be conducted by utilizing the conductive adhesive, so that the poor electric connection and combination of the chip and the substrate caused by welding can be avoided, and the chip packaging performance is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a chip package structure according to an embodiment of the invention;
fig. 3 is a third schematic structural diagram of a chip package structure according to an embodiment of the present invention;
fig. 4 is a flowchart illustrating a chip packaging method according to an embodiment of the invention;
fig. 5 is a second flowchart illustrating a chip packaging method according to an embodiment of the invention.
Icon: 110-a substrate; 111-a line layer; 120-a linking structure; 121-glue inlet holes; 122-glue outlet holes; 123-channel; 130-a first chip; 140-a second chip; 150-bumps; 151-conductive post; 152-solder ball; 160-plastic package body.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
Furthermore, the terms "horizontal", "vertical" and the like do not imply that the components are required to be absolutely horizontal or pendant, but rather may be slightly inclined. For example, "horizontal" merely means that the direction is more horizontal than "vertical" and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
An embodiment of the present invention provides a chip packaging structure, as shown in fig. 1, including: the substrate 110 with the circuit layer 111 is formed, the substrate 110 is formed with the connection structure 120, the connection structure 120 includes a glue inlet hole 121, a glue outlet hole 122 and a channel 123 which are mutually communicated, the channel 123 is formed in the substrate 110 and is connected with the circuit layer 111, the glue inlet hole 121 and the glue outlet hole 122 are formed on a side plate surface of the substrate 110, the connection structure 120 is filled with a conductive adhesive, the substrate 110 is provided with a first chip 130 in an attached manner, and a leading-out end of the first chip 130 is bonded with the connection structure 120 through the conductive adhesive.
In practical applications, the glue outlet 122 and the glue inlet 121 may be disposed in a plurality of holes, which is not limited herein.
In the connection structure 120, the vias 123 formed in the substrate 110 may be connected to the circuit layer 111 in the substrate 110 by providing conductive sidewalls on the sidewalls of the vias 123, and connecting the conductive sidewalls to the circuit layer 111 in the substrate 110. Of course, an opening may be provided on a sidewall of the channel 123, so that a corresponding connection point of the circuit layer 111 in the substrate 110 communicates with the channel 123 through the opening, so as to connect the channel 123 and the circuit layer 111. Of course, in the embodiment of the present invention, how the channel 123 is connected to the circuit layer 111 is not limited herein, as long as the conductive paste filled in the connection structure 120 can be electrically conducted with the circuit layer 111.
In practical applications, the terminal of the first chip 130 may be connected to one of the glue inlet 121 and the glue outlet 122 through the conductive glue filled in the connection structure 120, and of course, may also be connected to both the glue inlet 121 and the glue outlet 122, which is not limited herein. Moreover, according to different specific connection forms of the terminal of the first chip 130 and the connection structure 120, the glue inlet hole 121 and the glue outlet hole 122 may both be located in an orthographic projection of the first chip 130 on the substrate 110, or one of the glue inlet hole 121 or the glue outlet hole 122 may be located in the orthographic projection. And are not limited herein.
The chip package structure provided by the embodiment of the invention comprises a substrate 110 formed with a circuit layer 111, and a connection structure 120 is formed on the substrate 110. The connecting structure 120 includes a glue inlet hole 121, a glue outlet hole 122 and a channel 123 that are mutually communicated, wherein the channel 123 is formed in the substrate 110 and connected to the circuit layer 111 in the substrate 110, and the glue inlet hole 121 and the glue outlet hole 122 are formed on a side plate surface of the substrate 110. The connection structure 120 is filled with a conductive adhesive, the substrate 110 is mounted with the first chip 130, and the leading-out end of the first chip 130 is bonded to the connection structure 120 through the conductive adhesive. Since the channel 123 of the connection structure 120 is connected to the circuit layer 111 in the substrate 110, and the first chip 130 is bonded by the conductive paste filled in the connection structure 120, the terminal of the first chip 130 can be conducted with the circuit layer 111 in the substrate 110. The chip is packaged through the packaging structure, and the electric connection between the leading-out end of the chip and the circuit layer 111 of the chip substrate 110 is bonded through the conductive adhesive, so that the problem that when the chip is mounted on the substrate 110 in a flip-chip mode, the chip and the substrate 110 are poor in electric connection and poor in combination due to welding can be avoided, and the performance and yield of chip packaging are improved.
Alternatively, as shown in fig. 1, when there are a plurality of terminals of the first chip 130, the connection structures 120 are provided in a plurality corresponding to the terminals of the first chip 130, respectively.
Each of the terminals of the first chip 130 may be connected to the glue inlet 121 and the glue outlet 122 of the corresponding connection structure 120 at the same time, or may be connected to only one of the glue inlet 121 or the glue outlet 122 of the corresponding connection structure 120. Moreover, when each of the terminals of the first chip 130 is connected to one of the glue inlet hole 121 and the glue outlet hole 122 of the corresponding connection structure 120, each of the terminals may be connected to the corresponding glue outlet hole 122, or connected to the corresponding glue inlet hole 121, or randomly connected to the corresponding glue outlet hole 122 or the glue inlet hole 121, which is not limited herein.
Optionally, as shown in fig. 1, the terminals of the first chip 130 are connected to the glue holes 122 of the connection structure 120.
The leading-out terminal of the first chip 130 is connected to the glue outlet 122 of the connection structure 120, so that it is more convenient to fill the connection structure 120 with the conductive glue. Moreover, since the glue inlet hole 121 of the connection structure 120 is not connected to the terminal of the first chip 130, but is in conduction with the terminal and the circuit layer 111, the performance test of the package structure can be performed by using the glue inlet hole 121, and the operation is more convenient and faster.
Optionally, as shown in fig. 2, the board surface of the substrate 110 has a mounting area corresponding to the first chip 130 and a non-mounting area surrounding the mounting area, the glue outlet 122 of the connection structure 120 is located in the mounting area, and the glue inlet 121 is located in the non-mounting area.
Here, a mounting area corresponding to the first chip 130 is located in an orthographic projection of the first chip 130 on the substrate 110. When the leading-out end of the first chip 130 is connected to the glue outlet 122, the glue inlet 121 is disposed in the non-mounting region, and the glue outlet 122 is disposed in the mounting region, so that the first chip 130 can be mounted in the mounting region, and then the glue inlet 121 is used to fill the conductive glue into the connection structure 120. Thereby avoiding the problem of infirm bonding caused by the fact that the conductive adhesive is cured in advance due to the fact that the adhesive is filled firstly and then attached.
Optionally, as shown in fig. 3, the chip package structure further includes a second chip 140 stacked on the first chip 130, and the terminals of the second chip 140 are bonded to the glue inlet holes 121 of the connection structure 120 through a conductive glue.
The first chip 130 and the second chip 140 are generally chips having the same function and internal circuit. And the second chip 140 is generally located on a side of the first chip 130 away from the substrate 110. When the glue outlet 122 of the connection structure 120 is located in the mounting region, the glue inlet 121 is located in the non-mounting region, and the leading-out end of the first chip 130 is connected to the glue outlet 122, the chip package structure may further connect to the second chip 140 through the glue inlet 121, so as to further improve the performance of the package structure.
Optionally, as shown in fig. 3, a bump 150 is formed at the terminal of the second chip 140, and the bump 150 is connected to the glue inlet hole 121 of the connection structure 120.
By forming the bump 150 on the lead-out terminal of the second chip 140, the bump 150 is connected to the glue inlet hole 121 of the connection structure 120, so that the lead-out terminal of the second chip 140 can be more easily connected to the glue inlet hole 121. In addition, the bumps 150 with different heights can form a gap between the second chip 140 and the first chip 130, thereby reducing the problem of poor heat dissipation caused by chip stacking.
Optionally, as shown in fig. 3, the bump 150 includes a conductive pillar 151 and a solder ball 152, one end of the conductive pillar 151 is connected to the terminal of the second chip 140, the other end is connected to the solder ball 152, and the solder ball 152 is connected to the glue inlet 121 of the connection structure 120.
By configuring the bump 150 as a structure having the conductive pillar 151 and the solder ball 152, the solder ball 152 and the conductive adhesive can be re-fused by using a hot-press fusion welding technique, so as to improve the bonding effect between the bump 150 and the conductive adhesive, improve the connection stability between the bump 150 and the adhesive inlet 121, and further improve the fixing effect between the second chip 140 and the substrate 110, and the reliability of the electrical connection between the second chip 140 and the circuit layer 111.
Optionally, as shown in fig. 1, a molding compound 160 is disposed on a side of the substrate 110 where the first chip 130 is disposed, so as to mold the first chip 130 on the substrate 110.
By providing the plastic package body 160 on the side of the substrate 110 on which the first chip 130 is provided, the first chip 130 can be protected by the plastic package body 160, and adverse effects of the external environment on the first chip 130 can be reduced.
When the package structure is further provided with the second chip 140, the first chip 130 and the second chip 140 may be simultaneously packaged by the package body 160.
In practical applications, a solder ball 152 or a pin, etc. connected to the circuit layer 111 is usually disposed on a side of the substrate 110 facing away from the first chip 130, so as to facilitate disposing the package structure on a circuit board or other structures.
In another aspect of the embodiments of the present invention, a chip packaging method is provided, as shown in fig. 4, including:
s101: a via 123 is formed in the substrate 110 formed with the wiring layer 111, wherein the via 123 is connected with the wiring layer 111.
S102: a glue inlet hole 121 and a glue outlet hole 122 which are communicated with the channel 123 are respectively formed on one side plate surface of the substrate 110, and the channel 123, the glue inlet hole 121 and the glue outlet hole 122 form a connecting structure 120.
S103: the first chip 130 is mounted on the substrate 110, and the connection structure 120 is filled with a conductive adhesive through the adhesive inlet 121, so that the terminal of the first chip 130 is bonded to the adhesive outlet 122 through the conductive adhesive.
The channel 123 may be formed on the substrate 110 by first forming a groove (which may be formed by etching, laser grooving, or the like) connecting the circuit of the circuit layer 111 on one surface of the circuit layer 111 structure of the substrate 110, and then laminating a substrate on the groove to form the final substrate 110, thereby forming the channel 123 in the substrate 110. Of course, the person skilled in the art may also form the channel 123 in other ways, which are not limited here.
In practical applications, after the first chip 130 is mounted, the chip package structure may be connected to other circuit boards or devices by performing ball-mounting (solder balls 152, etc.) or pins on a side of the substrate 110 away from the first chip 130. After the first chip 130 is mounted, the first chip 130 may be plastically packaged to protect the first chip 130, so as to avoid adverse effects of an external environment on the first chip 130.
In the chip packaging method provided by the embodiment of the invention, the channel 123 may be formed in the substrate 110 on which the circuit layer 111 is formed, and the channel 123 is connected to the circuit layer 111. Then, a glue inlet hole 121 and a glue outlet hole 122 communicated with the channel 123 are respectively formed on one side plate surface of the substrate 110, so that the channel 123, the glue inlet hole 121 and the glue outlet hole 122 form a connecting structure 120. Then, the first chip 130 is mounted on the substrate 110, and the connection structure 120 is filled with a conductive adhesive through the adhesive inlet 121, so that the terminal of the first chip 130 is bonded to the adhesive outlet 122 through the conductive adhesive. By adopting the method, the chip can be fixed on the substrate 110 through the conductive adhesive, and the leading-out end of the chip and the circuit layer 111 of the substrate 110 can be conducted through the conductive adhesive, so that poor electrical connection and combination between the chip and the substrate 110 caused by welding can be avoided, and the chip packaging performance is improved.
Optionally, after the first chip 130 is mounted on the substrate 110 and the connection structure 120 is filled with a conductive adhesive through the glue inlet hole 121, so that the terminal of the first chip 130 is bonded to the glue outlet hole 122 through the conductive adhesive, as shown in fig. 5, the method further includes:
s201: the second chip 140 is mounted on the substrate 110, so that the terminals of the second chip 140 are bonded to the glue inlet holes 121 through the conductive glue. The second chip 140 is stacked on the first chip 130.
It should be noted that the first chip 130 and the second chip 140 are generally chips having the same functions and internal circuits. And the second chip 140 is generally located on a side of the first chip 130 away from the substrate 110.
By stacking the first chip 130 and the second chip 140, the performance of the package structure for realizing the corresponding functions can be further improved.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific implementation manners and effects of the chip packaging methods described above may also refer to the corresponding descriptions and explanations in the foregoing chip packaging structure embodiments, and no further description is provided in the present disclosure.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A chip package structure, comprising: the circuit board comprises a substrate with a circuit layer, wherein the substrate is provided with a connecting structure, the connecting structure comprises a glue inlet hole, a glue outlet hole and a channel which are communicated with each other, the channel is formed in the substrate and is connected with the circuit layer, the glue inlet hole and the glue outlet hole are formed in one side board surface of the substrate, conductive glue is filled in the connecting structure, a first chip is attached to the substrate, the leading-out end of the first chip is bonded with the connecting structure through the conductive glue, and the leading-out end of the first chip is connected with the glue outlet hole of the connecting structure; the surface of the substrate is provided with a mounting area corresponding to the first chip and a non-mounting area surrounding the mounting area, the glue outlet hole of the connecting structure is located in the mounting area, and the glue inlet hole is located in the non-mounting area; the chip packaging structure further comprises a second chip stacked on the first chip, and the leading-out end of the second chip is bonded with the glue inlet hole of the connecting structure through the conductive glue.
2. The chip packaging structure according to claim 1, wherein the first chip has a plurality of terminals, and the connection structures are respectively provided in a plurality corresponding to the terminals of the first chip.
3. The chip package structure of claim 1, wherein a bump is formed on the terminal of the second chip, and the bump is connected to the glue inlet of the connection structure.
4. The chip package structure according to claim 3, wherein the bump includes a conductive pillar and a solder ball, one end of the conductive pillar is connected to the terminal of the second chip, the other end of the conductive pillar is connected to the solder ball, and the solder ball is connected to the glue inlet of the connection structure.
5. The chip packaging structure according to claim 1, wherein a molding compound is disposed on a side of the substrate where the first chip is disposed, so as to mold the first chip on the substrate.
6. A method of chip packaging, comprising:
forming a channel in the substrate on which the circuit layer is formed; wherein the channel is connected with the line layer;
a glue inlet hole and a glue outlet hole which are communicated with the channel are respectively formed on one side plate surface of the substrate, the channel, the glue inlet hole and the glue outlet hole form a connecting structure, the glue outlet hole of the connecting structure is positioned in a mounting area, and the glue inlet hole is positioned in a non-mounting area;
mounting a first chip on the substrate, and filling a conductive colloid into the connecting structure through the glue inlet hole so as to bond the leading-out end of the first chip with the glue outlet hole through the conductive colloid;
mounting a second chip on the substrate so that the leading-out end of the second chip is bonded with the glue inlet hole through the conductive glue body; wherein the second chip is stacked on the first chip.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010643230.5A CN111540722B (en) | 2020-07-07 | 2020-07-07 | Chip packaging structure and packaging method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010643230.5A CN111540722B (en) | 2020-07-07 | 2020-07-07 | Chip packaging structure and packaging method |
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| CN111540722A CN111540722A (en) | 2020-08-14 |
| CN111540722B true CN111540722B (en) | 2021-05-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195422A (en) * | 1996-06-07 | 1998-10-07 | 松下电器产业株式会社 | Method for mounting semiconductor chip |
| US20060237229A1 (en) * | 2005-04-25 | 2006-10-26 | Brother Kogyo Kabushiki Kaisha | Method for forming pattern and a wired board |
| CN101207054A (en) * | 2006-12-21 | 2008-06-25 | 奇梦达股份公司 | Method for fabricating a circuit |
-
2020
- 2020-07-07 CN CN202010643230.5A patent/CN111540722B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1195422A (en) * | 1996-06-07 | 1998-10-07 | 松下电器产业株式会社 | Method for mounting semiconductor chip |
| US20060237229A1 (en) * | 2005-04-25 | 2006-10-26 | Brother Kogyo Kabushiki Kaisha | Method for forming pattern and a wired board |
| CN101207054A (en) * | 2006-12-21 | 2008-06-25 | 奇梦达股份公司 | Method for fabricating a circuit |
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| CN111540722A (en) | 2020-08-14 |
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