CN112086355B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN112086355B CN112086355B CN201910507430.5A CN201910507430A CN112086355B CN 112086355 B CN112086355 B CN 112086355B CN 201910507430 A CN201910507430 A CN 201910507430A CN 112086355 B CN112086355 B CN 112086355B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 238000005530 etching Methods 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 25
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 13
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 10
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 10
- 230000000694 effects Effects 0.000 abstract description 14
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 268
- 239000007789 gas Substances 0.000 description 41
- 239000011241 protective layer Substances 0.000 description 12
- 238000002955 isolation Methods 0.000 description 9
- 230000017525 heat dissipation Effects 0.000 description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004380 ashing Methods 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 229920005591 polysilicon Polymers 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a semiconductor device and a forming method thereof, comprising the following steps: providing a substrate, and sequentially and alternately forming at least one sacrificial layer and at least one lining layer on the substrate; etching the lining layer, the sacrificial layer and the substrate with partial thickness, wherein a plurality of fin parts are formed on the substrate; forming a pseudo gate structure crossing the fin part on the substrate; removing part of the sacrificial layer on the fin part under the pseudo gate structure to form a channel; the formation method of the invention can eliminate the self-heating effect of the semiconductor device in the use process and improve the use performance and stability of the semiconductor device.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin field effect transistor includes: the isolation structure covers part of the side wall of the fin part, and the grid structure is positioned on the substrate and spans across the fin part; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
With the ever-increasing demands on device performance, four-sided controlled fully-enclosed Gate structures (Gate-all-around) have evolved. Semiconductor devices having a Gate-all-around structure possess special properties that effectively limit short channel effects (Short channel effect), and it is the industry that is highly desirous in innovations that continuously shrink device dimensions in compliance with moore's law. The device channel formed by the thin silicon film in the fully-enclosed gate structure is surrounded by the gate of the device and is controlled by the gate only.
The self-heating effect is a phenomenon that the current of the device is reduced because the mobility of a carrier of the device is reduced due to the increase of the internal temperature when the device works; the special three-dimensional structure of the fin field effect transistor device also makes heat generated during operation of the fin field effect transistor device difficult to dissipate.
Therefore, the performance of the existing formed full-surrounding gate structure semiconductor device is poor.
Disclosure of Invention
The invention solves the problem of providing a semiconductor device and a forming method thereof, thereby improving the service performance of the semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising the steps of: providing a substrate, and sequentially and alternately forming at least one sacrificial layer and at least one lining layer on the substrate; etching the lining layer, the sacrificial layer and the substrate with partial thickness, wherein a plurality of fin parts are formed on the substrate; forming a pseudo gate structure crossing the fin part on the substrate; and removing part of the sacrificial layer on the fin part under the pseudo gate structure to form a channel.
Optionally, the plurality of fin portions includes at least a first fin portion and a second fin portion.
Optionally, the width of the first fin portion is 2-3 times that of the second fin portion, and the sacrificial layer on the first fin portion under the dummy gate structure is removed to form a channel.
Optionally, after removing the sacrificial layer, replacing the dummy gate structure with a metal gate structure, where the metal gate structure fills the channel.
Optionally, after forming a dummy gate structure crossing the fin portion on the substrate, removing a part of the sacrificial layer on the fin portion under the dummy gate structure, and before forming a channel, forming a side wall on a side wall of the dummy gate structure, and etching a part of the liner layer and the sacrificial layer on the fin portion in turn by using the side wall and the dummy gate structure as masks until the substrate is exposed.
Optionally, after exposing the substrate, removing a part of the sacrificial layer on the fin portion under the dummy gate structure, and before forming the channel, further including removing the sacrificial layer on the fin portion under the sidewall, and forming an inner sidewall on a sidewall of the sacrificial layer.
Optionally, after replacing the dummy gate structure with the metal gate structure, forming an epitaxial layer, where the epitaxial layer includes two ends of the liner layer on the etched fin portion.
Optionally, the material of the sacrificial layer includes one or more of silicon, germanium, silicon germanium, gallium arsenide.
Optionally, the material of the liner layer includes one or more of silicon, germanium, silicon germanium, gallium arsenide.
A semiconductor device formed by the method includes: the substrate is provided with a plurality of fin parts, the fin parts are separately positioned on the substrate, and a part of each fin part consists of a sacrificial layer and a lining layer; another part of each fin part consists of a lining layer and a channel; wherein: the sacrificial layer is positioned on the substrate and the lining, the lining is positioned on the sacrificial layer or the substrate, and the channel is positioned in the other part of each fin part; and the dummy gate structure is positioned on the substrate and spans across the fin part.
The present invention also provides a method of forming a semiconductor device, comprising the steps of: providing a substrate, wherein a plurality of fin parts are formed on the substrate; forming a protective layer on the substrate and the side wall of the fin part, wherein the top of the protective layer is level with the top of the fin part; etching to remove part of the fin portion at intervals; sequentially and alternately forming at least one sacrificial layer and at least one lining layer on the surface of the etched fin part; the number of layers of the sacrificial layers formed on the surfaces of the adjacent etched fin parts is different; the number of layers of the lining layer formed on the surfaces of the adjacent etched fin parts is different; and removing part of the protective layer, wherein the top of the protective layer is flush with the top of the etched fin part.
Optionally, the number of layers of the sacrificial layer formed on the surface of the fin portion after being etched at intervals is the same; meanwhile, the layers of the lining layers formed on the surfaces of the fin portions after being etched at intervals are the same.
Optionally, the number of layers of the sacrificial layer formed on the surface of the adjacent etched fin portion differs by 1-2 layers.
Optionally, the number of layers of the liner layer formed on the surface of the adjacent etched fin portion differs by 1-2 layers.
Optionally, after forming the sacrificial layer and the liner layer, removing the sacrificial layer, and forming a metal gate structure on the substrate, wherein the metal gate structure spans the etched fin portion and surrounds the liner layer.
A semiconductor device formed by the method includes: a substrate; a fin portion of partial thickness located on the substrate; sacrificial layer and liner layer, wherein: a sacrificial layer on the fin portion and the liner layer having a partial thickness; a liner layer on the sacrificial layer; the number of layers of the sacrificial layers on the fin parts with adjacent partial thicknesses is different; meanwhile, the layers of the lining layers on the fin parts with adjacent partial thicknesses are different.
Compared with the prior art, the technical scheme of the invention has the following advantages:
forming a plurality of fin parts on a substrate, etching part of the fin parts, sequentially and alternately forming a sacrificial layer and a lining layer on the surface of the etched fin parts, removing the sacrificial layer to form a channel, and subsequently forming a metal gate structure surrounding the lining layer on the etched fin parts when forming a metal gate structure on the substrate.
Meanwhile, the number of layers of the sacrificial layers formed on the surfaces of the fin portions after adjacent etching is different, meanwhile, the number of layers of the lining layers formed on the surfaces of the fin portions after adjacent etching is different, when the sacrificial layers are removed to form a channel, the metal gate structure is filled into the channel to form a fully-enclosed metal gate structure enclosing the lining layers on the fin portions, the number of the lining layers enclosed by the metal gate structure is different, and different heat dissipation effects are achieved by means of different densities of the lining layers on the adjacent fin portions and different intervals between the lining layers on the fin portions, so that the effect of balancing heat dissipation is achieved, and the self-heating effect of the semiconductor device can be eliminated in the use process, so that the use performance is improved.
Drawings
Fig. 1 to 5 are schematic structural views of a semiconductor device forming process in one embodiment;
fig. 6 to 11 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention;
fig. 12 to 24 are schematic structural views of a semiconductor device forming process in a second embodiment of the present invention;
fig. 25 to 33 are schematic structural views of a semiconductor device forming process in a third embodiment of the present invention.
Detailed Description
The method for forming the full-surrounding gate structure generally adopts the steps of forming a pseudo gate structure crossing the fin part on the substrate, removing part of the sacrificial layer in the fin part under the pseudo gate structure to form a channel, and then forming a gate medium with high dielectric constant and a metal gate, so that the full-surrounding gate structure is formed, but the usability of the semiconductor device formed at the moment is poor. This is because the fully-enclosed gate structure encloses all the fins, resulting in poor heat dissipation capability of the fully-enclosed gate structure, and thus, thermal noise is generated when the semiconductor device is used, which is easily caused by self-heating effect, and this thermal noise not only affects the performance and reliability of the circuit, but also may damage the formed circuit due to serious thermal problems, so that the use performance of the semiconductor device is reduced.
The specific semiconductor device is formed as follows:
referring to fig. 1, a substrate 1 is provided, a sacrificial layer 101 and a liner layer 102 are sequentially formed on the substrate 1, and the sacrificial layer 101 and the liner layer 102 are alternately formed on the substrate 1.
Referring to fig. 2, the liner layer 102 and the sacrificial layer 101 are etched until the substrate 1 is exposed, and a plurality of fins 2 are formed on the substrate 1 in a discrete arrangement.
Referring to fig. 3, a dummy gate structure 3 is formed on the substrate 1 across the fin 2.
Referring to fig. 4, the sacrificial layer 101 in the fin 2 covered by the dummy gate structure 3 is removed to form a channel 201.
Referring to fig. 5, the dummy gate structure 3 is removed, and a metal gate structure 4 is formed, the metal gate structure 4 surrounding the liner 102 on the fin 2.
The inventor finds that the fin parts are formed with the full-surrounding grid structure, and the heat dissipation capacity of the fin parts is larger than that of the full-surrounding grid structure, so that the single full-surrounding grid structure has poor heat dissipation capacity, and when the semiconductor device is formed, heat generated in the semiconductor is not easy to dissipate to generate thermal noise, so that the reliability of the use and the stability of the performance of the semiconductor device are affected.
The inventor researches and discovers that a full-surrounding grid structure is formed on one part of the fin part, and the fin part of the other part of the fin part does not fully surround the grid structure, and the heat dissipation capacity of the fin part is larger than that of the full-surrounding grid structure, so that heat generated in the semiconductor device can be timely dissipated in the use process of the semiconductor device, the self-heating effect generated in the semiconductor device is eliminated, and the stability of the performance of the semiconductor device is improved.
The inventor researches also find that the lining layers with different layers are formed on the adjacent fin parts, and the adjacent fin parts have different heat dissipation capacities when the full-surrounding grid structure is formed by utilizing the different densities of the lining layers on the adjacent fin parts, so that heat generated in the use process of the semiconductor device is effectively and timely dissipated, the self-heating effect formed in the semiconductor device is avoided, and the use performance of the semiconductor device is improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
First embodiment
Fig. 6 to 11 are schematic structural views of a semiconductor device forming process in the first embodiment of the present invention.
Referring first to fig. 6, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
Referring to fig. 7, at least one sacrificial layer 201 and at least one liner layer 202 are sequentially alternately formed on the substrate 200.
In this embodiment, two layers of the sacrificial layer 201 and two layers of the liner layer 202 are formed respectively; in other embodiments, the number of layers of the sacrificial layer 201 and the liner layer 202 may be set according to actual requirements.
Forming the sacrificial layer 201 on the substrate 200, and forming the liner layer 202 on the sacrificial layer 201; the sacrificial layer 201 and the liner layer 202 are alternately formed, that is, the sacrificial layer 201 is continuously formed on the liner layer 202, and the liner layer 202 is formed on the sacrificial layer 201 formed.
In this embodiment, the material of the sacrificial layer 201 is silicon germanium (SiGe); in other embodiments, the material of the sacrificial layer 201 may be one or more of silicon, germanium, and gallium arsenide.
In this embodiment, the material of the liner layer 202 is silicon; in other embodiments, the material of the second liner 202 may be one or more of germanium, silicon germanium, gallium arsenide.
In this embodiment, the sacrificial layer 201 and the liner layer 202 are formed on the substrate 200 by epitaxial growth.
In other embodiments, the sacrificial layer 201 and the liner layer 202 may be formed on the substrate 200 by ion doping or chemical vapor deposition.
In the present embodiment, a formationThe process of the sacrificial layer 201 employs a gas including hydrogen (H 2 ) Hydrogen chloride (HCl) gas, DCS gas, geH 4 Gas and B 2 H 6 A gas in which the hydrogen (H 2 ) The gas flow rate of the gas is 10-3000 sccm; the gas flow rate of the hydrogen chloride (HCl) gas is 10-200 sccm; the gas flow of the DCS gas is 20-2000 sccm; the GeH is 4 The gas flow rate of the gas is 10-500 sccm; the B is 2 H 6 The gas flow of the gas is 5-600 sccm; the temperature is 600-850 ℃, the pressure is 8-300 millitorr, and the time is 10 min-1 h.
In this embodiment, the process parameters for forming the liner 202 include the use of gases including hydrogen (H 2 ) Hydrogen chloride (HCl) gas, DCS gas, siH gas 4 Gas and B 2 H 6 A gas; wherein the hydrogen (H 2 ) The gas flow rate of the gas is 10-3000 sccm; the gas flow rate of the hydrogen chloride (HCl) gas is 10-250 sccm; the gas flow of the DCS gas is 20-2500 sccm; the SiH is 4 The gas flow rate of the gas is 10-700 sccm; the B is 2 H 6 The gas flow of the gas is 5-400 sccm; the pressure range is 8-300 millitorr; the temperature is 600-850 ℃.
Referring to fig. 8, the liner layer 202, the sacrificial layer 201, and a portion of the thickness of the substrate 200 are etched to form a plurality of discrete fins 300 on the substrate 200.
In this embodiment, 4 fins 300 are formed on the substrate 200; in other embodiments, the number of fin portions 300 may be determined according to actual needs.
In this embodiment, the 4 fins 300 are respectively a first fin 301, a second fin 302, a third fin 303, and a fourth fin 304.
In this embodiment, the process parameters of forming the fin 300 on the substrate 200 by using an etching process include using CF4 gas, hydrogen (H) 2 ) Oxygen (O) 2 )、CH 3 F gas and helium (He) are used as etching atmosphere, wherein the flow rate of the CF4 gas is 10-300 sccm, and the hydrogen (H) 2 ) Is 20-500 sccm of the oxygen (O) 2 ) The gas flow rate of the CH is 5-2005 sccm 3 The gas flow rate of the F gas is 60-800 sccm, the gas flow rate of the helium (He) gas is 60-200 sccm, and the reaction time is 5-150 s; the reaction temperature is 35-75 ℃.
Referring to fig. 9, a dummy gate structure 400 is formed on the substrate 200 across the fin 300.
In this embodiment, a hard mask layer is not formed on top of the dummy gate structure 400; in other embodiments, a hard mask layer may be formed on top of the dummy gate structure, so as to ensure that the quality of the top of the dummy gate structure 400 is protected during the subsequent process, and preparation is made for forming a metal gate structure with good surface quality.
In this embodiment, no sidewall is formed on the sidewall of the dummy gate structure 400; in other embodiments, a sidewall may also be formed on the sidewall of the dummy gate structure 400.
In this embodiment, the dummy gate structure 400 is formed by a conventional process.
Referring to fig. 10, the sacrificial layer 201 on the second fin portion 302 and the fourth fin portion 304 under the dummy gate structure 400 is removed, so as to form a channel 305.
In this embodiment, the sacrificial layer 201 on the second fin portion 302 and the fourth fin portion 304 is randomly removed; in other embodiments, the sacrificial layer 201 on the first fin 301 and the third fin 303 may also be removed.
In this embodiment, the sacrificial layer 201 on two fin portions of the fin portions 300 is removed; in other embodiments, the sacrificial layer 201 on 1 or 3 fin portions of the fin portions 300 may be removed, which only needs to ensure that the sacrificial layer on at least one fin portion is not removed.
In this embodiment, isotropic wet etching is used to remove the sacrificial layer 201; in other embodiments, the sacrificial layer 201 may also be removed by a dry etching process or the like.
In this embodiment, the wet etching solution used is: the temperature is 25-300 ℃, and the volume percentage of HCl gas is 20-90%.
In this embodiment, the wet etching solution has a good selectivity to silicon and silicon germanium, so that the morphology of silicon is not affected while silicon germanium is removed.
Referring to fig. 11, the dummy gate structure 400 is replaced with a metal gate structure 500, the metal gate structure 500 filling the channel 305.
In this embodiment, the dummy gate structure 400 is replaced with the metal gate structure 500 using conventional processes. The metal gate structure 500 includes a gate dielectric layer (not shown) and a metal gate that surrounds the liner 202.
In this embodiment, by forming the channel on a portion of the fin portion, when the metal gate structure is formed, a hybrid structure in which the liner layer of the fin portion is surrounded by the metal gate structure and the liner layer of the fin portion is not surrounded by the metal gate structure is formed, so that the metal gate structure in the hybrid structure can only surround a portion of the liner layer on the fin portion to form a fully-surrounded gate structure, and a portion of the liner layer is not surrounded by the metal gate structure.
A semiconductor device formed by the above method, comprising, a substrate 200; the fin portions 300 comprise a first fin portion 301, a second fin portion 302, a third fin portion 303 and a fourth fin portion 304, which are separately located on the substrate 200, wherein the first fin portion 301 and the third fin portion 303 are composed of a sacrificial layer 201 and a liner layer 202; the second fin 301 and the fourth fin 303 are composed of a liner layer 202 and a channel 305, wherein the sacrificial layer 201 is located on the substrate 200 and on the liner layer 202, the liner layer 202 is located on the substrate 200 or on the sacrificial layer 201, and the channel 305 is located in the second fin 301 and the fourth fin 303; a metal gate structure 500 is located on the substrate 200 and spans the fin 300.
Second embodiment
Fig. 12 to 24 are schematic structural views of a semiconductor device forming process in the second embodiment of the present invention.
Referring to fig. 12, a substrate 200 is provided.
In this embodiment, the material of the substrate 200 is monocrystalline silicon; in other embodiments, the substrate 200 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 200 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
Referring to fig. 13, at least one sacrificial layer 201 and at least one liner layer 202 are sequentially alternately formed on the substrate 200.
In this embodiment, two layers of the sacrificial layer 201 and two layers of the liner layer 202 are formed respectively; in other embodiments, the number of layers of the sacrificial layer 201 and the liner layer 202 may be set according to actual requirements.
In this embodiment, the process of forming the sacrificial layer 201 and the liner layer 202 is the same as in the first embodiment.
In this embodiment, the material of the sacrificial layer 201 is silicon germanium (SiGe); in other embodiments, the material of the sacrificial layer 201 may be one or more of silicon, germanium, and gallium arsenide.
In this embodiment, the material of the liner layer 202 is silicon; in other embodiments, the material of the second liner 202 may be one or more of germanium, silicon germanium, gallium arsenide.
Referring to fig. 14, the liner layer 202, the sacrificial layer 201, and a portion of the thickness of the substrate 200 are sequentially etched, and a plurality of fins 300 are formed on the substrate 200 in a discrete arrangement.
In this embodiment, the fin 300 includes a first fin 301 and a second fin 302, and the width of the first fin 301 is 2-3 times that of the second fin 302.
In this embodiment, the width direction is parallel to the surface of the substrate and perpendicular to the extending direction of the fin portion, and the length of the double arrow line in the figure indicates the width.
In this embodiment, the width of the first fin portion 301 and the width of the second fin portion 302 are different; in other embodiments, the width of the first fin 301 and the width of the second fin 302 may be the same.
In this embodiment, two first fin portions 301 and two second fin portions 302 are formed on the substrate 200; in other embodiments, different numbers of the first fins 301 and the second fins 302 may be formed.
In this embodiment, fin portions with two widths are formed on the substrate 200; in other embodiments, three or four equally different width fins may also be formed.
In this embodiment, the reason why the width of the first fin portion 301 is 2-3 times that of the second fin portion 302 is that the semiconductor device is easy to dissipate heat, and the self-heating effect is avoided; this is because the width of the liner layer 202 on the first fin portion 301 is greater than the width of the liner layer 202 on the second fin portion 302, the width of the liner layer surrounded by the metal gate structure is greater, and the heat dissipation capability of the formed semiconductor device is stronger; but the width of the liner surrounded by the metal gate structure cannot be too large, resulting in reduced performance of the resulting semiconductor device.
Referring to fig. 15, an isolation structure 600 is formed on the substrate 200, the isolation structure 600 covering a portion of the sidewalls of the fin 300.
In this embodiment, the isolation structure 600 is formed on the substrate 200; in other embodiments, the isolation structure 600 may not be formed on the substrate 200.
In this embodiment, the isolation structure 600 is a Shallow Trench Isolation (STI) structure; the isolation structure 600 is formed in a conventional manner.
Referring to fig. 16-17, a dummy gate structure 400 is formed on the substrate 200 across the fin 300.
FIG. 17 is a cross-sectional view of FIG. 16, wherein FIG. a is a cross-sectional view taken along line A-A; and B is a cross-sectional view taken along line B-B.
In this embodiment, a mask layer is not formed on top of the dummy gate structure 400; in other embodiments, a mask layer may be formed on top of the dummy gate structure 400 to protect the surface of the dummy gate structure from damage.
In this embodiment, before forming the dummy gate structure 400, an oxide layer (not shown) is further formed on the top and the sidewalls of the fin 300.
In this embodiment, the process of forming the dummy gate structure 400 is a conventional process, and no redundant description is necessary.
Referring to fig. 18, the sidewall 401 is formed on the sidewall of the dummy gate structure 400.
In this embodiment, the material of the sidewall 401 is silicon nitride; in other embodiments, the material of the sidewall 401 may be silicon oxide or silicon oxycarbide.
In this embodiment, the process of forming the sidewall 401 is the same as the conventional process.
Referring to fig. 19, with the side wall 401 and the dummy gate structure 400 as masks, the liner layer 202 and the sacrificial layer 201 on the first fin portion 301 and the second fin portion 302 are etched in sequence until the substrate 200 is exposed.
In this embodiment, the process of sequentially etching the liner layer 202 and the sacrificial layer 201 is the same as in the first embodiment.
Referring to fig. 20, the sacrificial layer 201 on the first fin 301 and the second fin 302 under the sidewall 401 is removed, and an inner sidewall 402 is formed on the sidewalls of the remaining sacrificial layer 201.
In this embodiment, the material of the inner wall 402 is also silicon nitride; in other embodiments, the material of the inner wall 402 may be silicon oxide or silicon carbide.
In this embodiment, the reason and advantage of forming the sidewall spacer 402 on the sidewall of the remaining sacrificial layer 201 are that: and when the metal gate structure is formed later, increasing the distance between the metal gate structure and the source drain, thereby reducing parasitic capacitance.
Referring to fig. 21, a portion of the sidewall 401 and a portion of the inner sidewall 402 are removed.
In this embodiment, the purpose of removing the partial thickness of the sidewall 401 and the partial thickness of the sidewall 402 is to expose the ends of the liner layer 202 on both sides of the sacrificial layer 201, so as to prepare for forming an epitaxial layer subsequently, surrounding both ends of the liner layer 202.
Referring to fig. 22, the sacrificial layer 201 on the first fin 301 under the dummy gate structure 400 is removed, and a channel 305 is formed.
In this embodiment, the sacrificial layer 201 on the first fin 301 is selectively removed, and a channel is formed to form a metal gate structure surrounding the liner layer.
In this embodiment, the process of removing the sacrificial layer 201 is the same as that in the first embodiment.
In this embodiment, the sacrificial layer 201 on the first fin 301 under the dummy gate structure 400 is removed, and before the channel 305 is formed, no epitaxial layer and no interlayer dielectric (ILD) are formed on the substrate 200 on both sides of the fin 300.
In other embodiments, before removing the sacrificial layer 201 on the fin 300 under the dummy gate structure 400 to form the channel 305, an epitaxial layer is further formed on the substrate 200 on both sides of the fin 300, the top of the epitaxial layer is level with the bottom of the dummy gate structure 400, and an interlayer dielectric (ILD) is formed on the epitaxial layer and the substrate, and the top of the interlayer dielectric (ILD) is level with the top of the dummy gate structure.
Referring to fig. 23, the dummy gate structure 400 is replaced with a metal gate structure 500.
On the first fin 301, the metal gate structure 500 fills the channel 305 and surrounds the liner 202, and such metal gate structure 500 maximizes the effective gate width, which facilitates improving the performance of the semiconductor device formed.
In this embodiment, the metal gate structure 500 includes a gate dielectric layer and a metal gate disposed on the gate dielectric layer.
Referring to fig. 24, an epitaxial layer 700 is formed surrounding both ends of the liner layer 202 on the first fin 301 and the second fin 302.
In this embodiment, the epitaxial layer 700 is formed for the purpose of: the fin structure is wrapped around the liner layer 202, and the control effect of the metal gate structure on the fin portion can be increased, so that the distance between the fin portion and the formed source drain can be increased, and the service performance of the semiconductor device is improved.
A semiconductor device formed by the above method, comprising, a substrate 200; the plurality of fin portions 300 are located on the substrate 200 and comprise a first fin portion 301 and a second fin portion 302, the first fin portion 301 is composed of a liner layer 202 and a channel 305, the second fin portion 302 is composed of the liner layer 202 and a sacrificial layer 201, and the sacrificial layer 201 is located on the substrate 200 and the liner layer 202; the liner layer 202 is located on the substrate 200 and on the sacrificial layer 201; the channel 305 is located in the first fin 301; an isolation structure 600, located on the substrate 200, covering a portion of the sidewalls of the fin 300; a metal gate structure 500 on the substrate 200 and crossing the first fin 301 and the second fin 302, wherein the metal gate structure 500 fills the channel 305 and surrounds the liner 202 on the first fin 301; a sidewall 401, located on the sidewall of the metal gate structure 500; an inner sidewall wall 402, which is located on the sidewall of the etched sacrificial layer 201 and on a portion of the sidewall of the metal gate structure 500; an epitaxial layer 700 is wrapped around the liner 202.
Third embodiment
Fig. 25 to 33 are schematic structural views of a forming process of forming a semiconductor device in a third embodiment of the present invention.
Referring to fig. 25, a substrate 200 is provided, and a number of fins 300 are formed on the substrate 200.
In this embodiment, 4 fins, namely, a first fin 301, a second fin 302, a third fin 303, and a fourth fin 304, are formed on the substrate 200.
In this embodiment, the substrate 200 is monocrystalline silicon; in other embodiments, the substrate 200 may also be polysilicon, silicon germanium, or the like.
In this embodiment, a fin material film is formed on the substrate 200, and a patterned layer (not shown) is formed on the fin material film; and etching the fin material film by taking the patterned layer as a mask to form the fin 300 on the substrate 200.
In this embodiment, a hard mask layer is not formed on top of the fin 300; in other embodiments, a hard mask layer may be formed on top of the fin 300 to protect the bottom of the fin from damage in subsequent processes.
Referring to fig. 26, a protection layer 800 is formed on the substrate 200 and on the sidewalls of the fin 300, wherein the top of the protection layer 800 is level with the top of the fin 300.
In this embodiment, the material of the protective layer 800 is silicon oxide; in other embodiments, the material of the protective layer 800 may be silicon nitride or silicon carbide.
In this embodiment, the protective layer 800 is formed by chemical vapor deposition; in other embodiments, the protective layer 800 may be formed by physical vapor deposition or atomic layer deposition.
In this embodiment, after the protection layer 800 is formed, a chemical mechanical polishing manner is adopted to make the top surface of the protection layer 800 flush with the top surface of the fin 300.
Referring to fig. 27, the fin 300 is etched at each interval to a partial thickness; first etching the first fin 301 and the third fin 303 with partial thickness.
In this embodiment, the first fin portion 301 with a partial thickness is etched and removed first; simultaneously etching the third fin 303 with partial thickness; in other embodiments, the second fin portion 302 may be etched to remove a portion of the thickness; and etching to remove part of the thickness of the fourth fin portion 304.
In this embodiment, dry etching is used to remove a portion of the thickness of the first fin portion 301 and a portion of the thickness of the third fin portion 303; in other embodiments, the first fin 301 with a partial thickness and the third fin 303 with a partial thickness may also be removed by wet etching.
Referring to fig. 28, at least one sacrificial layer 201 and at least one liner layer 202 are sequentially and alternately formed on the surfaces of the etched first fin 301 and the etched third fin 303.
In this embodiment, two layers of sacrificial layers 201 and two layers of liner layers 202 are sequentially and alternately formed on the surface of the etched first fin portion 301; in other embodiments, the number of layers of the sacrificial layer 201 and the liner layer 202 sequentially and alternately formed on the surface of the etched first fin portion 301 may be 1 layer, 3 layers, or 4 layers.
In this embodiment, two layers of sacrificial layers 201 and two layers of liner layers 202 are sequentially and alternately formed on the surface of the etched third fin portion 303; in other embodiments, the number of layers of the sacrificial layer 201 and the liner layer 202 sequentially and alternately formed on the surface of the etched third fin portion 303 may be 1 layer, 3 layers, or 4 layers.
In this embodiment, the sacrificial layer 201 and the liner layer 202 are formed by atomic layer deposition; in other embodiments, the sacrificial layer 201 and the liner layer 202 may also be formed by chemical deposition or physical deposition.
In this embodiment, the number of layers of the sacrificial layer 201 formed on the surfaces of the first fin portion 301 and the third fin portion 303 after the interval etching is the same; meanwhile, the number of layers 202 of the liner layer formed on the surfaces of the first fin portion 301 and the third fin portion 303 after the spacer etching is the same.
Referring to fig. 29, the second fin 302 and the fourth fin 304 having a partial thickness are etched away.
In this embodiment, the second fin portion 302 with a partial thickness and the fourth fin portion 304 with a partial thickness are removed by dry etching.
Referring to fig. 30, at least one sacrificial layer 201 and at least one liner layer 202 are sequentially and alternately formed on the surfaces of the etched second fin portion 302 and the etched fourth fin portion 304.
In this embodiment, a sacrificial layer 201 and a liner layer 202 are sequentially and alternately formed on the surface of the etched second fin portion 302 and the surface of the etched fourth fin portion 304.
In other embodiments, the number of layers of the sacrificial layer 201 and the liner layer 202 sequentially and alternately formed on the surface of the etched second fin portion 302 and the surface of the etched fourth fin portion 304 may be set according to actual needs.
The number of layers of the sacrificial layer 201 formed on the surface of the etched second fin portion 302 is different from the number of layers of the sacrificial layer 201 formed on the surfaces of the first fin portion 301 and the third fin portion 303;
the number of layers of the liner layer 202 formed on the surface of the etched second fin portion 302 is different from the number of layers of the liner layer 202 formed on the surfaces of the first fin portion 301 and the third fin portion 303.
Also, the number of layers of the sacrificial layer 201 formed on the surface of the etched third fin portion 303 is different from the number of layers of the sacrificial layer 201 formed on the surfaces of the second fin portion 302 and the fourth fin portion 304;
the number of layers of the liner layer 202 formed on the surface of the etched third fin portion 303 is different from the number of layers of the liner layer 202 formed on the surfaces of the second fin portion 302 and the fourth fin portion 304.
In this embodiment, the number of layers of the sacrificial layer formed on the surface of the fin portion after adjacent etching is 1-2, that is, the number of layers of the sacrificial layer 201 formed on the surface of the second fin portion 302 after etching is 1-2 different from the number of layers of the sacrificial layer 201 formed on the surfaces of the first fin portion 301 and the third fin portion 303.
In this embodiment, the number of layers of the liner layer formed on the surface of the fin portion after adjacent etching is 1-2, that is, the number of layers of the liner layer 202 formed on the surface of the second fin portion 302 after etching is 1-2 different from the number of layers of the liner layer 202 formed on the surfaces of the first fin portion 301 and the third fin portion 303.
Referring to fig. 31, a portion of the thickness of the protection layer 800 is removed, and the top of the protection layer 800 is flush with the top of the etched fin 300.
In this embodiment, the etching is used to remove a part of the thickness of the protective layer 800; in other embodiments, ashing or etching may be used to remove a portion of the thickness of the protective layer 800.
Referring to fig. 32, the sacrificial layer 201 is removed to form a via 305.
In this embodiment, the sacrificial layer 201 is removed by isotropic wet etching, and the wet etching solution used is: the temperature is 25-300 ℃, and the volume percentage of HCl gas is 20-90%.
Referring to fig. 33, a metal gate structure 500 is formed on the substrate 200, the metal gate structure 500 surrounding the liner 202.
In this embodiment, the metal gate structure 500 is a metal gate structure, and includes a gate dielectric layer (dielectric constant is greater than 3.9) and a metal gate layer on the gate dielectric layer.
A semiconductor device formed by the above method, comprising, a substrate 200; a fin 300 with a partial thickness, including a first fin 301, a second fin 302, a third fin 303, and a fourth fin 304 with a partial thickness, which are located on the substrate 200; the liner layers 202 are positioned on the fin portions 300 with partial thickness, and the layers of the liner layers 202 on the adjacent fin portions 300 with partial thickness are different; a channel 305 located on a portion of the thickness of the fin 300 and between liners 202 and between adjacent liners 202; a protective layer 800 on the substrate 200, the top of the protective layer being level with the top of the fin 300; the metal gate structure 500 is located on the substrate 200, across a portion of the thickness of the fin 300, fills the channel 305, and surrounds the liner 202.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate, and sequentially and alternately forming at least one sacrificial layer and at least one lining layer on the substrate; etching the lining layer, the sacrificial layer and the substrate with partial thickness, wherein a plurality of fin parts are formed on the substrate;
forming a pseudo gate structure crossing the fin part on the substrate;
removing part of the sacrificial layer on the fin parts under the pseudo gate structure to form a channel, wherein a part of each fin part consists of the sacrificial layer and the lining layer; and the other part of each fin part consists of the lining layer and the channel.
2. The method of forming a semiconductor device of claim 1, wherein a number of the fins comprises at least a first fin and a second fin.
3. The method of claim 2, wherein the width of the first fin is 2-3 times the width of the second fin, and the sacrificial layer on the first fin under the dummy gate structure is removed to form a channel.
4. The method of forming a semiconductor device of claim 1, further comprising, after removing the sacrificial layer, replacing the dummy gate structure with a metal gate structure, the metal gate structure filling the channel.
5. The method of claim 4, wherein after forming the dummy gate structure across the fin on the substrate, removing a portion of the sacrificial layer on the fin under the dummy gate structure, and before forming a channel, further comprising forming a sidewall on a sidewall of the dummy gate structure, and sequentially etching a portion of the liner layer and the sacrificial layer on the fin with the sidewall and the dummy gate structure as masks until the substrate is exposed.
6. The method of claim 5, wherein removing the sacrificial layer on the fin under the dummy gate structure until the substrate is exposed, and before forming a channel, further comprises removing the sacrificial layer on the fin under the sidewall, and forming an inner sidewall on the sidewall of the sacrificial layer.
7. The method of forming a semiconductor device of claim 6, wherein after replacing the dummy gate structure with a metal gate structure, further comprising forming an epitaxial layer comprising both ends of the liner layer on the etched fin.
8. The method of forming a semiconductor device of claim 1, wherein the material of the sacrificial layer comprises one or more of silicon, germanium, silicon germanium, gallium arsenide.
9. The method of forming a semiconductor device of claim 1, wherein the material of the liner layer comprises one or more of silicon, germanium, silicon germanium, gallium arsenide.
10. A semiconductor device formed by the method of any one of claims 1 to 9, comprising:
a substrate;
the fin parts are separately positioned on the substrate, and a part of each fin part consists of a sacrificial layer and a lining layer; another part of each fin part consists of a lining layer and a channel;
wherein: a sacrificial layer on the substrate and on the liner layer,
a liner layer on the sacrificial layer or the substrate,
a channel located in another portion of each of the fins;
and the dummy gate structure is positioned on the substrate and spans across the fin part.
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| CN109103262A (en) * | 2017-06-20 | 2018-12-28 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacturing method |
| CN109427779A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| US9842914B1 (en) * | 2016-08-19 | 2017-12-12 | International Business Machines Corporation | Nanosheet FET with wrap-around inner spacer |
| CN109103262A (en) * | 2017-06-20 | 2018-12-28 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its manufacturing method |
| CN109427779A (en) * | 2017-08-22 | 2019-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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