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CN113851535A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN113851535A
CN113851535A CN202010598335.3A CN202010598335A CN113851535A CN 113851535 A CN113851535 A CN 113851535A CN 202010598335 A CN202010598335 A CN 202010598335A CN 113851535 A CN113851535 A CN 113851535A
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China
Prior art keywords
layer
forming
fin
channel
channel layer
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Chinese (zh)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010598335.3A priority Critical patent/CN113851535A/en
Publication of CN113851535A publication Critical patent/CN113851535A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor device and a method of forming the same, wherein the semiconductor device comprises: a substrate; the fin parts comprise a plurality of channel layers along the normal direction of the surface of the substrate; a split layer located between at least one pair of adjacent fin portions, a gap being provided between the split layer and the channel layer; and the grid structure is positioned on the substrate, spans the plurality of fin parts and surrounds the channel layer. Because a gap is formed between the segmentation layer and the channel layer, after the grid structure crossing the fin part is formed on the substrate, the grid structure can surround the periphery of the channel layer, so that the control capability of the grid structure on the channel layer is enhanced, and the performance of the finally formed semiconductor device is improved.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
Metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most important components in modern integrated circuits, and the basic structure of a MOSFET includes: a semiconductor substrate; a gate structure located on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; and the source and drain doped regions are positioned in the semiconductor substrate at two sides of the grid structure.
With the development of semiconductor technology, the conventional planar MOSFET has a weak ability to control channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar MOSFET, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
With the further development of semiconductor technology, the conventional finfet has a limitation in further increasing the operating current. Specifically, only the region near the top surface and the sidewall in the fin is used as a channel region, so that the volume of the fin used as the channel region is small, which limits the increase of the operating current of the finfet. Therefore, a MOSFET of a (gate all around) structure is proposed, so that the volume for serving as a channel region is increased, further increasing the operating current of the MOSFET of the GAA structure.
However, the electrical performance of the GAA MOSFET in the prior art still needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which can effectively improve the performance of the finally formed semiconductor device.
To solve the above problems, the present invention provides a semiconductor device comprising: a substrate; the fin parts comprise a plurality of channel layers along the normal direction of the surface of the substrate; a split layer located between at least one pair of adjacent fin portions, a gap being provided between the split layer and the channel layer; and the grid structure is positioned on the substrate, spans the plurality of fin parts and surrounds the channel layer.
Optionally, the gap between the partition layer and the channel layer is 0nm to 20nm in size.
Optionally, the top surface of the dividing layer is higher than the top surface of the fin portion.
Optionally, the material of the partition layer is a dielectric material.
Correspondingly, the invention also provides a method for forming the semiconductor device, which comprises the following steps: providing a substrate; forming a plurality of fin parts which are distributed in a discrete mode on the substrate, wherein an isolation groove is formed between every two adjacent fin parts, each fin part comprises a plurality of fin part sacrificial layers which are overlapped along the direction vertical to the surface of the substrate, and an initial channel layer located between every two adjacent fin part sacrificial layers; etching to remove part of the initial channel layer on the side wall of the isolation groove to form a channel layer; forming a sacrificial layer on a sidewall of the channel layer; forming a partition layer in at least one of the isolation trenches; and etching to remove the sacrificial layer, and forming a gap between the segmentation layer and the channel layer.
Optionally, before the step of removing the sacrificial layer by etching and forming a gap between the partition layer and the channel layer, the method further includes: and forming a pseudo-gate structure crossing the plurality of fin parts on the substrate.
Optionally, after the dummy gate structure is formed, the sacrificial layer is removed by etching, and the step of forming a gap between the partition layer and the channel layer includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure; removing the pseudo gate structure, and forming a gate opening in the dielectric layer; and forming a gate groove between the adjacent channel layers except the fin sacrificial layer and the sacrificial layer exposed by the gate opening, and forming a gap between the partition layer and the channel layers.
Optionally, the gap size between the partition layer and the channel layer is 0nm to 20 nm.
Optionally, after forming a gap between the partition layer and the channel layer, a gate structure is formed in the gate opening and the gate trench, and the gate structure surrounds the channel layer.
Optionally, the material of the partition layer is a dielectric material.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the semiconductor device, the gap is formed between the dividing layer and the channel layer, and after the grid structure crossing the fin part is formed on the substrate, the grid structure can surround the periphery of the channel layer; on the other hand, due to the existence of the gap, impurities existing between the gate structure and the channel layer are reduced, and therefore the performance of the finally formed semiconductor device is improved.
In the forming method of the invention, part of the initial channel layer on the side wall of the isolation groove is removed by etching to form a channel layer; forming a sacrificial layer on the side wall of the channel layer, forming a partition layer in at least one isolation groove, and removing the sacrificial layer to form a gap between the partition layer and the channel layer, so that when a gate structure is formed, the gap between the partition layer and the channel layer can also form the gate structure, so that the formed gate structure can surround the peripheral side wall of the channel layer, the control capability of the gate structure on the channel layer is enhanced, and the electrical performance of the formed semiconductor device is improved; and because the sacrificial layer is formed on the side wall of the channel layer, before the grid structure is formed, in the process of removing the fin sacrificial layer and the sacrificial layer, the fin sacrificial layer is convenient to remove, the difficulty of removing the fin sacrificial layer is reduced, and impurities between the grid structure and the channel layer are reduced.
Drawings
Fig. 1 to 3 are schematic structural views of a semiconductor device;
fig. 4 to 17 are schematic structural diagrams of steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
At present, as the size of the GAA MOSFET is reduced, a Forksheet GAA MOSFET is introduced in the process of cutting the gate structure to form a required semiconductor device, but the electrical performance of the GAA MOSFET with the structure still needs to be improved. The following detailed description will be made in conjunction with the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided; forming a plurality of fin structures 101 arranged in parallel along a first direction on the substrate 100, wherein an isolation trench (not marked) is arranged between every two adjacent fin structures 101, and each fin structure 101 comprises a plurality of fin sacrificial layers 103 overlapped along the normal direction of the surface of the substrate 100 and a channel layer 104 positioned between every two adjacent fin sacrificial layers 103; and forming a dummy gate structure 105 crossing the adjacent fin structure 101 on the substrate 100 by using an isolation structure 106 located on the substrate 100, wherein the dummy gate structure 105 extends along a second direction, and the first direction is perpendicular to the second direction.
Referring to fig. 2, a portion of the dummy gate structure 105 is removed to expose the isolation trench; a partition layer 102 is formed within the isolation trench.
Referring to fig. 3, after the partition layer 102 is formed, the dummy gate structure 105 and the fin sacrificial layer 103 are removed, a gate opening and a gate trench are formed, and a gate structure 107 is formed in the gate opening and the gate trench.
The inventor finds that in the above embodiment, the formed dividing layer 102 covers a sidewall of the fin sacrificial layer 103, and in a subsequent process, the fin sacrificial layer 103 and the dummy gate structure 105 need to be removed by a wet etching process to form a gate trench and a gate opening. However, since one sidewall of the fin sacrificial layer 103 is covered by the dividing layer 102, the etching solution can only be removed by etching from the other sidewall of the fin sacrificial layer 103 during the removal of the fin sacrificial layer 103, which not only affects the etching efficiency, but also causes incomplete removal of the fin sacrificial layer 103 at the corners of the channel layer 104 and the dividing layer 102 and the fin sacrificial layer 103 covered by the dividing layer 102; in addition, after the gate trench is formed, a gate structure needs to be formed in the gate trench, the gate structure surrounding the channel layer 104. However, since one side of the gate trench is covered and shielded by the partition layer 102, during the process of forming the gate structure, the deposition of the gate structure can only be performed from the other side of the gate trench, which not only affects the forming efficiency, but also causes the final formed gate structure to have low compactness. The additionally formed gate structure can only surround the channel layer 104 on three sides, so that the area of a channel region formed by the gate structure surrounding the channel layer 104 is reduced, and the performance of a finally formed semiconductor device is further influenced; in addition, in the embodiment, after the dummy gate structure is formed, the dummy gate structure is etched to expose the isolation trenches between the fin portions, then the partition layers are formed in the isolation trenches, the isolation trenches between the fin portions are exposed when the dummy gate structure is etched, and in the process of forming the partition layers in the isolation trenches, the problem of misalignment of a photomask easily exists, so that the formed partition layers are easily overlapped with the fin portions, and the distance between the partition layers and the fin portions is difficult to control.
The inventor finds that before the cutting layer is formed, part of the initial channel layer on the side wall of the isolation groove is etched and removed to form the channel layer, so that the size of the channel layer is shortened, the sacrificial layer is formed on the side wall of the channel layer, and the cutting layer is formed in the isolation groove, so that the difficulty of subsequently removing the fin sacrificial layer is reduced, and the fin sacrificial layer is easier to remove; meanwhile, the formed gate structure can surround the periphery of the channel layer, so that the control capability of the gate structure on the channel layer is enhanced, and the electrical performance of the finally formed semiconductor device is enhanced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 17 are schematic structural diagrams of a process of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided.
In this embodiment, the substrate 200 is made of monocrystalline silicon.
In other embodiments, the substrate 200 may also be polysilicon or amorphous silicon. The substrate 200 may also be made of germanium, silicon germanium, gallium arsenide, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or other semiconductor materials.
Referring to fig. 5 and fig. 6, fig. 6 is a schematic cross-sectional view taken along line a-a in fig. 5, a plurality of fin portions arranged in parallel along a first direction Y are formed on the substrate 200, an isolation trench 201 is formed between adjacent fin portions, and the fin portions include a plurality of fin portion sacrificial layers 202 overlapped along a normal direction of a surface of the substrate 200 and an initial channel layer 203 located between two adjacent fin portion sacrificial layers 202.
In this embodiment, the number of the fin portions is three; the number of the fin sacrificial layers 202 is three; the number of layers of the initial channel layer 203 is three.
In this embodiment, the method for forming the fin portion includes: forming a fin material film (not shown) on the substrate 200, wherein the fin material film comprises a plurality of fin sacrificial material films overlapped along the surface normal direction of the substrate 200 and an initial channel material film positioned between two adjacent fin sacrificial material films; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by using the patterned layer as a mask until the fin material film is exposed out of the surface of the substrate 200 to form a fin part, wherein the fin part comprises a plurality of layers of fin part sacrificial layers 202 overlapped along the normal direction of the surface of the substrate 200 and an initial channel layer 203 positioned between two adjacent layers of fin part sacrificial layers 202.
In this embodiment, the fin sacrificial layer 202 and the initial channel layer 203 are made of different materials. The purpose of the method is to remove the fin sacrificial layer 202 when a gate structure is formed subsequently, so that the fin sacrificial layer 202 and the initial channel layer 203 which are made of different materials have a larger etching selection ratio, and damage to the initial channel layer 203 in the process of removing the fin sacrificial layer 202 is reduced.
In this embodiment, the fin sacrificial layer 202 is made of silicon germanium; the material of the initial channel layer 203 is monocrystalline silicon.
In this embodiment, after the etching the fin material film to form the fin, the method further includes: etching the substrate 200 with partial thickness by using the fin part as a mask; an isolation structure 204 is formed on the substrate 200, and a top surface of the isolation structure 204 is lower than a top surface of the substrate 200.
In this embodiment, the isolation structure 204 is made of silicon nitride.
In other embodiments, the material of the isolation structure 204 may further include one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.
In this embodiment, the isolation structure 204 functions to form electrical isolation.
In this embodiment, before forming the fin portion, the method further includes: an initial hard mask is formed on the fin material film (not shown), and a hard mask layer 205 is formed on the top surface of the fin when the fin material film is subsequently etched to form the fin.
In this embodiment, the hard mask layer 205 is made of silicon nitride; in other embodiments, the material of the hard mask layer 205 may also be at least one of silicon oxide, silicon carbide, or silicon oxynitride.
In this embodiment, the hard mask layer 205 serves to protect the top surface of the fin, so that the top surface of the fin can be ensured to have good formation quality in the subsequent process.
Referring to fig. 7, fig. 7 and fig. 6 are shown in the same view direction, and a portion of the initial channel layer 203 on the sidewall of the isolation trench 201 is etched away to form the channel layer 206.
In this embodiment, after etching to remove a portion of the initial channel layer 203 on the sidewall of the isolation trench 201 and form the channel layer 206, grooves 207 are formed on both sides of the channel layer 206.
In this embodiment, the process of etching the initial channel layer 203 is a wet etching process, and tetramethylammonium hydroxide (TMAH) is used as an etching solution in the wet etching process, so that the fin sacrificial layer 202 is not affected during the process of etching the initial channel layer 203 with a certain thickness.
In this embodiment, the purpose of etching the initial channel layer 203 to form the channel layer 206 is to increase the distance between the sidewall of the channel layer 206 and the sidewall of the isolation trench 201, so as to prepare for a subsequent gate structure to surround the peripheral sidewall of the channel layer 206.
In this embodiment, the initial channel layer 203 is etched to form the channel layer 206, and when the split layer is formed subsequently, the sidewall of the split layer does not cling to the sidewall of the channel layer 206, so that the distance between the split layer and the fin portion is also easy to control.
Referring to fig. 8, fig. 8 and fig. 7, a sacrificial layer 208 is formed on the sidewall of the channel layer 206.
In the present embodiment, the sacrificial layer 208 is formed in the groove 207.
In this embodiment, the material of the sacrificial layer 208 is silicon germanium; in other embodiments, the material of the sacrificial layer 208 may also be at least one of silicon germanium, amorphous silicon, amorphous germanium, or an oxide of silicon.
In this embodiment, the process of forming the sacrificial layer 208 includes: forming an initial sacrificial layer on the surface of the isolation structure 204, the sidewall of the fin sacrificial layer 202, the sidewall of the channel layer 206, and the sidewall and the top of the hard mask layer 205, etching back the initial sacrificial layer, and forming the sacrificial layer 208 in the groove 207.
In this embodiment, the material of the sacrificial layer 208 is also silicon germanium, which is the same as the material of the fin sacrificial layer 202, so as to facilitate a simplified process, and improve the rate and quality of the subsequent removal of the sacrificial layer 208 and the fin sacrificial layer 202, thereby improving the rate and quality of forming a semiconductor device.
In this embodiment, the process of forming the initial sacrificial layer is a chemical vapor deposition process; in other embodiments, at least one of an atomic layer deposition process, a physical vapor deposition process, and the like may also be employed.
Referring to fig. 9, fig. 9 and fig. 8 are shown in the same view direction, and a partition layer 209 is formed in at least one of the isolation trenches 201.
In this embodiment, the material of the dividing layer 209 is a dielectric material, and specifically may be one or a combination of a plurality of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon carbonitride (SiCBN).
In the present embodiment, the process of forming the dividing layer 209 is an atomic layer deposition process; in other embodiments, the process of forming the dividing layer 209 may also include a chemical vapor deposition process.
In this embodiment, the step of forming the dividing layer 209 includes: an initial dividing layer is formed in the isolation trench 201 and on the hard mask layer 205, the initial dividing layer is planarized until the top surface of the hard mask layer 205 is exposed, and the dividing layer 209 is formed in the isolation trench 201.
In this embodiment, the reason why the atomic layer deposition process is used to form the dividing layer is that the atomic layer deposition process can form the dividing layer 209 with a better coverage gradient, and can fill the isolation trench 201 with a higher degree, thereby improving the quality of the formed dividing layer 209.
In this embodiment, the dividing layer 209 is formed in only one of the isolation trenches 201, and the dividing layer 209 is subsequently used for dividing the gate structure, so as to realize the gate cut at the dividing layer 209.
In other embodiments, the dividing layer 209 may be formed in a plurality of isolation trenches 201 at the same time, which is designed according to the actual circuit design requirement.
In this embodiment, before the dummy gate structure is formed, the dividing layer 209 is formed in the isolation trench 201, so that there is no misalignment problem during photolithography, and the distance between the dividing layer 209 and the fin portion can be well controlled.
Referring to fig. 10 and 11, fig. 11 is a schematic cross-sectional view taken along line B-B in fig. 10, referring to fig. 10, before the sacrificial layer 208 is removed by etching, and a gap is formed between the partition layer 209 and the channel layer 206, the dummy gate structure 210 crossing several fins is formed on the substrate 200, the dummy gate structure 210 extends along a second direction X, and the first direction Y is perpendicular to the second direction X.
In this embodiment, the dummy gate structure 210 includes: the semiconductor structure comprises a pseudo gate dielectric layer 211 positioned on the fin portion, a pseudo gate layer 212 positioned on the pseudo gate dielectric layer 211, a protective layer 213 positioned on the pseudo gate layer 212, and a side wall 214 positioned on the side wall of the pseudo gate layer 212 and the protective layer 213.
In this embodiment, the material of the dummy gate layer 212 is polysilicon; in other embodiments, the material of the dummy gate layer 212 may also be amorphous silicon.
In this embodiment, the material of the protection layer 213 is silicon nitride; in other embodiments, the material of the protective layer may also use silicon oxide.
The method for forming the side wall 214 includes: forming a side wall material layer (not shown) on the top surface of the dummy gate dielectric layer 211, the side wall of the dummy gate layer 212, the side wall of the protection layer 213 and the top surface; and etching back the side wall material layer until the protective layer 213 and the top surface of the gate dielectric layer 211 are exposed, thereby forming the side wall 214.
The forming process of the side wall material layer is one or combination of a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the forming process of the side wall material layer adopts an atomic layer deposition process.
The material of the sidewall 214 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride or silicon oxycarbonitride. In this embodiment, the sidewall spacers 214 are made of silicon nitride.
In this embodiment, the sidewall spacers 214 are used to define the position of the subsequent source/drain doping layer.
In this embodiment, the hard mask layer 205 is removed before the dummy gate structure 210 is formed.
Referring to fig. 12 and 13, fig. 13 is a schematic cross-sectional view taken along line C-C in fig. 12, after the dummy gate structure 210 is formed, the fin portions on both sides of the dummy gate structure 210 are etched, a source-drain groove (not shown) is formed in the fin portion, and a source-drain doping layer 215 is formed in the source-drain groove.
In this embodiment, the source-drain grooves function to provide a space for the source-drain doped layer to be formed subsequently.
The process for etching the fin portion comprises the following steps: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the process of etching the fin portion is an anisotropic dry etching process, and parameters of the dry etching process include: the adopted etching gas comprises HBr and Ar, wherein the gas flow of HBr is 10 sccm-1000 sccm, and the gas flow of Ar is 10 sccm-1000 sccm.
In this embodiment, the forming process of the source-drain doping layer 215 includes an epitaxial growth process; the process of doping the source and drain ions in the source and drain doping layer 215 includes an in-situ doping process.
When the semiconductor structure is a P-type device, the source-drain doping layer 215 is made of the following materials: silicon, germanium, or silicon germanium; the source and drain ions are P-type ions and comprise boron ions and BF2-Ions or indium ions; when the semiconductor structure is an N-type device, the source-drain doping layer 215 is made of the following materials: silicon, gallium arsenide, or indium gallium arsenide; the source and drain ions are N-type ions and comprise phosphorus ions or arsenic ions.
In this embodiment, before the source-drain doping layer 215 is formed, a portion of the fin sacrificial layer 202 on the sidewall of the source-drain groove is etched, a blocking layer 216 is formed on the sidewall of the fin sacrificial layer after etching, and the blocking layer 216 is used to isolate a subsequently formed gate structure from the source-drain doping layer 215, so as to prevent punch-through between the gate structure and the source-drain doping layer 215.
After the dummy gate structure 210 is formed, the sacrificial layer 208 is removed by etching, and a gap is formed between the partition layer 209 and the channel layer 206, please refer to fig. 14 to 16.
Referring to fig. 14, the view directions of fig. 14 and fig. 13 are the same, after the source-drain doping layer 215 is formed, a dielectric layer 217 is formed on the substrate 200 and on the isolation structure 204, and the dielectric layer 217 covers the sidewall of the dummy gate structure 210.
In this embodiment, the dielectric layer 217 is located on the sidewall of the sidewall spacer 214 and exposes the top surface of the protection layer 213.
In this embodiment, the dielectric layer 217 is specifically formed on the isolation structure 204, and the dielectric layer 217 further covers the source-drain doping layer 215.
In this embodiment, the method for forming the dielectric layer 217 includes: forming an initial dielectric layer (not shown) on the substrate 200 and on the isolation structure 204, the initial dielectric layer covering the top surface and the sidewall surface of the protection layer 213; planarizing the initial dielectric layer until the top surface of the passivation layer 213 is exposed, forming the dielectric layer 217.
In this embodiment, the dielectric layer 217 is made of silicon oxide.
Referring to fig. 15, the view directions of fig. 15 and fig. 14 are the same, the dummy gate structure 210 is removed, and a gate opening 218 is formed in the dielectric layer 217.
In this embodiment, the process of removing the dummy gate structure 210 is a wet etching process, and specifically, tetramethylammonium hydroxide (TMAH) is used as an etching solution.
In this embodiment, the dummy gate structure 210 is removed in preparation for the subsequent formation of a gate structure.
In this embodiment, the protection layer 213, the dummy gate layer 212 and the dummy gate dielectric layer at the bottom of the protection layer 213 are removed.
Referring to fig. 16, fig. 16 and fig. 11, the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 are removed, a gate trench 219 is formed between the adjacent channel layers 206, and a gap 220 is formed between the partition layer 209 and the channel layer 206.
In the present embodiment, the gap 220 is formed between the partition layer 209 and the channel layer 206, so that the channel layer 206 on the sidewall of the partition layer 209 can be completely surrounded by the formed gate structure when the gate structure is formed later, thereby improving the control effect of the gate structure on the channel layer 206.
In the present embodiment, the size of the gap 220 between the partition layer 209 and the channel layer 206 is 0nm to 20 nm; when the size of the gap 220 is smaller than 0nm, the formed gap is too small, and when a gate structure is formed subsequently, the gate structure does not have enough filling space, so that the gate structure cannot be well surrounded on the peripheral surface of the channel layer 206, the control capability of the gate structure on the channel layer cannot be improved, and in the process of removing the fin sacrificial layer, because the gap 220 is too small, a residual fin sacrificial layer is easily left between the partition layer 209 and the channel layer 206; when the size of the gap 200 is larger than 20nm, although a good-quality gate structure may be formed on the peripheral sidewall of the channel layer 206, and the fin sacrificial layer between the partition layer 209 and the channel layer 206 is easily removed, the size of the channel layer 206 is too small, which may easily cause a short channel effect and reduce the electrical performance of the semiconductor device.
In this embodiment, the most preferable size of the gap 220 is 2nm to 5nm, because as the size of the semiconductor device is smaller and is continuously developed toward the optimized performance, the most preferable size of the gap 220 is 2nm to 5nm, which not only can ensure that the formed gate structure can surround the peripheral side of the channel layer, improve the control capability of the gate structure on the channel layer, but also ensure that the fin sacrificial layer left between the partition layer and the channel layer has less residue, thereby facilitating the removal of the fin sacrificial layer, and ensuring that the length of the gate structure is not too long, thereby facilitating the improvement of the integration level and the electrical performance of the semiconductor device.
In this embodiment, since the fin sacrificial layer 202 and the sacrificial layer 208 are made of the same material, they can be removed in one etching process, thereby reducing the number of processes and shortening the production cycle.
In this implementation, the process of removing the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 is a wet etching process.
In other embodiments, the removal of the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 may also be performed by a dry etching process.
In this embodiment, the reason why the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218 are removed by using a wet etching process is that the wet etching process has a high etching selectivity, and in the process of removing the fin sacrificial layer 202 and the sacrificial layer 208 exposed by the gate opening 218, the surface of the channel layer 206 may be hardly damaged or damaged a little, so that the channel layer 206 can be ensured to have good surface quality, which is beneficial to forming a high-quality semiconductor device.
In this embodiment, the parameters of the wet etching process include: HCl gas with the temperature of 25-300 ℃ and the volume percentage of 20-90 percent.
In this embodiment, since the sidewall of the partition layer 209 is not tightly attached to the channel layer 206 any more but tightly attached to the sacrificial layer 208, in the process of removing the fin sacrificial layer 202, the etching solution may simultaneously etch and remove the sidewalls of the fin sacrificial layer 202 from both sides, so as to improve the etching efficiency of removing the fin sacrificial layer 202 on one hand, and on the other hand, the problem of incomplete removal of the fin sacrificial layer 202 and the fin sacrificial layer 202 covered by the partition layer 209 no longer exist at the corners of the channel layer 206 and the partition layer 209 on the other hand, thereby improving the quality and efficiency of removing the fin sacrificial layer 202.
Referring to fig. 17, a gate structure 221 is formed in the gate opening 218 and the gate trench 219, and the gate structure 221 surrounds the channel layer 206.
In the present embodiment, due to the gap 220 between the partition layer 209 and the channel layer 206, the gate structure 221 formed around the partition layer 209 can surround the peripheral sidewall of the channel layer 206, instead of the conventional gate structure 221 around the partition layer 209 can surround only three sides of the channel layer 206, so that the area of the channel region formed by the gate structure 221 surrounding the channel layer 206 is increased, the controllability of the gate structure 221 on the channel layer 206 is enhanced, and the electrical performance of the finally formed semiconductor device is improved.
In this embodiment, the gate structure 221 includes a gate dielectric layer 222 and a gate electrode layer 223 on the gate dielectric layer 222.
In this embodiment, the gate dielectric layer 222 is a high-k dielectric material (dielectric coefficient greater than 3.9); the high-k dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.
The material of the gate electrode layer 223 is metal, and the metal material includes one or more of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.
Correspondingly, the invention also provides a semiconductor device, which comprises a substrate 200; a plurality of fins including a plurality of channel layers 206 along a normal direction of a surface of the substrate 200; a split layer 209 located between at least one pair of adjacent fins, the split layer 209 and the channel layer 206 having a gap 220 therebetween; a gate structure 221 on the substrate 200 and spanning over the fins, and surrounding the channel layer 206.
In this embodiment, a gap 220 is formed between the partition layer 209 and the channel layer 206, the gate structure 221 can be filled in the gap 220 to form a structure that surrounds the channel layer 206 completely, so as to increase the surface area of the channel layer 206 surrounded by the gate structure 221, thereby enhancing the controllability of the gate structure 221 on the channel layer 206 and enhancing the electrical performance of the formed semiconductor device; and due to the existence of the gap 220, impurities (i.e., residual fin sacrificial layers) existing between the gate structure 221 and the channel layer 206 are reduced, so that the performance of the finally formed semiconductor device is improved.
The gap 220 between the partition layer 209 and the channel layer 206 is 0nm to 20nm in size; when the size of the gap 220 is smaller than 0nm, the formed gap is too small, and when a gate structure is formed subsequently, the gate structure does not have enough filling space, so that the gate structure cannot be well surrounded on the peripheral surface of the channel layer 206, the control capability of the gate structure on the channel layer cannot be improved, and in the process of removing the fin sacrificial layer, because the gap 220 is too small, a residual fin sacrificial layer is easily left between the partition layer 209 and the channel layer 206; when the size of the gap 220 is larger than 20nm, although a good-quality gate structure may be formed on the peripheral sidewall of the channel layer 206 and the fin sacrificial layer between the partition layer 209 and the channel layer 206 is easily removed, the size of the channel layer 206 is too small, which may easily cause a short channel effect and reduce the electrical performance of the semiconductor device.
In this embodiment, the most preferable size of the gap 220 is 2nm to 5nm, because as the size of the semiconductor device is smaller and is continuously developed toward the optimized performance, the most preferable size of the gap 220 is 2nm to 5nm, which not only can ensure that the formed gate structure can surround the peripheral side of the channel layer, improve the control capability of the gate structure on the channel layer, but also ensure that the fin sacrificial layer left between the partition layer and the channel layer has less residue, thereby facilitating the removal of the fin sacrificial layer, and ensuring that the length of the gate structure is not too long, thereby facilitating the improvement of the integration level and the electrical performance of the semiconductor device.
The top surface of the dividing layer 209 is higher than the top surface of the fin portion, and the dividing layer 209 is subsequently used for dividing the gate structure, so that the gate structure is cut at the dividing layer 209 (gate cut).
In this embodiment, the material of the partition layer 209 is a dielectric material, which includes: silicon oxide, silicon oxynitride, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boride (SiCBN), and the like.
An isolation structure 204 is located on the substrate 200.
In this embodiment, the isolation structure 204 is made of silicon nitride.
In other embodiments, the material of the isolation structure 204 may further include one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon carbonitride boronitride (SiCBN), and the like.
In this embodiment, the isolation structure 204 functions to form electrical isolation.
Further comprising: and the source-drain doping layer 215 is positioned in the fin parts at two sides of the gate structure 221.
Further comprising: and the blocking layer 216 is positioned between the gate structure 221 and the source-drain doping layer 215, and is used for isolating the gate structure 221 from the source-drain doping layer 215 and preventing punch-through between the gate structure 221 and the source-drain doping layer 215.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
the fin parts comprise a plurality of channel layers along the normal direction of the surface of the substrate;
a split layer located between at least one pair of adjacent fin portions, a gap being provided between the split layer and the channel layer;
and the grid structure is positioned on the substrate, spans the plurality of fin parts and surrounds the channel layer.
2. The semiconductor device according to claim 1, wherein the gap size between the partition layer and the channel layer is 0nm to 20 nm.
3. The semiconductor device of claim 1, wherein a top surface of the dividing layer is higher than a top surface of the fin.
4. The semiconductor device according to claim 1, wherein a material of the partition layer is a dielectric material.
5. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a plurality of fin parts which are distributed in a discrete mode on the substrate, wherein an isolation groove is formed between every two adjacent fin parts, each fin part comprises a plurality of fin part sacrificial layers which are overlapped along the direction vertical to the surface of the substrate, and an initial channel layer located between every two adjacent fin part sacrificial layers;
etching to remove part of the initial channel layer on the side wall of the isolation groove to form a channel layer;
forming a sacrificial layer on a sidewall of the channel layer;
forming a partition layer in at least one of the isolation trenches;
and etching to remove the sacrificial layer, and forming a gap between the segmentation layer and the channel layer.
6. The method of forming a semiconductor device according to claim 5, wherein before the etching to remove the sacrifice layer and form a gap between the partition layer and the channel layer, further comprising: and forming a pseudo-gate structure crossing the plurality of fin parts on the substrate.
7. The method for forming a semiconductor device according to claim 6, wherein after the dummy gate structure is formed, the sacrificial layer is removed by etching, and the step of forming a gap between the partition layer and the channel layer includes:
forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure;
removing the pseudo gate structure, and forming a gate opening in the dielectric layer;
and removing the fin sacrificial layer and the sacrificial layer exposed by the gate opening, forming a gate groove between the adjacent channel layers, and forming a gap between the partition layer and the channel layers.
8. The method for forming a semiconductor device according to claim 5, wherein the gap size between the partition layer and the channel layer is 0nm to 20 nm.
9. The method of forming a semiconductor device according to claim 7, wherein after forming a gap between the partition layer and the channel layer, a gate structure is formed in the gate opening and the gate groove, the gate structure surrounding the channel layer.
10. The method for forming a semiconductor device according to claim 5, wherein a material of the dividing layer is a dielectric material.
CN202010598335.3A 2020-06-28 2020-06-28 Semiconductor device and method of forming the same Pending CN113851535A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504616A (en) * 2023-06-29 2023-07-28 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190067434A1 (en) * 2017-08-22 2019-02-28 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US20190067447A1 (en) * 2017-08-22 2019-02-28 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
CN110021528A (en) * 2018-01-10 2019-07-16 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN110246806A (en) * 2019-06-11 2019-09-17 中国科学院微电子研究所 Stack ring grid nanometer sheet cmos device structure and its manufacturing method
CN110277316A (en) * 2018-03-13 2019-09-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20200152780A1 (en) * 2018-11-12 2020-05-14 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof
CN111223779A (en) * 2018-11-23 2020-06-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN113555285A (en) * 2020-04-23 2021-10-26 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190067434A1 (en) * 2017-08-22 2019-02-28 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
US20190067447A1 (en) * 2017-08-22 2019-02-28 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method thereof
CN110021528A (en) * 2018-01-10 2019-07-16 中芯国际集成电路制造(上海)有限公司 Semiconductor devices and forming method thereof
CN110277316A (en) * 2018-03-13 2019-09-24 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
US20200152780A1 (en) * 2018-11-12 2020-05-14 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor device and fabrication method thereof
CN111180513A (en) * 2018-11-12 2020-05-19 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same
CN111223779A (en) * 2018-11-23 2020-06-02 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN110246806A (en) * 2019-06-11 2019-09-17 中国科学院微电子研究所 Stack ring grid nanometer sheet cmos device structure and its manufacturing method
CN113555285A (en) * 2020-04-23 2021-10-26 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116504616A (en) * 2023-06-29 2023-07-28 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device
CN116504616B (en) * 2023-06-29 2023-11-14 北京北方华创微电子装备有限公司 Method for manufacturing semiconductor device

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