CN111796456A - Back sheet and method for producing back sheet - Google Patents
Back sheet and method for producing back sheet Download PDFInfo
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- CN111796456A CN111796456A CN202010654794.9A CN202010654794A CN111796456A CN 111796456 A CN111796456 A CN 111796456A CN 202010654794 A CN202010654794 A CN 202010654794A CN 111796456 A CN111796456 A CN 111796456A
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- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 99
- 238000002161 passivation Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000002360 preparation method Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 13
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 24
- 230000001678 irradiating effect Effects 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 11
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 8
- 229910052733 gallium Inorganic materials 0.000 claims description 8
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 5
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 claims description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 4
- ZXTFQUMXDQLMBY-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo] ZXTFQUMXDQLMBY-UHFFFAOYSA-N 0.000 claims description 4
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 claims description 4
- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 239000011787 zinc oxide Substances 0.000 claims description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
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- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
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- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/1336—Illuminating devices
- G02F1/133602—Direct backlight
- G02F1/133603—Direct backlight with LEDs
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application provides a back plate and a preparation method of the back plate, wherein the preparation method comprises the following steps: preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on a substrate in sequence, wherein the first metal layer is patterned to form a first conductive member and a second conductive member, and the second metal layer is patterned to form a third conductive member and a fourth conductive member; etching the passivation layer and the insulating layer to form a first via hole, a second via hole, a third via hole, a fourth via hole and a fifth via hole corresponding to the fourth conductive member; preparing a connecting member made of a metal oxide semiconductor on the passivation layer, and patterning the connecting member to form a first connecting member and a second connecting member, wherein the first connecting member is connected with the first conductive member through a first via hole and connected with the third conductive member through a second via hole, and the second connecting member is connected with the second conductive member through the third via hole and connected with the fourth conductive member through a fourth via hole; the connecting member is irradiated with extreme ultraviolet light. The application reduces the contact resistance of the first metal layer and the second metal layer.
Description
Technical Field
The application relates to the technical field of display, in particular to a back plate and a preparation method of the back plate.
Background
In the existing AM Mini LED backplane, the backplane includes a chip bonding area, a driving circuit area, and a backlight bonding area, in the chip bonding area and the backlight bonding area, an Indium Tin Oxide (ITO) material is usually used to realize the overlapping of a first metal layer and a second metal layer, however, after the ITO overlapping layer is prepared, a copper bonding terminal in the chip bonding area is in an exposed state, so that the ITO cannot be annealed, the contact resistance of the first metal layer and the second metal layer is large, and the subsequent lighting effect is affected.
Therefore, the existing AM Mini LED backplane has a technical problem that the contact resistance between the first metal layer and the second metal layer is too large, and needs to be improved.
Disclosure of Invention
The embodiment of the application provides a backboard and a preparation method of the backboard, which are used for relieving the technical problem that contact resistance between a first metal layer and a second metal layer in the existing AM Mini LED backboard is overlarge.
The application provides a preparation method of a back plate, wherein the back plate comprises a chip binding area, a driving circuit area and a backlight source binding area, and the preparation method comprises the following steps:
providing a substrate;
sequentially preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on the substrate, wherein the first metal layer is patterned to form a first conductive member in the chip binding region and a second conductive member in the backlight source binding region, and the second metal layer is patterned to form a third conductive member in the chip binding region and a fourth conductive member in the backlight source binding region;
etching the passivation layer and the insulating layer to form a first via hole and a second via hole in the chip binding region, and a third via hole, a fourth via hole and a fifth via hole in the backlight source binding region, wherein the fifth via hole corresponds to the fourth conductive member;
preparing a connection member on the passivation layer, the connection member material including a metal oxide semiconductor, the connection member being patterned to form a first connection member and a second connection member, the first connection member being connected to the first conductive member through the first via and connected to the third conductive member through the second via, the second connection member being connected to the second conductive member through the third via and connected to the fourth conductive member through the fourth via;
irradiating the connection member with extreme ultraviolet light to decrease the connection member resistance.
In the method for manufacturing a back sheet of the present application, the step of manufacturing a connection member on the passivation layer, the connection member material including a metal oxide semiconductor, includes: and preparing a connecting member on the passivation layer, wherein the connecting member is made of at least one of indium tin oxide, indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide.
In the method for manufacturing a back sheet of the present application, the step of irradiating the connection member with extreme ultraviolet light to lower the resistance of the connection member includes: and irradiating the connecting component by using extreme ultraviolet light emitted by an extreme ultraviolet light source, wherein the irradiation power of the extreme ultraviolet light source is greater than a first preset value.
In the method for manufacturing a back sheet of the present application, the step of irradiating the connection member with extreme ultraviolet light to lower the resistance of the connection member includes: and irradiating the connecting component by using extreme ultraviolet light emitted by an extreme ultraviolet light source, wherein the irradiation time of the extreme ultraviolet light source is greater than a second preset value.
In the method for manufacturing a back sheet of the present application, after the step of irradiating the connecting member with extreme ultraviolet light to reduce the resistance of the connecting member, the method further includes: and binding the backlight source with the fourth conductive member through the fifth via hole.
In the preparation method of the backplane of the present application, the step of sequentially preparing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate further includes: an active layer is formed between the first metal layer and the second metal layer, or between the substrate and the first metal layer.
In the method for manufacturing a back sheet of the present application, the step of forming an active layer between the first metal layer and the second metal layer, or between the substrate and the first metal layer includes: forming the active layer, wherein the material of the active layer comprises polysilicon or metal oxide semiconductor.
In the method for manufacturing a backplane of the present application, the step of sequentially manufacturing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate includes: and in the driving circuit area, the first metal layer is patterned to form a grid electrode of a thin film transistor, and the second metal layer is patterned to form a source electrode and a drain electrode of the thin film transistor.
In the method for manufacturing a backplane of the present application, the step of sequentially manufacturing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate includes: preparing a first metal layer and a second metal layer, wherein the materials of the first metal layer and the second metal layer respectively comprise at least one of copper, molybdenum-copper alloy and molybdenum-aluminum alloy.
The application also provides a back plate which comprises a chip binding area, a driving circuit area and a backlight source binding area and is manufactured by adopting the preparation method of the back plate.
Has the advantages that: the application provides a back plate and a preparation method of the back plate, wherein the back plate comprises a chip binding area, a driving circuit area and a backlight source binding area, and the preparation method comprises the following steps: providing a substrate; sequentially preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on the substrate, wherein the first metal layer forms a first conductive member in the chip binding region, the second metal layer forms a second conductive member in the backlight source binding region, the second metal layer forms a third conductive member in the chip binding region, and the fourth conductive member in the backlight source binding region; etching the passivation layer and the insulating layer to form a first via hole and a second via hole in the chip binding region, and a third via hole, a fourth via hole and a fifth via hole in the backlight source binding region, wherein the fifth via hole corresponds to the fourth conductive member; preparing a connection member on the passivation layer, the connection member material including a metal oxide semiconductor, the connection member being patterned to form a first connection member and a second connection member, the first connection member being connected to the first conductive member through the first via and connected to the third conductive member through the second via, the second connection member being connected to the second conductive member through the third via and connected to the fourth conductive member through the fourth via; irradiating the connection member with extreme ultraviolet light to decrease the connection member resistance. According to the backlight module, the connecting component is irradiated by the extreme ultraviolet light, so that the contact resistance of the first metal layer and the second metal layer is reduced, and the lighting result cannot be influenced after the subsequent backlight source is bound with the backboard.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flow chart of a method for manufacturing a back plate according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a first stage of a method for manufacturing a back plate according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a second stage of a method for manufacturing a back plate according to an embodiment of the present application.
Fig. 4 is a third-stage schematic diagram of a method for manufacturing a back sheet according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a fourth stage of a method for manufacturing a back plate according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a fifth stage of a method for manufacturing a back plate according to an embodiment of the present application.
Fig. 7 is a schematic diagram of a sixth stage of a method for manufacturing a back plate according to an embodiment of the present application.
Fig. 8 is a schematic diagram of a seventh stage of a method for manufacturing a back plate according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of a backlight module according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
The embodiment of the application provides a backboard and a preparation method of the backboard, which are used for relieving the technical problem that contact resistance between a first metal layer and a second metal layer in the existing AM Mini LED backboard is overlarge.
As shown in fig. 1, the present application provides a method for manufacturing a backplane, where the backplane includes a chip bonding area, a driving circuit area, and a backlight bonding area, and the method includes:
s101: providing a substrate;
s102: sequentially preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on a substrate, wherein the first metal layer is patterned to form a first conductive component in a chip binding region and a second conductive component in a backlight source binding region, and the second metal layer is patterned to form a third conductive component in the chip binding region and a fourth conductive component in the backlight source binding region;
s103: etching the passivation layer and the insulating layer to form a first via hole and a second via hole in the chip binding region, and a third via hole, a fourth via hole and a fifth via hole in the backlight source binding region, wherein the fifth via hole corresponds to the fourth conductive member;
s104: preparing a connecting member on the passivation layer, wherein the connecting member is made of a metal oxide semiconductor, the connecting member is patterned to form a first connecting member and a second connecting member, the first connecting member is connected with the first conductive member through a first via hole and connected with the third conductive member through a second via hole, and the second connecting member is connected with the second conductive member through a third via hole and connected with the fourth conductive member through a fourth via hole;
s105: the connecting member is irradiated with extreme ultraviolet light to reduce the resistance of the connecting member.
The production method will be specifically described below with reference to fig. 2 to 8.
In S101, a substrate is provided. As shown in fig. 2, the material of the substrate 11 is typically glass.
In S102, a first metal layer, an insulating layer, a second metal layer, and a passivation layer are sequentially formed on a substrate, the first metal layer is patterned to form a first conductive member located in a chip bonding region and a second conductive member located in a backlight bonding region, and the second metal layer is patterned to form a third conductive member located in the chip bonding region and a fourth conductive member located in the backlight bonding region.
In this embodiment, taking a back plate as an example to form a bottom gate thin film transistor in the driving circuit region 200, as shown in fig. 3 and 4, a first metal layer, an insulating layer 13, an active layer 14, an ohmic contact layer 15, a second metal layer, and a passivation layer 17 are sequentially formed on a substrate 11.
A barrier layer and a buffer layer (not shown) are usually disposed between the substrate 11 and the first metal layer, the barrier layer is generally made of silicon oxide (SiOx) for blocking external impurity particles from entering the substrate 11 and isolating water and oxygen, the buffer layer is generally made of silicon nitride (SiNx), and the silicon nitride has strong ion blocking capability and good water and oxygen isolation capability, and can effectively prevent impurities from diffusing into the thin film transistor in a thermal process.
As shown in fig. 3, the first metal layer is patterned to form a gate 123 of the thin film transistor in the driving circuit region 200, a first conductive member 121 in the chip bonding region 100, and a second conductive member 122 in the backlight bonding region 300, where the first conductive member 121 and the second conductive member 122 may be various signal lines formed in the first metal layer. The material of the first metal layer includes at least one of copper, molybdenum-copper alloy, and molybdenum-aluminum alloy.
The material of the insulating layer 13 is typically at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure.
The active layer 14 includes three portions respectively formed in the chip bonding region 100, the driving circuit region 200, and the backlight bonding region 300, wherein the portion located in the driving circuit region 200 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions, and a channel region located between the source region and the drain region. The active layer 14 may be an amorphous silicon material, a polycrystalline silicon (a-Si) material, a metal oxide semiconductor material, or the like, wherein the metal oxide semiconductor may include at least one of indium tin oxide, indium gallium zinc oxide, indium zinc tin oxide, and indium gallium zinc tin oxide.
The ohmic contact layer 15 includes three portions respectively formed in the chip bonding area 100, the driving circuit area 200 and the backlight bonding area 300, wherein at the portion of the driving circuit area 200, the source and drain regions of the active layer 14 are respectively formed.
The second metal layer is patterned to form a source electrode 163 and a drain electrode 164 of the thin film transistor in the driving circuit region 200, a third conductive member 161 in the die bonding region 100, and a fourth conductive member 162 in the backlight bonding region 300, wherein the source electrode 163 and the drain electrode 164 are respectively connected to a source region and a drain region of the active layer 14, and the third conductive member 161 and the fourth conductive member 162 may be various signal lines formed in the second metal layer. The material of the first metal layer includes at least one of copper, molybdenum-copper alloy, and molybdenum-aluminum alloy.
As shown in fig. 4, a passivation layer 17 is formed on the second metal layer and covers the third conductive member 161, the fourth conductive member 162, the source electrode 163 and the drain electrode 164, and the material of the passivation layer 17 is typically at least one of silicon nitride (SiNx) and silicon oxide (SiOx), and may be a single-layer or multi-layer structure.
The above embodiment has been described with reference to a thin film transistor having a bottom gate structure, but the invention is not limited thereto, and a thin film transistor having a top gate structure may be formed, in which case the active layer 14 is formed between the substrate 11 and the first metal layer.
In S103, the passivation layer 17 and the insulating layer 13 are etched to form a first via hole and a second via hole in the chip bonding area 100, and a third via hole, a fourth via hole and a fifth via hole in the backlight bonding area 300, where the fifth via hole corresponds to the fourth conductive member 162.
As shown in fig. 4, after the passivation layer 17 is formed, the passivation layer 17 and the insulating layer 13 are etched to form a first via, a second via, a third via, a fourth via and a fifth via, where the first via penetrates through the passivation layer 17 and the insulating layer 13 and corresponds to the first conductive member 121, the second via penetrates only through the passivation layer 17 and corresponds to the third conductive member 161, the third via penetrates through the passivation layer 17 and the insulating layer 13 and corresponds to the second conductive member 122, and the fourth via and the fifth via penetrate only through the passivation layer 17 and correspond to the fourth conductive member 162, respectively.
In S104, a connection member is prepared on the passivation layer, the connection member material includes a metal oxide semiconductor, the connection member is patterned to form a first connection member 181 and a second connection member 182, the first connection member 181 is connected to the first conductive member 121 through a first via and is connected to the third conductive member 161 through a second via, and the second connection member 182 is connected to the second conductive member 122 through a third via and is connected to the fourth conductive member 162 through a fourth via.
As shown in fig. 5 and 6, a whole layer of connecting members is formed, and then a first connecting member 181 located in the chip bonding region 100 and a second connecting member 182 located in the backlight bonding region 300 are formed by patterning, in the chip bonding region 100, in order to meet the requirement of line change, the first conductive member 121 and the third conductive member 161 need to be overlapped in a deep and shallow hole manner, the first connecting member 181 is connected with the first conductive member 121 through a first via hole formed in the passivation layer 17 and the gate insulating layer 13, and is connected with the third conductive member 161 through a second via hole formed in the passivation layer 17, wherein the first via hole is a deep hole, and the second via hole is a shallow hole; similarly, in the backlight bonding area 300, in order to meet the line change requirement, the second conductive member 122 and the fourth conductive member 162 need to be lapped by deep and shallow holes, the second connecting member 182 is connected to the second conductive member 122 through a third via formed in the passivation layer 17 and the gate insulating layer 13, and is connected to the fourth conductive member 162 through a fourth via formed in the passivation layer 17, wherein the third via is a deep hole, and the fourth via is a shallow hole.
The material of the connecting member comprises at least one of indium tin oxide, indium gallium zinc tin oxide and indium gallium zinc tin oxide. After the connecting member is patterned to form the first connecting member 181 and the second connecting member 182, the fifth via hole is not filled, so that a partial region of the fourth conductive member 162 is exposed in the fifth via hole, and the exposed portion forms a binding terminal for binding the backlight.
In S105, the connection member is irradiated with extreme ultraviolet light to reduce the connection member resistance.
Extreme ultraviolet light refers to ultraviolet light which needs to be excited by electrifying a K pole of an ultraviolet tube and then emitted, and the wavelength of the ultraviolet light is 13.5 nanometers. As shown in fig. 7, since the valence band and the conduction band exist in the atomic orbitals of the semiconductor material, when the connection member is irradiated with high-energy extreme ultraviolet light 80 emitted from the extreme ultraviolet light source, electrons in the valence band transition into the conduction band, and holes are also formed in the valence band, so that the concentration of carriers is increased, the resistance of the connection member is reduced, the contact resistance of the first metal layer and the second metal layer is reduced, and the lighting result is not affected after the subsequent backlight source is bound to the backplane.
In one embodiment, the method of reducing the resistance of the connecting member is Extreme Ultraviolet (EUV) irradiation, and other similar treatment methods are possible, and the apparatus used for the emitter uv 80 is a Str apparatus, and other apparatuses having similar functions are also possible.
In one embodiment, the irradiation power of the euv light source is greater than a first preset value, and the first preset value may be 15W, or may be other values determined according to the material and thickness of the connecting member. The higher the irradiation power of the euv light source, the more the number of high-energy photons contained in the generated euv light 80 beam increases, the more transition behavior occurs when the connection member is irradiated with light, the more the number of carriers increases, and therefore the effect of reducing the resistance becomes more remarkable.
In one embodiment, the irradiation time of the euv light source is greater than a second preset value, which may be 10 minutes or other values determined according to the material and thickness of the connecting member. The longer the irradiation time of the euv light source, the more the number of high-energy photons contained in the generated euv light 80 beam increases, the more transition behavior occurs when the connection member is irradiated with light, the more the number of carriers increases, and therefore the effect of reducing the resistance becomes more remarkable.
In one embodiment, as shown in fig. 8, after S105, the method further includes the steps of: the backlight 20 is bound to the fourth conductive member 162 by the fifth via, and the backlight 20 is one or more Mini LED devices. The driving circuit area 200 is provided with a driving circuit, the driving circuit includes a plurality of thin film transistors, the backplane is bound with the chip on film COF in the chip binding area 100, the chip IC in the COF provides a driving signal for the driving circuit, and the driving circuit drives the Mini LED device to emit light after receiving the driving signal.
The application also provides a back plate which comprises a chip binding area, a driving circuit area and a backlight source binding area, and the back plate is prepared by the preparation method. By irradiating the connecting member with extreme ultraviolet light, the contact resistance of the first metal layer and the second metal layer is reduced, and therefore, the lighting result is not affected after the subsequent backlight source is bound with the backboard.
As shown in fig. 9, the present application further provides a backlight module, which includes a back plate 10, a backlight source 20, a rubber frame 30, a diffusion plate 40, a reflective sheet 50 and an optical film 60, wherein the backlight source 20 is bound to the back plate 10, the back plate 10 is made by any one of the above-mentioned preparation methods, and the backlight source 20 is a Mini LED device.
After the liquid crystal display panel is assembled subsequently, the liquid crystal display panel is fixed on a rubber frame 30 of a backlight module through a bonding layer, light 21 emitted by a backlight source 20 arranged on a back plate 10 in the backlight module irradiates the liquid crystal display panel after passing through a diffusion plate 40, a reflector plate 50 and an optical diaphragm 60, the light 21 is changed into polarized light through a lower polarizer of the liquid crystal display panel firstly, the liquid crystal panel inputs data signal voltages with different sizes to each pixel respectively through the switching action of a TFT (thin film transistor), liquid crystal molecules rotate under different voltages in different states, so that the transmission degrees of the polarized light are different, and finally the light brightness emitted through an upper polarizer is also different, so that the multi-gray-scale picture display is realized.
In a small-sized backlight module, only one back plate 10 is provided, in a middle-sized backlight module, a plurality of back plates 10 are used for splicing, for example, in an 8K product with a resolution of 7680x4320, a partition on a liquid crystal display panel usually includes a plurality of pixels, the backlight module is formed by splicing 12 back plates 10, all the backlight sources 20 form a plurality of backlight units, each back plate 10 includes 432 backlight units, each backlight unit includes 4 LED devices connected in series, a driving circuit in each back plate 10 drives the backlight sources 20 in the back plate individually, and controls light emission individually, and provides backlight for the pixels in each partition individually.
In the backlight module of the present application, before the backlight source 20 is bound with the backplate 10, the extreme ultraviolet light irradiation treatment is performed on the connecting member, so that the contact resistance of the first metal layer and the second metal layer can be reduced, the performance of the backplate 10 is improved, and further the performance of the backlight module is better.
According to the above embodiment:
the application provides a back plate and a preparation method of the back plate, wherein the back plate comprises a chip binding area, a driving circuit area and a backlight source binding area, and the preparation method comprises the following steps: providing a substrate; sequentially preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on a substrate, wherein the first metal layer forms a first conductive member in a chip binding area, the second metal layer forms a second conductive member in a backlight source binding area, the second metal layer forms a third conductive member in the chip binding area, and the fourth conductive member in the backlight source binding area; etching the passivation layer and the insulating layer to form a first via hole and a second via hole in the chip binding region, and a third via hole, a fourth via hole and a fifth via hole in the backlight source binding region, wherein the fifth via hole corresponds to the fourth conductive member; preparing a connecting member on the passivation layer, wherein the connecting member is made of a metal oxide semiconductor, the connecting member is patterned to form a first connecting member and a second connecting member, the first connecting member is connected with the first conductive member through a first via hole and connected with the third conductive member through a second via hole, and the second connecting member is connected with the second conductive member through a third via hole and connected with the fourth conductive member through a fourth via hole; the connecting member is irradiated with extreme ultraviolet light to reduce the resistance of the connecting member. According to the backlight module, the connecting component is irradiated by the extreme ultraviolet light, so that the contact resistance of the first metal layer and the second metal layer is reduced, and the lighting result cannot be influenced after the subsequent backlight source is bound with the backboard.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The backplane and the preparation method of the backplane provided by the embodiment of the present application are described in detail above, and the principle and the embodiment of the present application are explained by applying specific examples herein, and the description of the above embodiment is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A preparation method of a back plate comprises a chip binding area, a driving circuit area and a backlight source binding area, and is characterized by comprising the following steps:
providing a substrate;
sequentially preparing a first metal layer, an insulating layer, a second metal layer and a passivation layer on the substrate, wherein the first metal layer is patterned to form a first conductive member in the chip binding region and a second conductive member in the backlight source binding region, and the second metal layer is patterned to form a third conductive member in the chip binding region and a fourth conductive member in the backlight source binding region;
etching the passivation layer and the insulating layer to form a first via hole and a second via hole in the chip binding region, and a third via hole, a fourth via hole and a fifth via hole in the backlight source binding region, wherein the fifth via hole corresponds to the fourth conductive member;
preparing a connection member on the passivation layer, the connection member material including a metal oxide semiconductor, the connection member being patterned to form a first connection member and a second connection member, the first connection member being connected to the first conductive member through the first via and connected to the third conductive member through the second via, the second connection member being connected to the second conductive member through the third via and connected to the fourth conductive member through the fourth via;
irradiating the connection member with extreme ultraviolet light to decrease the connection member resistance.
2. The method of fabricating a backplane according to claim 1, wherein the step of fabricating a connection member on the passivation layer, the connection member material comprising a metal oxide semiconductor, comprises: and preparing a connecting member on the passivation layer, wherein the connecting member is made of at least one of indium tin oxide, indium gallium zinc oxide, indium zinc tin oxide and indium gallium zinc tin oxide.
3. The method of manufacturing a back sheet according to claim 1, wherein the step of irradiating the connection member with extreme ultraviolet light to lower the resistance of the connection member comprises: and irradiating the connecting component by using extreme ultraviolet light emitted by an extreme ultraviolet light source, wherein the irradiation power of the extreme ultraviolet light source is greater than a first preset value.
4. The method of manufacturing a back sheet according to claim 1, wherein the step of irradiating the connection member with extreme ultraviolet light to lower the resistance of the connection member comprises: and irradiating the connecting component by using extreme ultraviolet light emitted by an extreme ultraviolet light source, wherein the irradiation time of the extreme ultraviolet light source is greater than a second preset value.
5. The method of manufacturing a back sheet according to claim 1, wherein the step of irradiating the connection member with extreme ultraviolet light to lower the resistance of the connection member further comprises: and binding the backlight source with the fourth conductive member through the fifth via hole.
6. The method of preparing a backplane according to claim 1, wherein the step of sequentially preparing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate further comprises: an active layer is formed between the first metal layer and the second metal layer, or between the substrate and the first metal layer.
7. The method of preparing the back sheet of claim 6, wherein the step of forming an active layer between the first metal layer and the second metal layer, or between the substrate and the first metal layer, comprises: forming the active layer, wherein the material of the active layer comprises polysilicon or metal oxide semiconductor.
8. The method of preparing a backplane according to claim 6, wherein the step of sequentially preparing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate comprises: and in the driving circuit area, the first metal layer is patterned to form a grid electrode of a thin film transistor, and the second metal layer is patterned to form a source electrode and a drain electrode of the thin film transistor.
9. The method of preparing a backplane according to claim 1, wherein the step of sequentially preparing the first metal layer, the insulating layer, the second metal layer, and the passivation layer on the substrate comprises: preparing a first metal layer and a second metal layer, wherein the materials of the first metal layer and the second metal layer respectively comprise at least one of copper, molybdenum-copper alloy and molybdenum-aluminum alloy.
10. A back plate comprising a chip bonding area, a driving circuit area and a backlight bonding area, characterized in that it is manufactured by the method of any one of claims 1 to 9.
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Application publication date: 20201020 |