CN111699552B - 高频模块 - Google Patents
高频模块 Download PDFInfo
- Publication number
- CN111699552B CN111699552B CN201980012421.7A CN201980012421A CN111699552B CN 111699552 B CN111699552 B CN 111699552B CN 201980012421 A CN201980012421 A CN 201980012421A CN 111699552 B CN111699552 B CN 111699552B
- Authority
- CN
- China
- Prior art keywords
- frequency module
- bonding
- resin layer
- sealing resin
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
- H01Q1/526—Electromagnetic shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/142—HF devices
- H01L2924/1421—RF devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Geometry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明提供一种高频模块,能够在通过接合线形成部件间屏蔽件时,通过在接合的终点部配置突起电极,来使线的环形状稳定。高频模块(1a)具备:多层布线基板(2)、安装于该多层布线基板(2)的上表面(20a)的部件(3a~3d)、由多个接合线(11)形成为覆盖部件(3a)的屏蔽部件(13)、以及设置于各接合线(11)的接合的终点部(12b)的突起电极(5a)。通过在各接合线(11)的接合的终点部(12b)设置突起电极(5a),能够抑制在接合线(11)的第二接合侧的不期望的弯曲,能够容易地形成覆盖部件(3a)的侧面以及顶面的屏蔽部件(13)。
Description
技术领域
本发明涉及具备屏蔽件的高频模块。
背景技术
在通信终端装置等电子设备的母基板安装有各种高频模块。在这种高频模块中有利用密封树脂层密封安装于布线基板的部件的高频模块。另外,为了遮断对部件的噪声,也有利用屏蔽膜覆盖密封树脂层的表面的情况。在布线基板安装多个部件的情况下,有想要仅对特定的部件遮断噪声的情况,但在覆盖密封树脂层的表面的屏蔽膜中,难以仅对特定的部件进行屏蔽,设计自由度较低。因此,提出能够进行设计自由度较高的屏蔽部件的配置的高频模块。例如,如图11所示,在专利文献1所记载的高频模块100中,在布线基板101安装部件102。部件102被多个接合线103包围,通过这些接合线103,部件102被屏蔽。这样一来,只要仅在需要进行屏蔽的位置安装接合线103即可,所以屏蔽部件的设计自由度提高。
专利文献1:日本专利第5276169号公报(参照段落0021~0024、图3等)
然而,在以往的高频模块100中,以规定间隔排列接合线103的环来构成屏蔽结构,但接合线103容易变形。因此,若形成跨越部件102的形状的屏蔽部件,则需要增大接合线103的特别是作为线终点侧的第二接合侧的端部与部件102之间的距离。这是因为在线接合技术中,虽然在作为线起点侧的第一接合侧控制环形状比较容易,但在第二接合侧难以控制环形状。在第二接合侧难以控制环形状的理由是因为:在第二接合侧,难以将线弯曲并配置到部件附近,所以需要形成为延伸末端形状,这样一来,必须在远离部件的位置设定线的终点。因此,难以将跨越部件102的接合线103形成为不在部件102与线之间设置较大的距离且不使其与部件102接触。
发明内容
本发明是鉴于上述的课题而完成的,其目的在于提供屏蔽件的设计自由度较高且屏蔽特性不容易变动的、能够高密度地安装部件的高频模块。
为了实现上述的目的,本发明的高频模块的特征在于,具备:布线基板;部件,安装于上述布线基板的一个主面;第一突起电极,形成于上述布线基板的上述一个主面;以及屏蔽部件,由接合线形成,屏蔽上述部件,上述接合线的接合的起点部连接于上述布线基板的上述一个主面,上述接合线的接合的终点部连接于上述第一突起电极。
根据该构成,通过将接合线的接合的终点部与突起电极连接,能够控制第二接合侧的环形状,所以能够不与部件接触地形成屏蔽部件。另外,特别是在难以获取较小距离的接合的终点部,由于设置有突起电极,所以能够消除或者减小线的延伸末端部分,所以能够减小部件与接合线终点部之间的距离。因此,能够高密度地安装部件,能够使设计自由度提高。另外,在通过线接合安装部件的情况下,能够在与部件安装相同的工序中同时形成屏蔽部件。
另外,也可以通过金属镀覆形成上述第一突起电极。
另外,也可以由金属块形成上述第一突起电极。
另外,也可以:还具备形成于上述布线基板的上述一个主面的第二突起电极,上述起点部连接于上述第二突起电极。
根据该构成,能够将接合线与各突起电极接合,所以接合线的环形状的控制变得容易,并且能够在减小部件与接合线之间的距离且使接合线与部件的侧面不接触的情况下形成屏蔽部件。
另外,也可以通过金属镀覆形成上述第二突起电极。
另外,也可以由金属块形成上述第二突起电极。
另外,也可以:还具备密封上述部件的密封树脂层和设置于上述密封树脂层的表面的屏蔽膜,上述密封树脂层具有与上述布线基板的上述一个主面抵接的抵接面、与该抵接面对置的对置面、以及连接上述抵接面和上述对置面的边缘彼此的侧面,上述屏蔽膜至少覆盖上述密封树脂层的上述对置面和上述侧面,在上述密封树脂层的上述对置面处,上述接合线与上述屏蔽膜接触。
根据该构成,通过将接合线与屏蔽膜连接,能够使作为分隔屏蔽(CompartmentShield)的屏蔽性能提高。
另外,也可以:由多个上述接合线形成上述屏蔽部件,多个上述接合线配置成分别跨越上述部件。根据该构成,能够容易地形成覆盖部件的形状的屏蔽部件。
另外,也可以:由多个上述接合线形成上述屏蔽部件,多个上述接合线沿着上述部件的周围配置成包围上述部件。
根据该构成,能够在部件的周围配置屏蔽部件,所以能够使屏蔽性能提高。
另外,也可以:在从与上述布线基板的上述一个主面垂直的方向观察时,多个上述接合线中的一部分接合线分别大致平行地配置,多个上述接合线中的剩余的接合线分别大致平行地配置成与上述一部分接合线交叉。
根据该构成,能够容易地形成覆盖部件的侧面以及顶面的屏蔽部件。
另外,也可以:在从与上述布线基板的上述一个主面垂直的方向观察时,上述部件具有矩形形状,多个上述接合线在相对于上述部件的一边倾斜的方向上分别大致平行地配置。
根据该构成,能够通过较少的根数的接合线,遮断针对部件的来自所有方向的电磁波。
另外,也可以具备:布线基板;部件,安装于上述布线基板的一个主面;多个第一突起电极,形成于上述布线基板的上述一个主面;屏蔽部件,由多个接合线形成,屏蔽上述部件;密封树脂层,密封上述部件;以及屏蔽膜,设置于上述密封树脂层的表面,上述密封树脂层具有与上述布线基板的上述一个主面抵接的抵接面、与该抵接面对置的对置面、以及连接上述抵接面和上述对置面的边缘彼此的侧面,上述屏蔽膜至少覆盖上述密封树脂层的上述对置面和上述侧面,上述接合线的一端连接于上述第一突起电极,上述接合线的另一端从上述密封树脂层的上述对置面露出并与上述屏蔽膜连接。
根据该构成,通过将接合线与屏蔽膜连接,能够使作为分隔屏蔽的屏蔽性能进一步提高。
根据本发明,通过将接合线的接合的终点部与突起电极连接,能够控制第二接合侧的环形状,所以能够不与部件接触地形成屏蔽部件。另外,通过基于突起电极的环形状的控制,能够减小接合线与部件之间的距离,所以能够高密度地安装部件,能够使设计自由度提高。
附图说明
图1是本发明的第一实施方式所涉及的高频模块的剖视图。
图2是除去了图1的高频模块的屏蔽膜后的状态的俯视图。
图3是本发明的第二实施方式所涉及的高频模块的剖视图。
图4是除去了图3的高频模块的屏蔽膜后的状态的俯视图。
图5是表示图3的高频模块的突起电极的变形例的图。
图6是表示图3的高频模块的接合线的变形例的图。
图7是本发明的第三实施方式所涉及的高频模块的剖视图。
图8是除去了图7的高频模块的屏蔽膜后的状态的俯视图。
图9是本发明的第四实施方式所涉及的高频模块的剖视图。
图10是除去了图9的高频模块的屏蔽膜后的状态的俯视图。
图11是以往的高频模块的剖视图。
具体实施方式
<第一实施方式>
参照图1~图2对本发明的第一实施方式所涉及的高频模块1a进行说明。此外,图1是图2的A-A箭头方向的剖视图,图2是除去了高频模块1a的屏蔽膜6后的状态的俯视图。
如图1以及图2所示,该实施方式所涉及的高频模块1a具备多层布线基板2(相当于本发明的“布线基板”)、安装于该多层布线基板2的上表面20a的多个部件3a~3d、层叠于多层布线基板2的上表面20a的密封树脂层4、覆盖密封树脂层4的表面的屏蔽膜6、安装于多层布线基板2的上表面20a的多个第一突起电极5a、以及配置成跨越部件3a的接合线11,并且高频模块1a例如搭载于使用高频信号的电子设备的母基板等。
例如通过层叠由低温共烧陶瓷、高温共烧陶瓷、玻璃环氧树脂等形成的多个绝缘层2a~2d构成多层布线基板2。在多层布线基板2的上表面20a(相当于本发明的“布线基板的一个主面”)形成部件3a~3d的安装电极7。在多层布线基板2的下表面20b形成外部连接用的多个外部电极8。另外,在相邻的绝缘层2a~2d间分别形成各种内部布线电极9,并且在多层布线基板2的内部形成用于将形成于绝缘层2a~2d的内部布线电极9彼此连接的多个导通孔导体10。此外,安装电极7、外部电极8以及内部布线电极9均由Cu、Ag、Al等作为布线电极而一般被采用的金属来形成。另外,各导通孔导体10由Ag、Cu等金属形成。此外,也可以分别对各安装电极7、各外部电极8实施镀Ni/Au。
部件3a~3d由IC、PA(功率放大器)等半导体元件、芯片电感器、芯片电容器、芯片电阻等芯片部件构成,通过焊接等一般的表面安装技术安装于多层布线基板2。
密封树脂层4由环氧树脂等作为密封树脂而一般被采用的树脂形成,密封各部件3a~3d。另外,密封树脂层4具有与多层布线基板2抵接的下表面4b(相当于本发明的“密封树脂层的抵接面”)、与该下表面4b对置的上表面4a(相当于本发明的“密封树脂层的对置面”)、以及侧面4c。
第一突起电极5a由在表面进行镀Au而得到的金属部件等形成。例如在多层布线基板2为陶瓷基板的情况下,第一突起电极5a的形成方法是:在陶瓷层叠体(烧结前的多层布线基板2)的上表面压接在贯通孔填充了导电性膏体的树脂片,并对陶瓷层叠体进行烧制,从而烧掉树脂片,烧结导电性膏体,而在多层布线基板2的上表面20a形成金属突起物,并且通过对其实施镀Au,从而能够形成第一突起电极5a。或者,也可以配置进行了镀Au的金属块,也可以在金属块配置后实施镀Au。金属块也可以是金属销。另外,也可以使用通过电镀形成在布线基板上的金属突起物。在该情况下,能够位置精度良好并且以需要的最低限度的面积进行配置,并且由于不使用焊料等,所以也没有焊料闪光等的担心,因此优选。
另外,在多层布线基板2为玻璃环氧基板等树脂基板的情况下,能够如以下那样形成第一突起电极5a。首先,在多层布线基板2的上表面20a配置由板状的Cu等金属材料形成的电极基体,通过无电解电镀形成供电膜以覆盖该电极基体。通过无电解镀Cu形成供电膜。其后,给予电镀抗蚀剂膜以覆盖供电膜。能够从已知的光致抗蚀剂膜材料适当地选择电镀抗蚀剂膜。接下来,通过对电镀抗蚀剂膜进行曝光、显影,形成开口部以使供电膜的至少一部分露出,并且通过对开口部实施电镀,在多层布线基板2的上表面20a形成金属突起物。例如通过镀Cu形成金属突起物。其后,除去电镀抗蚀剂膜,并通过蚀刻除去露出的供电膜以及电极基体,之后在金属突起物形成镀Ni膜以及镀Au膜,从而能够形成第一突起电极5a。
第一突起电极5a的表面需要进行镀Au,但既可以如上述那样是镀Ni膜和镀Au膜的双层,也可以是镀Au膜单层。另外,也可以通过在多层布线基板2的上表面20a配置在表面实施了镀Au的金属块来形成第一突起电极5a。另外,也可以利用具有进行了镀Au的端子电极的部件作为第一突起电极5a。
接合线11是一般利用于线接合的Au、Al、Cu等金属线。如图2所示,多个接合线11配置成跨越部件3a,在从与多层布线基板2的上表面20a垂直的方向观察时,各接合线11相对于部件3a沿纵向和横向配置成格子状。通过像这样各接合线11配置成覆盖部件3a,形成针对部件3a的屏蔽部件13。另外,在该实施方式中,在作为接合的终点部12b(第二接合侧的端部)的端部配置有第一突起电极5a。对于接合线11而言,距离接合的终点部12b的高度越高,越难以控制环形状,特别是越有在第二接合侧弯曲允许量以上而与部件3a接触的担心。然而,在本实施方式中,在接合的终点部12b配置第一突起电极5a,从而接合线11的距离接合的终点部12b的高度变低,所以能够使环形状稳定。因此,能够不与部件3a接触并且在与部件3a的距离较小的位置配置接合线11。
屏蔽膜6覆盖密封树脂层4的表面(上表面4a、侧面4c)和多层布线基板2的侧面20c。另外,屏蔽膜6与在多层布线基板2的侧面20c露出的接地电极(图示省略)连接。
屏蔽膜6能够由具有层叠于密封树脂层4的上表面4a的紧贴膜、层叠于紧贴膜的导电膜、层叠于导电膜的保护膜的多层结构形成。这里,紧贴膜是为了提高导电膜与密封树脂层4之间的紧贴强度而设置的,例如能够由SUS等金属形成。导电膜是担负屏蔽膜6的实际的屏蔽功能的层,例如能够由Cu、Ag、Al中的任意一种金属形成。保护膜是为了防止导电膜腐蚀或者损伤而设置的,例如能够由SUS形成。
因此,根据上述的实施方式,通过在接合线11的第二接合侧的端部亦即接合的终点部12b配置第一突起电极5a,从而能够降低第二接合侧的接合线11的环的高度,能够进行环形状的控制。因此,能够防止接合线11在第二接合侧不期望地弯曲所引起的与部件3a的接触,所以能够容易地形成减小部件3a的侧面与接合线11之间的距离,并且跨越部件3a那样的屏蔽部件13。另外,由于能够减小部件3a与接合线11之间的距离,所以能够在多层布线基板2的上表面20a高密度地安装部件,能够使设计自由度提高。
另外,与仅利用金属销形成屏蔽件的情况相比较,能够容易地形成覆盖部件3a的顶面的屏蔽件。另外,在多层布线基板2的上表面20a有通过线接合进行安装的部件的情况下,能够在安装部件的工序中同时形成基于接合线11的屏蔽部件,能够降低制造成本。
<第二实施方式>
参照图3~图4对本发明的第二实施方式所涉及的高频模块1b进行说明。此外,图3是高频模块1b的剖视图,且是图4的B-B箭头方向的剖视图,图4是除去了高频模块1b的屏蔽膜6后的状态的俯视图。
如图3~图4所示,该实施方式所涉及的高频模块1b与参照图1~图2说明的第一实施方式的高频模块1a的不同之处在于在接合线11的接合的起点部12a(第一接合侧的端部)配置有第二突起电极5b。其它的构成与第一实施方式的高频模块1a相同,所以通过附加相同的附图标记而省略说明。
在该实施方式中,在接合线11的接合的起点部12a(第一接合侧的端部)配置第二突起电极5b,在接合线11的接合的终点部12b(第二接合侧的端部)配置第一突起电极5a。此外,能够与第一突起电极5a相同地形成第二突起电极5b。
根据该构成,除了与第一实施方式的高频模块1a相同的效果之外,还能够降低接合线11的距离起点部12a以及终点部12b的高度,所以环形状的控制变得更容易。
(突起电极的变形例)
在上述的实施方式中,多个第一突起电极5a以及多个第二突起电极5b配置在多层布线基板2的上表面20a,但也可以如图5所示的高频模块1c的突起电极5c那样,突起电极形成为框状。在该情况下,不需要形成多个突起电极,所以能够抑制制造成本。
(接合线的变形例)
在上述的实施方式中,在从与多层布线基板2的上表面20a垂直的方向观察时,多个接合线11相对于部件3a沿纵向和横向配置成格子状,但也可以如图6所示的高频模块1d那样,多个接合线11a相对于部件3a在倾斜方向上大致平行地排列。通过相对于部件3a在倾斜方向上配置接合线11a,能够同时遮断针对部件3a的来自纵向和横向的电磁波。因此,与配置成格子状的情况相比,能够以较少的根数的接合线11a使针对部件3a的屏蔽特性提高。
<第三实施方式>
参照图7~图8对本发明的第三实施方式所涉及的高频模块1e进行说明。此外,图7是高频模块1e的剖视图,且是图8的C-C箭头方向的剖视图,图8是除去了图7的屏蔽膜6后的状态的俯视图。
如图7以及图8所示,该实施方式所涉及的高频模块1e与参照图1~图2说明的第一实施方式的高频模块1a的不同之处在于在从与多层布线基板2的上表面20a垂直的方向观察时,多个接合线11b沿着部件3a的周围配置成包围部件3a这一点。其它的构成与第一实施方式的高频模块1a相同,所以通过附加相同的附图标记而省略说明。
在该实施方式中,接合的终点部12b(第二接合侧的端部)与第一突起电极5a连接且接合的起点部12a(第一接合侧的端部)与多层布线基板2的上表面20a连接的多个接合线11b沿着部件3a的周围配置,而包围部件3a的侧面,从而形成屏蔽部件。另外,在密封树脂层4的上表面4a,接合线11b与屏蔽膜6接触,所以形成覆盖部件3a的侧面以及上表面的屏蔽件。
根据该构成,通过致密地配置接合线11,能够使接合线11的环形状稳定。另外,接合线11在密封树脂层4的上表面4a与屏蔽膜6接触,所以能够遮断针对部件3a的侧面以及上表面的电磁波。
<第四实施方式>
参照图9~图10对本发明的第四实施方式所涉及的高频模块1f进行说明。此外,图9是高频模块1f的剖视图,且是图10的D-D箭头方向的剖视图,图10是除去了图9的屏蔽膜6后的状态的俯视图。
如图9以及图10所示,该实施方式所涉及的高频模块1f与参照图1~图2说明的第一实施方式的高频模块1a的不同之处在于接合线11c在密封树脂层4的上表面4a与屏蔽膜6连接这一点。其它的构成与第一实施方式的高频模块1a相同,所以通过附加相同的附图标记而省略说明。
将接合线配置成跨越部件3a并形成密封树脂层4,之后对密封树脂层4的上表面4a进行研磨,从而接合线11c从密封树脂层4的上表面4a露出。通过在该状态下形成屏蔽膜6,从而能够形成在密封树脂层4的上表面4a与屏蔽膜6连接的接合线11c。
根据该构成,能够通过接合线11c和屏蔽膜6形成覆盖部件3a的屏蔽部件13。另外,容易实现高频模块1f的低高度化。
此外,本发明并不限定于上述的各实施方式,只要不脱离其主旨,则除了上述以外还能够进行各种变更。例如,也可以组合上述的各实施方式、变形例的构成。
产业上的可利用性
另外,本发明能够应用于具备屏蔽件的各种高频模块。
附图标记说明:1a~1f…高频模块,2…多层布线基板(布线基板),3a~3d…部件,4…密封树脂层,5a~5c…突起电极(第一突起电极、第二突起电极),6…屏蔽膜,11、11a~11c…接合线,12a…接合的起点部,12b…接合的终点部,13…屏蔽部件。
Claims (12)
1.一种高频模块,其特征在于,具备:
布线基板;
部件,安装于上述布线基板的一个主面;
第一突起电极,形成于上述布线基板的上述一个主面;以及
屏蔽部件,由接合线形成,屏蔽上述部件,
上述接合线的接合的起点部连接于上述布线基板的上述一个主面,上述接合线的接合的终点部的前端连接于上述第一突起电极的同与上述布线基板的上述一个主面抵接的抵接面对置的对置面。
2.根据权利要求1所述的高频模块,其特征在于,
通过金属镀覆形成上述第一突起电极。
3.根据权利要求1所述的高频模块,其特征在于,
由金属块形成上述第一突起电极。
4.根据权利要求1所述的高频模块,其特征在于,
还具备形成于上述布线基板的上述一个主面的第二突起电极,
上述起点部连接于上述第二突起电极。
5.根据权利要求4所述的高频模块,其特征在于,
通过金属镀覆形成上述第二突起电极。
6.根据权利要求4所述的高频模块,其特征在于,
由金属块形成上述第二突起电极。
7. 根据权利要求1~6中的任意一项所述的高频模块,其特征在于,还具备:
密封树脂层,密封上述部件;以及
屏蔽膜,设置于上述密封树脂层的表面,
上述密封树脂层具有与上述布线基板的上述一个主面抵接的抵接面、与该抵接面对置的对置面、以及连接上述抵接面和上述对置面的边缘彼此的侧面,
上述屏蔽膜至少覆盖上述密封树脂层的上述对置面和上述侧面,
在上述密封树脂层的上述对置面处,上述接合线与上述屏蔽膜接触。
8.根据权利要求1~6中的任意一项所述的高频模块,其特征在于,
由多个上述接合线形成上述屏蔽部件,
多个上述接合线配置成分别跨越上述部件。
9.根据权利要求1~6中的任意一项所述的高频模块,其特征在于,
由多个上述接合线形成上述屏蔽部件,
多个上述接合线沿着上述部件的周围配置成包围上述部件。
10.根据权利要求8所述的高频模块,其特征在于,
在从与上述布线基板的上述一个主面垂直的方向观察时,
多个上述接合线中的一部分接合线分别大致平行地配置,
多个上述接合线中的剩余的接合线分别大致平行地配置成与上述一部分接合线交叉。
11.根据权利要求8所述的高频模块,其特征在于,
在从与上述布线基板的上述一个主面垂直的方向观察时,
上述部件具有矩形形状,
多个上述接合线在相对于上述部件的一边倾斜的方向上分别大致平行地配置。
12.一种高频模块,其特征在于,具备:
布线基板;
部件,安装于上述布线基板的一个主面;
多个第一突起电极,形成于上述布线基板的上述一个主面;
屏蔽部件,由多个接合线形成,屏蔽上述部件;
密封树脂层,密封上述部件;以及
屏蔽膜,设置于上述密封树脂层的表面,
上述密封树脂层具有与上述布线基板的上述一个主面抵接的抵接面、与该抵接面对置的对置面、以及连接上述抵接面和上述对置面的边缘彼此的侧面,
上述屏蔽膜至少覆盖上述密封树脂层的上述对置面和上述侧面,
上述接合线的一端侧的前端连接于上述第一突起电极的同与上述布线基板的上述一个主面抵接的抵接面对置的对置面,上述接合线的另一端从上述密封树脂层的上述对置面露出并与上述屏蔽膜连接。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018020691 | 2018-02-08 | ||
JP2018-020691 | 2018-02-08 | ||
PCT/JP2019/003966 WO2019156051A1 (ja) | 2018-02-08 | 2019-02-05 | 高周波モジュール |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111699552A CN111699552A (zh) | 2020-09-22 |
CN111699552B true CN111699552B (zh) | 2023-08-15 |
Family
ID=67549384
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201980012421.7A Active CN111699552B (zh) | 2018-02-08 | 2019-02-05 | 高频模块 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11476172B2 (zh) |
JP (1) | JP6950757B2 (zh) |
CN (1) | CN111699552B (zh) |
WO (1) | WO2019156051A1 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11239178B2 (en) * | 2018-11-29 | 2022-02-01 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structures and methods of manufacturing the same |
WO2021039325A1 (ja) | 2019-08-23 | 2021-03-04 | 株式会社村田製作所 | モジュール |
WO2021060161A1 (ja) * | 2019-09-27 | 2021-04-01 | 株式会社村田製作所 | モジュール |
US11450618B2 (en) | 2020-01-17 | 2022-09-20 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of compartment shielding using bond wires |
JP7282048B2 (ja) * | 2020-02-12 | 2023-05-26 | 三菱電機株式会社 | 電力用半導体装置およびその製造方法 |
CN219085958U (zh) * | 2020-06-11 | 2023-05-26 | 株式会社村田制作所 | 模块 |
CN219108105U (zh) * | 2020-06-16 | 2023-05-30 | 株式会社村田制作所 | 模块 |
US12055633B2 (en) * | 2020-08-25 | 2024-08-06 | Lumentum Operations Llc | Package for a time of flight device |
WO2022044504A1 (ja) * | 2020-08-31 | 2022-03-03 | 株式会社村田製作所 | 回路モジュール及びサブモジュールの製造方法 |
CN114256211B (zh) * | 2020-09-25 | 2022-10-18 | 荣耀终端有限公司 | 封装体及其制备方法、终端和电子设备 |
CN220189619U (zh) * | 2020-10-22 | 2023-12-15 | 株式会社村田制作所 | 电路模块 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1032351A (ja) * | 1996-07-17 | 1998-02-03 | Toshiba Corp | 発光装置 |
CN1376554A (zh) * | 2001-03-22 | 2002-10-30 | 松下电器产业株式会社 | 激光加工用电介质基板与其加工方法及半导体组件与其制造方法 |
JP2007258670A (ja) * | 2006-02-24 | 2007-10-04 | Yamaha Corp | 半導体装置 |
JP2009033114A (ja) * | 2007-06-29 | 2009-02-12 | Tdk Corp | 電子モジュール、及び電子モジュールの製造方法 |
JP2010258295A (ja) * | 2009-04-27 | 2010-11-11 | Sharp Corp | 高周波モジュール、その製造方法、および電子機器 |
JP2017084898A (ja) * | 2015-10-26 | 2017-05-18 | 株式会社村田製作所 | 高周波モジュール |
WO2021251219A1 (ja) * | 2020-06-11 | 2021-12-16 | 株式会社村田製作所 | モジュール |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3012868A (en) | 1957-12-16 | 1961-12-12 | Dow Chemical Co | Enhanced organic explosives |
JP2001044305A (ja) * | 1999-07-29 | 2001-02-16 | Mitsui High Tec Inc | 半導体装置 |
JP4057968B2 (ja) * | 2003-07-29 | 2008-03-05 | 京セラ株式会社 | 電子装置 |
JP3838571B2 (ja) * | 2003-08-14 | 2006-10-25 | 松下電器産業株式会社 | 固体撮像装置の製造方法 |
US7088009B2 (en) * | 2003-08-20 | 2006-08-08 | Freescale Semiconductor, Inc. | Wirebonded assemblage method and apparatus |
JP4083142B2 (ja) | 2004-06-02 | 2008-04-30 | 富士通株式会社 | 半導体装置 |
EP2752872B1 (en) | 2008-07-31 | 2018-06-27 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture thereof |
US8012868B1 (en) * | 2008-12-15 | 2011-09-06 | Amkor Technology Inc | Semiconductor device having EMI shielding and method therefor |
KR20120026909A (ko) * | 2010-09-10 | 2012-03-20 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
JP5327299B2 (ja) * | 2011-09-09 | 2013-10-30 | オムロン株式会社 | 半導体装置及びマイクロフォン |
KR101835483B1 (ko) * | 2011-12-09 | 2018-03-08 | 삼성전자주식회사 | 멀티-칩 패키지 및 그의 제조 방법 |
CN107078125B (zh) | 2015-01-21 | 2020-06-02 | 株式会社村田制作所 | 功率放大模块 |
US10043763B2 (en) * | 2015-12-19 | 2018-08-07 | Skyworks Solutions, Inc. | Shielded lead frame packages |
KR101815754B1 (ko) * | 2016-03-10 | 2018-01-08 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 |
US10134686B2 (en) * | 2016-09-30 | 2018-11-20 | Avago Technologies International Sales Pte. Limited | Systems and methods for providing electromagnetic interference (EMI) compartment shielding for components disposed inside of system electronic packages |
-
2019
- 2019-02-05 JP JP2019570744A patent/JP6950757B2/ja active Active
- 2019-02-05 WO PCT/JP2019/003966 patent/WO2019156051A1/ja active Application Filing
- 2019-02-05 CN CN201980012421.7A patent/CN111699552B/zh active Active
-
2020
- 2020-08-05 US US16/985,411 patent/US11476172B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1032351A (ja) * | 1996-07-17 | 1998-02-03 | Toshiba Corp | 発光装置 |
CN1376554A (zh) * | 2001-03-22 | 2002-10-30 | 松下电器产业株式会社 | 激光加工用电介质基板与其加工方法及半导体组件与其制造方法 |
JP2007258670A (ja) * | 2006-02-24 | 2007-10-04 | Yamaha Corp | 半導体装置 |
JP2009033114A (ja) * | 2007-06-29 | 2009-02-12 | Tdk Corp | 電子モジュール、及び電子モジュールの製造方法 |
JP2010258295A (ja) * | 2009-04-27 | 2010-11-11 | Sharp Corp | 高周波モジュール、その製造方法、および電子機器 |
JP2017084898A (ja) * | 2015-10-26 | 2017-05-18 | 株式会社村田製作所 | 高周波モジュール |
WO2021251219A1 (ja) * | 2020-06-11 | 2021-12-16 | 株式会社村田製作所 | モジュール |
Also Published As
Publication number | Publication date |
---|---|
US20200365476A1 (en) | 2020-11-19 |
WO2019156051A1 (ja) | 2019-08-15 |
US11476172B2 (en) | 2022-10-18 |
JPWO2019156051A1 (ja) | 2021-01-07 |
CN111699552A (zh) | 2020-09-22 |
JP6950757B2 (ja) | 2021-10-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111699552B (zh) | 高频模块 | |
JP6753514B2 (ja) | 高周波モジュール | |
CN106171049B (zh) | 电子设备 | |
JP6837432B2 (ja) | 高周波モジュール | |
EP1965615A1 (en) | Module having built-in component and method for fabricating such module | |
EP2738798A1 (en) | Package for accommodating semiconductor element, semiconductor device provided with same, and electronic device | |
US8363422B2 (en) | Electronic component module and method for manufacturing the same | |
US9510461B2 (en) | Electric component module and method of manufacturing the same | |
US11348894B2 (en) | High-frequency module | |
WO2021039325A1 (ja) | モジュール | |
EP3451371A1 (en) | Substrate for mounting electronic component, electronic device and electronic module | |
KR20060095092A (ko) | 고주파 모듈 부품 및 그 제조 방법 | |
CN111696946A (zh) | 半导体封装、半导体器件以及用于制造半导体器件的方法 | |
US10219380B2 (en) | Electronic device module and manufacturing method thereof | |
CN111512432B (zh) | 布线基板、电子装置以及电子模块 | |
CN210129511U (zh) | 高频模块 | |
KR100516815B1 (ko) | 반도체장치 | |
JP6495701B2 (ja) | 電子部品収納用パッケージおよびその製造方法 | |
US20230225092A1 (en) | Electronic component module and method of manufacturing electronic component module | |
US12113030B2 (en) | Electronic component module comprising shield and sealing resin covering electronic components | |
JP2013110299A (ja) | 複合モジュール | |
CN107710901B (zh) | 高频模块及其制造方法 | |
CN118824972A (zh) | 半导体装置及其制造方法 | |
JP2006344631A (ja) | 部品内蔵基板 | |
CN116190325A (zh) | 电子封装模块及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |